2019-06-04 15:11:33 +07:00
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// SPDX-License-Identifier: GPL-2.0-only
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2014-04-16 14:24:44 +07:00
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/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
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2018-04-13 18:33:49 +07:00
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#include <linux/delay.h>
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2014-04-16 14:24:44 +07:00
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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2018-12-13 03:38:54 +07:00
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#include <linux/of_device.h>
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2014-04-16 14:24:44 +07:00
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2015-03-12 21:48:02 +07:00
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#include <linux/sort.h>
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#include <soc/tegra/fuse.h>
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2014-04-16 14:24:44 +07:00
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#include "mc.h"
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#define MC_INTSTATUS 0x000
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#define MC_INTMASK 0x004
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#define MC_ERR_STATUS 0x08
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#define MC_ERR_STATUS_TYPE_SHIFT 28
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#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
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#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
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#define MC_ERR_STATUS_READABLE (1 << 27)
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#define MC_ERR_STATUS_WRITABLE (1 << 26)
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#define MC_ERR_STATUS_NONSECURE (1 << 25)
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#define MC_ERR_STATUS_ADR_HI_SHIFT 20
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#define MC_ERR_STATUS_ADR_HI_MASK 0x3
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#define MC_ERR_STATUS_SECURITY (1 << 17)
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#define MC_ERR_STATUS_RW (1 << 16)
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#define MC_ERR_ADR 0x0c
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2018-12-13 03:38:53 +07:00
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#define MC_GART_ERROR_REQ 0x30
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2018-04-10 02:28:31 +07:00
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#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
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#define MC_SECURITY_VIOLATION_STATUS 0x74
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2014-04-16 14:24:44 +07:00
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#define MC_EMEM_ARB_CFG 0x90
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
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#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
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#define MC_EMEM_ARB_MISC0 0xd8
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2015-03-12 21:48:02 +07:00
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#define MC_EMEM_ADR_CFG 0x54
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#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
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2019-04-12 05:12:47 +07:00
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#define MC_TIMING_CONTROL 0xfc
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#define MC_TIMING_UPDATE BIT(0)
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2014-04-16 14:24:44 +07:00
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static const struct of_device_id tegra_mc_of_match[] = {
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2018-04-10 02:28:31 +07:00
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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2018-12-13 03:38:52 +07:00
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{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
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2018-04-10 02:28:31 +07:00
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#endif
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2014-04-16 14:24:44 +07:00
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
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2014-11-07 22:10:41 +07:00
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#endif
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#ifdef CONFIG_ARCH_TEGRA_132_SOC
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{ .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
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2015-03-23 16:45:12 +07:00
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#endif
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#ifdef CONFIG_ARCH_TEGRA_210_SOC
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{ .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
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2014-04-16 14:24:44 +07:00
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#endif
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
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2019-04-11 15:48:25 +07:00
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static int tegra_mc_block_dma_common(struct tegra_mc *mc,
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2018-04-13 18:33:49 +07:00
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) | BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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2019-04-11 15:48:25 +07:00
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static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
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2018-04-13 18:33:49 +07:00
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const struct tegra_mc_reset *rst)
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{
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return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
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}
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2019-04-11 15:48:25 +07:00
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static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
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2018-04-13 18:33:49 +07:00
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const struct tegra_mc_reset *rst)
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{
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unsigned long flags;
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u32 value;
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spin_lock_irqsave(&mc->lock, flags);
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value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
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mc_writel(mc, value, rst->control);
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spin_unlock_irqrestore(&mc->lock, flags);
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return 0;
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}
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2019-04-11 15:48:25 +07:00
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static int tegra_mc_reset_status_common(struct tegra_mc *mc,
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2018-04-13 18:33:49 +07:00
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const struct tegra_mc_reset *rst)
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{
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return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
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}
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2019-04-11 15:48:25 +07:00
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const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
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.block_dma = tegra_mc_block_dma_common,
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.dma_idling = tegra_mc_dma_idling_common,
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.unblock_dma = tegra_mc_unblock_dma_common,
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.reset_status = tegra_mc_reset_status_common,
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2018-04-13 18:33:49 +07:00
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};
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static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
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{
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return container_of(rcdev, struct tegra_mc, reset);
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}
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static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
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unsigned long id)
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{
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unsigned int i;
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for (i = 0; i < mc->soc->num_resets; i++)
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if (mc->soc->resets[i].id == id)
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return &mc->soc->resets[i];
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return NULL;
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}
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static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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int retries = 500;
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int err;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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if (rst_ops->block_dma) {
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/* block clients DMA requests */
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err = rst_ops->block_dma(mc, rst);
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if (err) {
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2018-12-13 03:38:59 +07:00
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dev_err(mc->dev, "failed to block %s DMA: %d\n",
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2018-04-13 18:33:49 +07:00
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rst->name, err);
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return err;
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}
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}
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if (rst_ops->dma_idling) {
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/* wait for completion of the outstanding DMA requests */
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while (!rst_ops->dma_idling(mc, rst)) {
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if (!retries--) {
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2018-12-13 03:38:59 +07:00
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dev_err(mc->dev, "failed to flush %s DMA\n",
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2018-04-13 18:33:49 +07:00
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rst->name);
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return -EBUSY;
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}
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usleep_range(10, 100);
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}
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}
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if (rst_ops->hotreset_assert) {
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/* clear clients DMA requests sitting before arbitration */
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err = rst_ops->hotreset_assert(mc, rst);
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if (err) {
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2018-12-13 03:38:59 +07:00
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dev_err(mc->dev, "failed to hot reset %s: %d\n",
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2018-04-13 18:33:49 +07:00
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rst->name, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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int err;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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if (rst_ops->hotreset_deassert) {
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/* take out client from hot reset */
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err = rst_ops->hotreset_deassert(mc, rst);
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if (err) {
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2018-12-13 03:38:59 +07:00
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dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
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2018-04-13 18:33:49 +07:00
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rst->name, err);
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return err;
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}
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}
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if (rst_ops->unblock_dma) {
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/* allow new DMA requests to proceed to arbitration */
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err = rst_ops->unblock_dma(mc, rst);
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if (err) {
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2018-12-13 03:38:59 +07:00
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dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
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2018-04-13 18:33:49 +07:00
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rst->name, err);
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return err;
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}
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}
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return 0;
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}
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static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct tegra_mc *mc = reset_to_mc(rcdev);
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const struct tegra_mc_reset_ops *rst_ops;
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const struct tegra_mc_reset *rst;
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rst = tegra_mc_reset_find(mc, id);
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if (!rst)
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return -ENODEV;
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rst_ops = mc->soc->reset_ops;
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if (!rst_ops)
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return -ENODEV;
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return rst_ops->reset_status(mc, rst);
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}
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static const struct reset_control_ops tegra_mc_reset_ops = {
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.assert = tegra_mc_hotreset_assert,
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.deassert = tegra_mc_hotreset_deassert,
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.status = tegra_mc_hotreset_status,
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};
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static int tegra_mc_reset_setup(struct tegra_mc *mc)
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{
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int err;
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mc->reset.ops = &tegra_mc_reset_ops;
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mc->reset.owner = THIS_MODULE;
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mc->reset.of_node = mc->dev->of_node;
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mc->reset.of_reset_n_cells = 1;
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mc->reset.nr_resets = mc->soc->num_resets;
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err = reset_controller_register(&mc->reset);
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if (err < 0)
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return err;
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return 0;
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}
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2014-04-16 14:24:44 +07:00
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static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
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{
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unsigned long long tick;
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unsigned int i;
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u32 value;
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/* compute the number of MC clock cycles per tick */
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2019-04-12 05:12:48 +07:00
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tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
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2014-04-16 14:24:44 +07:00
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do_div(tick, NSEC_PER_SEC);
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2019-04-12 05:12:49 +07:00
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value = mc_readl(mc, MC_EMEM_ARB_CFG);
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2014-04-16 14:24:44 +07:00
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value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
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value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
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2019-04-12 05:12:49 +07:00
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mc_writel(mc, value, MC_EMEM_ARB_CFG);
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2014-04-16 14:24:44 +07:00
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/* write latency allowance defaults */
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for (i = 0; i < mc->soc->num_clients; i++) {
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const struct tegra_mc_la *la = &mc->soc->clients[i].la;
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u32 value;
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2019-04-12 05:12:49 +07:00
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value = mc_readl(mc, la->reg);
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2014-04-16 14:24:44 +07:00
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value &= ~(la->mask << la->shift);
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value |= (la->def & la->mask) << la->shift;
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2019-04-12 05:12:49 +07:00
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mc_writel(mc, value, la->reg);
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2014-04-16 14:24:44 +07:00
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}
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2019-04-12 05:12:47 +07:00
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/* latch new values */
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2019-04-12 05:12:49 +07:00
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mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
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2019-04-12 05:12:47 +07:00
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2014-04-16 14:24:44 +07:00
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return 0;
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}
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2015-03-12 21:48:02 +07:00
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void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
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{
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unsigned int i;
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struct tegra_mc_timing *timing = NULL;
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for (i = 0; i < mc->num_timings; i++) {
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if (mc->timings[i].rate == rate) {
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timing = &mc->timings[i];
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break;
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}
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}
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if (!timing) {
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dev_err(mc->dev, "no memory timing registered for rate %lu\n",
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rate);
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return;
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}
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for (i = 0; i < mc->soc->num_emem_regs; ++i)
|
|
|
|
mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
|
|
|
|
{
|
|
|
|
u8 dram_count;
|
|
|
|
|
|
|
|
dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
|
|
|
|
dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
|
|
|
|
dram_count++;
|
|
|
|
|
|
|
|
return dram_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int load_one_timing(struct tegra_mc *mc,
|
|
|
|
struct tegra_mc_timing *timing,
|
|
|
|
struct device_node *node)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
err = of_property_read_u32(node, "clock-frequency", &tmp);
|
|
|
|
if (err) {
|
|
|
|
dev_err(mc->dev,
|
2018-08-28 07:57:23 +07:00
|
|
|
"timing %pOFn: failed to read rate\n", node);
|
2015-03-12 21:48:02 +07:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
timing->rate = tmp;
|
|
|
|
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
|
|
|
|
sizeof(u32), GFP_KERNEL);
|
|
|
|
if (!timing->emem_data)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
err = of_property_read_u32_array(node, "nvidia,emem-configuration",
|
|
|
|
timing->emem_data,
|
|
|
|
mc->soc->num_emem_regs);
|
|
|
|
if (err) {
|
|
|
|
dev_err(mc->dev,
|
2018-08-28 07:57:23 +07:00
|
|
|
"timing %pOFn: failed to read EMEM configuration\n",
|
|
|
|
node);
|
2015-03-12 21:48:02 +07:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int load_timings(struct tegra_mc *mc, struct device_node *node)
|
|
|
|
{
|
|
|
|
struct device_node *child;
|
|
|
|
struct tegra_mc_timing *timing;
|
|
|
|
int child_count = of_get_child_count(node);
|
|
|
|
int i = 0, err;
|
|
|
|
|
|
|
|
mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!mc->timings)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mc->num_timings = child_count;
|
|
|
|
|
|
|
|
for_each_child_of_node(node, child) {
|
|
|
|
timing = &mc->timings[i++];
|
|
|
|
|
|
|
|
err = load_one_timing(mc, timing, child);
|
2016-01-26 00:23:07 +07:00
|
|
|
if (err) {
|
|
|
|
of_node_put(child);
|
2015-03-12 21:48:02 +07:00
|
|
|
return err;
|
2016-01-26 00:23:07 +07:00
|
|
|
}
|
2015-03-12 21:48:02 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_mc_setup_timings(struct tegra_mc *mc)
|
|
|
|
{
|
|
|
|
struct device_node *node;
|
|
|
|
u32 ram_code, node_ram_code;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
ram_code = tegra_read_ram_code();
|
|
|
|
|
|
|
|
mc->num_timings = 0;
|
|
|
|
|
|
|
|
for_each_child_of_node(mc->dev->of_node, node) {
|
|
|
|
err = of_property_read_u32(node, "nvidia,ram-code",
|
|
|
|
&node_ram_code);
|
2015-10-10 00:47:40 +07:00
|
|
|
if (err || (node_ram_code != ram_code))
|
2015-03-12 21:48:02 +07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
err = load_timings(mc, node);
|
2016-01-26 00:23:07 +07:00
|
|
|
of_node_put(node);
|
2015-03-12 21:48:02 +07:00
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mc->num_timings == 0)
|
|
|
|
dev_warn(mc->dev,
|
|
|
|
"no memory timings for RAM code %u registered\n",
|
|
|
|
ram_code);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-16 14:24:44 +07:00
|
|
|
static const char *const status_names[32] = {
|
|
|
|
[ 1] = "External interrupt",
|
|
|
|
[ 6] = "EMEM address decode error",
|
2018-04-10 02:28:31 +07:00
|
|
|
[ 7] = "GART page fault",
|
2014-04-16 14:24:44 +07:00
|
|
|
[ 8] = "Security violation",
|
|
|
|
[ 9] = "EMEM arbitration error",
|
|
|
|
[10] = "Page fault",
|
|
|
|
[11] = "Invalid APB ASID update",
|
|
|
|
[12] = "VPR violation",
|
|
|
|
[13] = "Secure carveout violation",
|
|
|
|
[16] = "MTS carveout violation",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const char *const error_names[8] = {
|
|
|
|
[2] = "EMEM decode error",
|
|
|
|
[3] = "TrustZone violation",
|
|
|
|
[4] = "Carveout violation",
|
|
|
|
[6] = "SMMU translation error",
|
|
|
|
};
|
|
|
|
|
|
|
|
static irqreturn_t tegra_mc_irq(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct tegra_mc *mc = data;
|
2018-04-10 02:28:29 +07:00
|
|
|
unsigned long status;
|
2014-04-16 14:24:44 +07:00
|
|
|
unsigned int bit;
|
|
|
|
|
|
|
|
/* mask all interrupts to avoid flooding */
|
2018-04-10 02:28:29 +07:00
|
|
|
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
|
2018-04-10 02:28:27 +07:00
|
|
|
if (!status)
|
|
|
|
return IRQ_NONE;
|
2014-04-16 14:24:44 +07:00
|
|
|
|
|
|
|
for_each_set_bit(bit, &status, 32) {
|
|
|
|
const char *error = status_names[bit] ?: "unknown";
|
|
|
|
const char *client = "unknown", *desc;
|
|
|
|
const char *direction, *secure;
|
|
|
|
phys_addr_t addr = 0;
|
|
|
|
unsigned int i;
|
|
|
|
char perm[7];
|
|
|
|
u8 id, type;
|
|
|
|
u32 value;
|
|
|
|
|
|
|
|
value = mc_readl(mc, MC_ERR_STATUS);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PHYS_ADDR_T_64BIT
|
|
|
|
if (mc->soc->num_address_bits > 32) {
|
|
|
|
addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
|
|
|
|
MC_ERR_STATUS_ADR_HI_MASK);
|
|
|
|
addr <<= 32;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
if (value & MC_ERR_STATUS_RW)
|
|
|
|
direction = "write";
|
|
|
|
else
|
|
|
|
direction = "read";
|
|
|
|
|
|
|
|
if (value & MC_ERR_STATUS_SECURITY)
|
|
|
|
secure = "secure ";
|
|
|
|
else
|
|
|
|
secure = "";
|
|
|
|
|
2015-06-05 02:33:48 +07:00
|
|
|
id = value & mc->soc->client_id_mask;
|
2014-04-16 14:24:44 +07:00
|
|
|
|
|
|
|
for (i = 0; i < mc->soc->num_clients; i++) {
|
|
|
|
if (mc->soc->clients[i].id == id) {
|
|
|
|
client = mc->soc->clients[i].name;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
type = (value & MC_ERR_STATUS_TYPE_MASK) >>
|
|
|
|
MC_ERR_STATUS_TYPE_SHIFT;
|
|
|
|
desc = error_names[type];
|
|
|
|
|
|
|
|
switch (value & MC_ERR_STATUS_TYPE_MASK) {
|
|
|
|
case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
|
|
|
|
perm[0] = ' ';
|
|
|
|
perm[1] = '[';
|
|
|
|
|
|
|
|
if (value & MC_ERR_STATUS_READABLE)
|
|
|
|
perm[2] = 'R';
|
|
|
|
else
|
|
|
|
perm[2] = '-';
|
|
|
|
|
|
|
|
if (value & MC_ERR_STATUS_WRITABLE)
|
|
|
|
perm[3] = 'W';
|
|
|
|
else
|
|
|
|
perm[3] = '-';
|
|
|
|
|
|
|
|
if (value & MC_ERR_STATUS_NONSECURE)
|
|
|
|
perm[4] = '-';
|
|
|
|
else
|
|
|
|
perm[4] = 'S';
|
|
|
|
|
|
|
|
perm[5] = ']';
|
|
|
|
perm[6] = '\0';
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
perm[0] = '\0';
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
value = mc_readl(mc, MC_ERR_ADR);
|
|
|
|
addr |= value;
|
|
|
|
|
|
|
|
dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
|
|
|
|
client, secure, direction, &addr, error,
|
|
|
|
desc, perm);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear interrupts */
|
|
|
|
mc_writel(mc, status, MC_INTSTATUS);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2018-04-10 02:28:31 +07:00
|
|
|
static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct tegra_mc *mc = data;
|
|
|
|
unsigned long status;
|
|
|
|
unsigned int bit;
|
|
|
|
|
|
|
|
/* mask all interrupts to avoid flooding */
|
|
|
|
status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
|
|
|
|
if (!status)
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
for_each_set_bit(bit, &status, 32) {
|
|
|
|
const char *direction = "read", *secure = "";
|
|
|
|
const char *error = status_names[bit];
|
|
|
|
const char *client, *desc;
|
|
|
|
phys_addr_t addr;
|
|
|
|
u32 value, reg;
|
|
|
|
u8 id, type;
|
|
|
|
|
|
|
|
switch (BIT(bit)) {
|
|
|
|
case MC_INT_DECERR_EMEM:
|
|
|
|
reg = MC_DECERR_EMEM_OTHERS_STATUS;
|
|
|
|
value = mc_readl(mc, reg);
|
|
|
|
|
|
|
|
id = value & mc->soc->client_id_mask;
|
|
|
|
desc = error_names[2];
|
|
|
|
|
|
|
|
if (value & BIT(31))
|
|
|
|
direction = "write";
|
|
|
|
break;
|
|
|
|
|
|
|
|
case MC_INT_INVALID_GART_PAGE:
|
2018-12-13 03:38:53 +07:00
|
|
|
reg = MC_GART_ERROR_REQ;
|
|
|
|
value = mc_readl(mc, reg);
|
|
|
|
|
|
|
|
id = (value >> 1) & mc->soc->client_id_mask;
|
|
|
|
desc = error_names[2];
|
|
|
|
|
|
|
|
if (value & BIT(0))
|
|
|
|
direction = "write";
|
|
|
|
break;
|
2018-04-10 02:28:31 +07:00
|
|
|
|
|
|
|
case MC_INT_SECURITY_VIOLATION:
|
|
|
|
reg = MC_SECURITY_VIOLATION_STATUS;
|
|
|
|
value = mc_readl(mc, reg);
|
|
|
|
|
|
|
|
id = value & mc->soc->client_id_mask;
|
|
|
|
type = (value & BIT(30)) ? 4 : 3;
|
|
|
|
desc = error_names[type];
|
|
|
|
secure = "secure ";
|
|
|
|
|
|
|
|
if (value & BIT(31))
|
|
|
|
direction = "write";
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
client = mc->soc->clients[id].name;
|
|
|
|
addr = mc_readl(mc, reg + sizeof(u32));
|
|
|
|
|
|
|
|
dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s)\n",
|
|
|
|
client, secure, direction, &addr, error,
|
|
|
|
desc);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear interrupts */
|
|
|
|
mc_writel(mc, status, MC_INTSTATUS);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2014-04-16 14:24:44 +07:00
|
|
|
static int tegra_mc_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct resource *res;
|
|
|
|
struct tegra_mc *mc;
|
2018-04-10 02:28:31 +07:00
|
|
|
void *isr;
|
2014-04-16 14:24:44 +07:00
|
|
|
int err;
|
|
|
|
|
|
|
|
mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
|
|
|
|
if (!mc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, mc);
|
2018-04-13 18:33:49 +07:00
|
|
|
spin_lock_init(&mc->lock);
|
2018-12-13 03:38:54 +07:00
|
|
|
mc->soc = of_device_get_match_data(&pdev->dev);
|
2014-04-16 14:24:44 +07:00
|
|
|
mc->dev = &pdev->dev;
|
|
|
|
|
|
|
|
/* length of MC tick in nanoseconds */
|
|
|
|
mc->tick = 30;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
mc->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(mc->regs))
|
|
|
|
return PTR_ERR(mc->regs);
|
|
|
|
|
2018-12-13 03:38:52 +07:00
|
|
|
mc->clk = devm_clk_get(&pdev->dev, "mc");
|
|
|
|
if (IS_ERR(mc->clk)) {
|
|
|
|
dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
|
|
|
|
PTR_ERR(mc->clk));
|
|
|
|
return PTR_ERR(mc->clk);
|
|
|
|
}
|
|
|
|
|
2018-04-10 02:28:31 +07:00
|
|
|
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
|
|
|
|
if (mc->soc == &tegra20_mc_soc) {
|
|
|
|
isr = tegra20_mc_irq;
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
{
|
|
|
|
err = tegra_mc_setup_latency_allowance(mc);
|
|
|
|
if (err < 0) {
|
2018-12-13 03:38:59 +07:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"failed to setup latency allowance: %d\n",
|
2018-04-10 02:28:31 +07:00
|
|
|
err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
isr = tegra_mc_irq;
|
2014-04-16 14:24:44 +07:00
|
|
|
|
2018-12-13 03:38:51 +07:00
|
|
|
err = tegra_mc_setup_timings(mc);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(&pdev->dev, "failed to setup timings: %d\n",
|
|
|
|
err);
|
|
|
|
return err;
|
|
|
|
}
|
2015-03-12 21:48:02 +07:00
|
|
|
}
|
|
|
|
|
2014-04-16 14:24:44 +07:00
|
|
|
mc->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (mc->irq < 0) {
|
|
|
|
dev_err(&pdev->dev, "interrupt not specified\n");
|
|
|
|
return mc->irq;
|
|
|
|
}
|
|
|
|
|
2018-12-13 03:38:59 +07:00
|
|
|
WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
|
2015-06-05 02:33:48 +07:00
|
|
|
|
2018-04-10 02:28:29 +07:00
|
|
|
mc_writel(mc, mc->soc->intmask, MC_INTMASK);
|
2014-04-16 14:24:44 +07:00
|
|
|
|
2018-12-13 03:38:58 +07:00
|
|
|
err = devm_request_irq(&pdev->dev, mc->irq, isr, 0,
|
2018-04-10 02:28:28 +07:00
|
|
|
dev_name(&pdev->dev), mc);
|
|
|
|
if (err < 0) {
|
|
|
|
dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
|
|
|
|
err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2018-05-26 21:20:35 +07:00
|
|
|
err = tegra_mc_reset_setup(mc);
|
|
|
|
if (err < 0)
|
|
|
|
dev_err(&pdev->dev, "failed to register reset controller: %d\n",
|
|
|
|
err);
|
|
|
|
|
2018-12-13 03:38:57 +07:00
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
|
2018-05-08 23:55:30 +07:00
|
|
|
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
|
2018-12-13 03:38:57 +07:00
|
|
|
if (IS_ERR(mc->smmu)) {
|
2018-05-08 23:55:30 +07:00
|
|
|
dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
|
|
|
|
PTR_ERR(mc->smmu));
|
2018-12-13 03:38:57 +07:00
|
|
|
mc->smmu = NULL;
|
|
|
|
}
|
2018-05-08 23:55:30 +07:00
|
|
|
}
|
|
|
|
|
2018-12-13 03:38:56 +07:00
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
|
|
|
|
mc->gart = tegra_gart_probe(&pdev->dev, mc);
|
|
|
|
if (IS_ERR(mc->gart)) {
|
|
|
|
dev_err(&pdev->dev, "failed to probe GART: %ld\n",
|
|
|
|
PTR_ERR(mc->gart));
|
|
|
|
mc->gart = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_mc_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_mc *mc = dev_get_drvdata(dev);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
|
|
|
|
err = tegra_gart_suspend(mc->gart);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2014-04-16 14:24:44 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-12-13 03:38:56 +07:00
|
|
|
static int tegra_mc_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct tegra_mc *mc = dev_get_drvdata(dev);
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && mc->gart) {
|
|
|
|
err = tegra_gart_resume(mc->gart);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct dev_pm_ops tegra_mc_pm_ops = {
|
|
|
|
.suspend = tegra_mc_suspend,
|
|
|
|
.resume = tegra_mc_resume,
|
|
|
|
};
|
|
|
|
|
2014-04-16 14:24:44 +07:00
|
|
|
static struct platform_driver tegra_mc_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "tegra-mc",
|
|
|
|
.of_match_table = tegra_mc_of_match,
|
2018-12-13 03:38:56 +07:00
|
|
|
.pm = &tegra_mc_pm_ops,
|
2014-04-16 14:24:44 +07:00
|
|
|
.suppress_bind_attrs = true,
|
|
|
|
},
|
|
|
|
.prevent_deferred_probe = true,
|
|
|
|
.probe = tegra_mc_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tegra_mc_init(void)
|
|
|
|
{
|
|
|
|
return platform_driver_register(&tegra_mc_driver);
|
|
|
|
}
|
|
|
|
arch_initcall(tegra_mc_init);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
|
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|