mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
33 lines
1.0 KiB
Plaintext
33 lines
1.0 KiB
Plaintext
|
ZTE zx2967 Watchdog timer
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
|
||
|
|
- compatible : should be one of the following.
|
||
|
|
* zte,zx296718-wdt
|
||
|
|
- reg : Specifies base physical address and size of the registers.
|
||
|
|
- clocks : Pairs of phandle and specifier referencing the controller's clocks.
|
||
|
|
- resets : Reference to the reset controller controlling the watchdog
|
||
|
|
controller.
|
||
|
|
|
||
|
|
Optional properties:
|
||
|
|
|
||
|
|
- timeout-sec : Contains the watchdog timeout in seconds.
|
||
|
|
- zte,wdt-reset-sysctrl : Directs how to reset system by the watchdog.
|
||
|
|
if we don't want to restart system when watchdog been triggered,
|
||
|
|
it's not required, vice versa.
|
||
|
|
It should include following fields.
|
||
|
|
* phandle of aon-sysctrl.
|
||
|
|
* offset of register that be written, should be 0xb0.
|
||
|
|
* configure value that be written to aon-sysctrl.
|
||
|
|
* bit mask, corresponding bits will be affected.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
|
||
|
|
wdt: watchdog@1465000 {
|
||
|
|
compatible = "zte,zx296718-wdt";
|
||
|
|
reg = <0x1465000 0x1000>;
|
||
|
|
clocks = <&topcrm WDT_WCLK>;
|
||
|
|
resets = <&toprst 35>;
|
||
|
|
zte,wdt-reset-sysctrl = <&aon_sysctrl 0xb0 1 0x115>;
|
||
|
|
};
|