2005-04-17 05:20:36 +07:00
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/*
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* This file contains work-arounds for x86 and x86_64 platform bugs.
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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2006-12-07 08:14:10 +07:00
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#include <asm/pci-direct.h>
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#include <asm/genapic.h>
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#include <asm/cpu.h>
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2005-04-17 05:20:36 +07:00
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#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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2006-12-07 08:14:10 +07:00
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static void __devinit verify_quirk_intel_irqbalance(struct pci_dev *dev)
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{
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#ifdef CONFIG_X86_64
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2007-05-03 00:27:04 +07:00
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if (genapic != &apic_flat)
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panic("APIC mode must be flat on this system\n");
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2006-12-07 08:14:10 +07:00
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#elif defined(CONFIG_X86_GENERICARCH)
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2007-05-03 00:27:04 +07:00
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if (genapic != &apic_default)
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panic("APIC mode must be default(flat) on this system. Use apic=default\n");
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2006-12-07 08:14:10 +07:00
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#endif
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}
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2005-04-17 05:20:36 +07:00
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2006-12-07 08:14:10 +07:00
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void __init quirk_intel_irqbalance(void)
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2005-04-17 05:20:36 +07:00
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{
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u8 config, rev;
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u32 word;
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/* BIOS may enable hardware IRQ balancing for
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* E7520/E7320/E7525(revision ID 0x9 and below)
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* based platforms.
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* Disable SW irqbalance/affinity on those platforms.
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*/
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2006-12-07 08:14:10 +07:00
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rev = read_pci_config_byte(0, 0, 0, PCI_CLASS_REVISION);
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2005-04-17 05:20:36 +07:00
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if (rev > 0x9)
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return;
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printk(KERN_INFO "Intel E7520/7320/7525 detected.");
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2006-12-07 08:14:10 +07:00
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/* enable access to config space */
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config = read_pci_config_byte(0, 0, 0, 0xf4);
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write_pci_config_byte(0, 0, 0, 0xf4, config|0x2);
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2005-04-17 05:20:36 +07:00
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/* read xTPR register */
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2006-12-07 08:14:10 +07:00
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word = read_pci_config_16(0, 0, 0x40, 0x4c);
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2005-04-17 05:20:36 +07:00
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if (!(word & (1 << 13))) {
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printk(KERN_INFO "Disabling irq balancing and affinity\n");
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#ifdef CONFIG_IRQBALANCE
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irqbalance_disable("");
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#endif
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noirqdebug_setup("");
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#ifdef CONFIG_PROC_FS
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no_irq_affinity = 1;
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2006-12-07 08:14:10 +07:00
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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printk(KERN_INFO "Disabling cpu hotplug control\n");
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enable_cpu_hotplug = 0;
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#endif
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#ifdef CONFIG_X86_64
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/* force the genapic selection to flat mode so that
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* interrupts can be redirected to more than one CPU.
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*/
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genapic_force = &apic_flat;
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2005-04-17 05:20:36 +07:00
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#endif
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}
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2006-12-07 08:14:10 +07:00
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/* put back the original value for config space */
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2006-01-19 08:44:13 +07:00
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if (!(config & 0x2))
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2006-12-07 08:14:10 +07:00
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write_pci_config_byte(0, 0, 0, 0xf4, config);
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2005-04-17 05:20:36 +07:00
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}
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2006-12-07 08:14:10 +07:00
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, verify_quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, verify_quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, verify_quirk_intel_irqbalance);
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2005-04-17 05:20:36 +07:00
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#endif
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