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267 lines
8.0 KiB
C
267 lines
8.0 KiB
C
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/*
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* tcic.h 1.13 1999/10/25 20:03:34
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*
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* The contents of this file are subject to the Mozilla Public License
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* Version 1.1 (the "License"); you may not use this file except in
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* compliance with the License. You may obtain a copy of the License
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* at http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS"
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* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
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* the License for the specific language governing rights and
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* limitations under the License.
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*
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* The initial developer of the original code is David A. Hinds
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* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
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* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
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*
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* Alternatively, the contents of this file may be used under the
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* terms of the GNU General Public License version 2 (the "GPL"), in which
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* case the provisions of the GPL are applicable instead of the
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* above. If you wish to allow the use of your version of this file
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* only under the terms of the GPL and not to allow others to use
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* your version of this file under the MPL, indicate your decision by
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* deleting the provisions above and replace them with the notice and
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* other provisions required by the GPL. If you do not delete the
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* provisions above, a recipient may use your version of this file
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* under either the MPL or the GPL.
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*/
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#ifndef _LINUX_TCIC_H
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#define _LINUX_TCIC_H
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#define TCIC_BASE 0x240
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/* offsets of registers from TCIC_BASE */
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#define TCIC_DATA 0x00
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#define TCIC_ADDR 0x02
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#define TCIC_SCTRL 0x06
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#define TCIC_SSTAT 0x07
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#define TCIC_MODE 0x08
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#define TCIC_PWR 0x09
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#define TCIC_EDC 0x0A
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#define TCIC_ICSR 0x0C
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#define TCIC_IENA 0x0D
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#define TCIC_AUX 0x0E
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#define TCIC_SS_SHFT 12
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#define TCIC_SS_MASK 0x7000
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/* Flags for TCIC_ADDR */
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#define TCIC_ADR2_REG 0x8000
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#define TCIC_ADR2_INDREG 0x0800
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#define TCIC_ADDR_REG 0x80000000
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#define TCIC_ADDR_SS_SHFT (TCIC_SS_SHFT+16)
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#define TCIC_ADDR_SS_MASK (TCIC_SS_MASK<<16)
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#define TCIC_ADDR_INDREG 0x08000000
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#define TCIC_ADDR_IO 0x04000000
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#define TCIC_ADDR_MASK 0x03ffffff
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/* Flags for TCIC_SCTRL */
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#define TCIC_SCTRL_ENA 0x01
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#define TCIC_SCTRL_INCMODE 0x18
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#define TCIC_SCTRL_INCMODE_HOLD 0x00
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#define TCIC_SCTRL_INCMODE_WORD 0x08
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#define TCIC_SCTRL_INCMODE_REG 0x10
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#define TCIC_SCTRL_INCMODE_AUTO 0x18
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#define TCIC_SCTRL_EDCSUM 0x20
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#define TCIC_SCTRL_RESET 0x80
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/* Flags for TCIC_SSTAT */
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#define TCIC_SSTAT_6US 0x01
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#define TCIC_SSTAT_10US 0x02
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#define TCIC_SSTAT_PROGTIME 0x04
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#define TCIC_SSTAT_LBAT1 0x08
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#define TCIC_SSTAT_LBAT2 0x10
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#define TCIC_SSTAT_RDY 0x20 /* Inverted */
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#define TCIC_SSTAT_WP 0x40
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#define TCIC_SSTAT_CD 0x80 /* Card detect */
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/* Flags for TCIC_MODE */
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#define TCIC_MODE_PGMMASK 0x1f
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#define TCIC_MODE_NORMAL 0x00
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#define TCIC_MODE_PGMWR 0x01
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#define TCIC_MODE_PGMRD 0x02
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#define TCIC_MODE_PGMCE 0x04
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#define TCIC_MODE_PGMDBW 0x08
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#define TCIC_MODE_PGMWORD 0x10
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#define TCIC_MODE_AUXSEL_MASK 0xe0
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/* Registers accessed through TCIC_AUX, by setting TCIC_MODE */
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#define TCIC_AUX_TCTL (0<<5)
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#define TCIC_AUX_PCTL (1<<5)
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#define TCIC_AUX_WCTL (2<<5)
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#define TCIC_AUX_EXTERN (3<<5)
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#define TCIC_AUX_PDATA (4<<5)
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#define TCIC_AUX_SYSCFG (5<<5)
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#define TCIC_AUX_ILOCK (6<<5)
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#define TCIC_AUX_TEST (7<<5)
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/* Flags for TCIC_PWR */
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#define TCIC_PWR_VCC(sock) (0x01<<(sock))
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#define TCIC_PWR_VCC_MASK 0x03
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#define TCIC_PWR_VPP(sock) (0x08<<(sock))
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#define TCIC_PWR_VPP_MASK 0x18
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#define TCIC_PWR_CLIMENA 0x40
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#define TCIC_PWR_CLIMSTAT 0x80
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/* Flags for TCIC_ICSR */
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#define TCIC_ICSR_CLEAR 0x01
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#define TCIC_ICSR_SET 0x02
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#define TCIC_ICSR_JAM (TCIC_ICSR_CLEAR|TCIC_ICSR_SET)
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#define TCIC_ICSR_STOPCPU 0x04
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#define TCIC_ICSR_ILOCK 0x08
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#define TCIC_ICSR_PROGTIME 0x10
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#define TCIC_ICSR_ERR 0x20
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#define TCIC_ICSR_CDCHG 0x40
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#define TCIC_ICSR_IOCHK 0x80
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/* Flags for TCIC_IENA */
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#define TCIC_IENA_CFG_MASK 0x03
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#define TCIC_IENA_CFG_OFF 0x00 /* disabled */
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#define TCIC_IENA_CFG_OD 0x01 /* active low, open drain */
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#define TCIC_IENA_CFG_LOW 0x02 /* active low, totem pole */
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#define TCIC_IENA_CFG_HIGH 0x03 /* active high, totem pole */
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#define TCIC_IENA_ILOCK 0x08
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#define TCIC_IENA_PROGTIME 0x10
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#define TCIC_IENA_ERR 0x20 /* overcurrent or iochk */
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#define TCIC_IENA_CDCHG 0x40
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/* Flags for TCIC_AUX_WCTL */
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#define TCIC_WAIT_COUNT_MASK 0x001f
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#define TCIC_WAIT_ASYNC 0x0020
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#define TCIC_WAIT_SENSE 0x0040
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#define TCIC_WAIT_SRC 0x0080
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#define TCIC_WCTL_WR 0x0100
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#define TCIC_WCTL_RD 0x0200
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#define TCIC_WCTL_CE 0x0400
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#define TCIC_WCTL_LLBAT1 0x0800
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#define TCIC_WCTL_LLBAT2 0x1000
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#define TCIC_WCTL_LRDY 0x2000
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#define TCIC_WCTL_LWP 0x4000
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#define TCIC_WCTL_LCD 0x8000
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/* Flags for TCIC_AUX_SYSCFG */
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#define TCIC_SYSCFG_IRQ_MASK 0x000f
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#define TCIC_SYSCFG_MCSFULL 0x0010
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#define TCIC_SYSCFG_IO1723 0x0020
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#define TCIC_SYSCFG_MCSXB 0x0040
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#define TCIC_SYSCFG_ICSXB 0x0080
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#define TCIC_SYSCFG_NOPDN 0x0100
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#define TCIC_SYSCFG_MPSEL_SHFT 9
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#define TCIC_SYSCFG_MPSEL_MASK 0x0e00
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#define TCIC_SYSCFG_MPSENSE 0x2000
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#define TCIC_SYSCFG_AUTOBUSY 0x4000
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#define TCIC_SYSCFG_ACC 0x8000
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#define TCIC_ILOCK_OUT 0x01
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#define TCIC_ILOCK_SENSE 0x02
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#define TCIC_ILOCK_CRESET 0x04
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#define TCIC_ILOCK_CRESENA 0x08
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#define TCIC_ILOCK_CWAIT 0x10
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#define TCIC_ILOCK_CWAITSNS 0x20
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#define TCIC_ILOCK_HOLD_MASK 0xc0
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#define TCIC_ILOCK_HOLD_CCLK 0xc0
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#define TCIC_ILOCKTEST_ID_SH 8
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#define TCIC_ILOCKTEST_ID_MASK 0x7f00
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#define TCIC_ILOCKTEST_MCIC_1 0x8000
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#define TCIC_ID_DB86082 0x02
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#define TCIC_ID_DB86082A 0x03
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#define TCIC_ID_DB86084 0x04
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#define TCIC_ID_DB86084A 0x08
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#define TCIC_ID_DB86072 0x15
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#define TCIC_ID_DB86184 0x14
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#define TCIC_ID_DB86082B 0x17
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#define TCIC_TEST_DIAG 0x8000
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/*
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* Indirectly addressed registers
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*/
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#define TCIC_SCF1(sock) ((sock)<<3)
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#define TCIC_SCF2(sock) (((sock)<<3)+2)
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/* Flags for SCF1 */
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#define TCIC_SCF1_IRQ_MASK 0x000f
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#define TCIC_SCF1_IRQ_OFF 0x0000
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#define TCIC_SCF1_IRQOC 0x0010
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#define TCIC_SCF1_PCVT 0x0020
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#define TCIC_SCF1_IRDY 0x0040
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#define TCIC_SCF1_ATA 0x0080
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#define TCIC_SCF1_DMA_SHIFT 8
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#define TCIC_SCF1_DMA_MASK 0x0700
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#define TCIC_SCF1_DMA_OFF 0
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#define TCIC_SCF1_DREQ2 2
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#define TCIC_SCF1_IOSTS 0x0800
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#define TCIC_SCF1_SPKR 0x1000
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#define TCIC_SCF1_FINPACK 0x2000
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#define TCIC_SCF1_DELWR 0x4000
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#define TCIC_SCF1_HD7IDE 0x8000
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/* Flags for SCF2 */
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#define TCIC_SCF2_RI 0x0001
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#define TCIC_SCF2_IDBR 0x0002
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#define TCIC_SCF2_MDBR 0x0004
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#define TCIC_SCF2_MLBAT1 0x0008
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#define TCIC_SCF2_MLBAT2 0x0010
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#define TCIC_SCF2_MRDY 0x0020
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#define TCIC_SCF2_MWP 0x0040
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#define TCIC_SCF2_MCD 0x0080
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#define TCIC_SCF2_MALL 0x00f8
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/* Indirect addresses for memory window registers */
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#define TCIC_MWIN(sock,map) (0x100+(((map)+((sock)<<2))<<3))
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#define TCIC_MBASE_X 2
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#define TCIC_MMAP_X 4
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#define TCIC_MCTL_X 6
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#define TCIC_MBASE_4K_BIT 0x4000
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#define TCIC_MBASE_HA_SHFT 12
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#define TCIC_MBASE_HA_MASK 0x0fff
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#define TCIC_MMAP_REG 0x8000
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#define TCIC_MMAP_CA_SHFT 12
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#define TCIC_MMAP_CA_MASK 0x3fff
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#define TCIC_MCTL_WSCNT_MASK 0x001f
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#define TCIC_MCTL_WCLK 0x0020
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#define TCIC_MCTL_WCLK_CCLK 0x0000
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#define TCIC_MCTL_WCLK_BCLK 0x0020
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#define TCIC_MCTL_QUIET 0x0040
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#define TCIC_MCTL_WP 0x0080
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#define TCIC_MCTL_ACC 0x0100
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#define TCIC_MCTL_KE 0x0200
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#define TCIC_MCTL_EDC 0x0400
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#define TCIC_MCTL_B8 0x0800
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#define TCIC_MCTL_SS_SHFT TCIC_SS_SHFT
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#define TCIC_MCTL_SS_MASK TCIC_SS_MASK
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#define TCIC_MCTL_ENA 0x8000
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/* Indirect addresses for I/O window registers */
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#define TCIC_IWIN(sock,map) (0x200+(((map)+((sock)<<1))<<2))
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#define TCIC_IBASE_X 0
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#define TCIC_ICTL_X 2
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#define TCIC_ICTL_WSCNT_MASK TCIC_MCTL_WSCNT_MASK
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#define TCIC_ICTL_QUIET TCIC_MCTL_QUIET
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#define TCIC_ICTL_1K 0x0080
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#define TCIC_ICTL_PASS16 0x0100
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#define TCIC_ICTL_ACC TCIC_MCTL_ACC
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#define TCIC_ICTL_TINY 0x0200
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#define TCIC_ICTL_B16 0x0400
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#define TCIC_ICTL_B8 TCIC_MCTL_B8
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#define TCIC_ICTL_BW_MASK (TCIC_ICTL_B16|TCIC_ICTL_B8)
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#define TCIC_ICTL_BW_DYN 0
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#define TCIC_ICTL_BW_8 TCIC_ICTL_B8
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#define TCIC_ICTL_BW_16 TCIC_ICTL_B16
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#define TCIC_ICTL_BW_ATA (TCIC_ICTL_B16|TCIC_ICTL_B8)
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#define TCIC_ICTL_SS_SHFT TCIC_SS_SHFT
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#define TCIC_ICTL_SS_MASK TCIC_SS_MASK
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#define TCIC_ICTL_ENA TCIC_MCTL_ENA
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#endif /* _LINUX_TCIC_H */
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