2009-02-11 03:10:44 +07:00
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/*
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2012-11-02 01:53:42 +07:00
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* Copyright 2009 Freescale Semiconductor, Inc.
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2009-02-11 03:10:44 +07:00
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* provides masks and opcode images for use by code generation, emulation
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* and for instructions that older assemblers might not know about
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*/
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#ifndef _ASM_POWERPC_PPC_OPCODE_H
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#define _ASM_POWERPC_PPC_OPCODE_H
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2018-07-05 23:24:57 +07:00
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#include <asm/asm-const.h>
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2009-02-11 03:10:44 +07:00
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2012-06-25 20:33:22 +07:00
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#define __REG_R0 0
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#define __REG_R1 1
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#define __REG_R2 2
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#define __REG_R3 3
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#define __REG_R4 4
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#define __REG_R5 5
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#define __REG_R6 6
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#define __REG_R7 7
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#define __REG_R8 8
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#define __REG_R9 9
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#define __REG_R10 10
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#define __REG_R11 11
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#define __REG_R12 12
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#define __REG_R13 13
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#define __REG_R14 14
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#define __REG_R15 15
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#define __REG_R16 16
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#define __REG_R17 17
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#define __REG_R18 18
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#define __REG_R19 19
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#define __REG_R20 20
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#define __REG_R21 21
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#define __REG_R22 22
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#define __REG_R23 23
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#define __REG_R24 24
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#define __REG_R25 25
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#define __REG_R26 26
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#define __REG_R27 27
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#define __REG_R28 28
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#define __REG_R29 29
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#define __REG_R30 30
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#define __REG_R31 31
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2012-06-25 20:33:24 +07:00
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#define __REGA0_0 0
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#define __REGA0_R1 1
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#define __REGA0_R2 2
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#define __REGA0_R3 3
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#define __REGA0_R4 4
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#define __REGA0_R5 5
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#define __REGA0_R6 6
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#define __REGA0_R7 7
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#define __REGA0_R8 8
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#define __REGA0_R9 9
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#define __REGA0_R10 10
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#define __REGA0_R11 11
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#define __REGA0_R12 12
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#define __REGA0_R13 13
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#define __REGA0_R14 14
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#define __REGA0_R15 15
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#define __REGA0_R16 16
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#define __REGA0_R17 17
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#define __REGA0_R18 18
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#define __REGA0_R19 19
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#define __REGA0_R20 20
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#define __REGA0_R21 21
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#define __REGA0_R22 22
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#define __REGA0_R23 23
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#define __REGA0_R24 24
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#define __REGA0_R25 25
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#define __REGA0_R26 26
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#define __REGA0_R27 27
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#define __REGA0_R28 28
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#define __REGA0_R29 29
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#define __REGA0_R30 30
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#define __REGA0_R31 31
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2013-04-28 12:20:07 +07:00
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/* opcode and xopcode for instructions */
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#define OP_TRAP 3
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#define OP_TRAP_64 2
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#define OP_31_XOP_TRAP 4
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#define OP_31_XOP_LDX 21
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_LWZX 23
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#define OP_31_XOP_LDUX 53
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_DCBST 54
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#define OP_31_XOP_LWZUX 55
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#define OP_31_XOP_TRAP_64 68
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#define OP_31_XOP_DCBF 86
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#define OP_31_XOP_LBZX 87
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2017-03-17 15:31:38 +07:00
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#define OP_31_XOP_STDX 149
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_STWX 151
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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#define OP_31_XOP_STDUX 181
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#define OP_31_XOP_STWUX 183
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_STBX 215
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#define OP_31_XOP_LBZUX 119
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#define OP_31_XOP_STBUX 247
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#define OP_31_XOP_LHZX 279
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#define OP_31_XOP_LHZUX 311
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KVM: PPC: Book3S HV: Virtualize doorbell facility on POWER9
On POWER9, we no longer have the restriction that we had on POWER8
where all threads in a core have to be in the same partition, so
the CPU threads are now independent. However, we still want to be
able to run guests with a virtual SMT topology, if only to allow
migration of guests from POWER8 systems to POWER9.
A guest that has a virtual SMT mode greater than 1 will expect to
be able to use the doorbell facility; it will expect the msgsndp
and msgclrp instructions to work appropriately and to be able to read
sensible values from the TIR (thread identification register) and
DPDES (directed privileged doorbell exception status) special-purpose
registers. However, since each CPU thread is a separate sub-processor
in POWER9, these instructions and registers can only be used within
a single CPU thread.
In order for these instructions to appear to act correctly according
to the guest's virtual SMT mode, we have to trap and emulate them.
We cause them to trap by clearing the HFSCR_MSGP bit in the HFSCR
register. The emulation is triggered by the hypervisor facility
unavailable interrupt that occurs when the guest uses them.
To cause a doorbell interrupt to occur within the guest, we set the
DPDES register to 1. If the guest has interrupts enabled, the CPU
will generate a doorbell interrupt and clear the DPDES register in
hardware. The DPDES hardware register for the guest is saved in the
vcpu->arch.vcore->dpdes field. Since this gets written by the guest
exit code, other VCPUs wishing to cause a doorbell interrupt don't
write that field directly, but instead set a vcpu->arch.doorbell_request
flag. This is consumed and set to 0 by the guest entry code, which
then sets DPDES to 1.
Emulating reads of the DPDES register is somewhat involved, because
it requires reading the doorbell pending interrupt status of all of the
VCPU threads in the virtual core, and if any of those VCPUs are
running, their doorbell status is only up-to-date in the hardware
DPDES registers of the CPUs where they are running. In order to get
a reasonable approximation of the current doorbell status, we send
those CPUs an IPI, causing an exit from the guest which will update
the vcpu->arch.vcore->dpdes field. We then use that value in
constructing the emulated DPDES register value.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-05-16 13:41:20 +07:00
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#define OP_31_XOP_MSGSNDP 142
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#define OP_31_XOP_MSGCLRP 174
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KVM: PPC: Book3S HV: Implement H_TLB_INVALIDATE hcall
When running a nested (L2) guest the guest (L1) hypervisor will use
the H_TLB_INVALIDATE hcall when it needs to change the partition
scoped page tables or the partition table which it manages. It will
use this hcall in the situations where it would use a partition-scoped
tlbie instruction if it were running in hypervisor mode.
The H_TLB_INVALIDATE hcall can invalidate different scopes:
Invalidate TLB for a given target address:
- This invalidates a single L2 -> L1 pte
- We need to invalidate any L2 -> L0 shadow_pgtable ptes which map the L2
address space which is being invalidated. This is because a single
L2 -> L1 pte may have been mapped with more than one pte in the
L2 -> L0 page tables.
Invalidate the entire TLB for a given LPID or for all LPIDs:
- Invalidate the entire shadow_pgtable for a given nested guest, or
for all nested guests.
Invalidate the PWC (page walk cache) for a given LPID or for all LPIDs:
- We don't cache the PWC, so nothing to do.
Invalidate the entire TLB, PWC and partition table for a given/all LPIDs:
- Here we re-read the partition table entry and remove the nested state
for any nested guest for which the first doubleword of the partition
table entry is now zero.
The H_TLB_INVALIDATE hcall takes as parameters the tlbie instruction
word (of which only the RIC, PRS and R fields are used), the rS value
(giving the lpid, where required) and the rB value (giving the IS, AP
and EPN values).
[paulus@ozlabs.org - adapted to having the partition table in guest
memory, added the H_TLB_INVALIDATE implementation, removed tlbie
instruction emulation, reworded the commit message.]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-10-08 12:31:09 +07:00
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#define OP_31_XOP_TLBIE 306
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_MFSPR 339
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#define OP_31_XOP_LWAX 341
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_LHAX 343
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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#define OP_31_XOP_LWAUX 373
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_LHAUX 375
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#define OP_31_XOP_STHX 407
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#define OP_31_XOP_STHUX 439
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#define OP_31_XOP_MTSPR 467
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#define OP_31_XOP_DCBI 470
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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#define OP_31_XOP_LDBRX 532
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_LWBRX 534
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#define OP_31_XOP_TLBSYNC 566
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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#define OP_31_XOP_STDBRX 660
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_STWBRX 662
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#define OP_31_XOP_STFSX 663
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#define OP_31_XOP_STFSUX 695
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#define OP_31_XOP_STFDX 727
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#define OP_31_XOP_STFDUX 759
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_LHBRX 790
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2017-03-23 07:55:16 +07:00
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#define OP_31_XOP_LFIWAX 855
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#define OP_31_XOP_LFIWZX 887
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2013-04-28 12:20:07 +07:00
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#define OP_31_XOP_STHBRX 918
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#define OP_31_XOP_STFIWX 983
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/* VSX Scalar Load Instructions */
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#define OP_31_XOP_LXSDX 588
|
|
|
|
|
#define OP_31_XOP_LXSSPX 524
|
|
|
|
|
#define OP_31_XOP_LXSIWAX 76
|
|
|
|
|
#define OP_31_XOP_LXSIWZX 12
|
|
|
|
|
|
|
|
|
|
/* VSX Scalar Store Instructions */
|
|
|
|
|
#define OP_31_XOP_STXSDX 716
|
|
|
|
|
#define OP_31_XOP_STXSSPX 652
|
|
|
|
|
#define OP_31_XOP_STXSIWX 140
|
|
|
|
|
|
|
|
|
|
/* VSX Vector Load Instructions */
|
|
|
|
|
#define OP_31_XOP_LXVD2X 844
|
|
|
|
|
#define OP_31_XOP_LXVW4X 780
|
|
|
|
|
|
|
|
|
|
/* VSX Vector Load and Splat Instruction */
|
|
|
|
|
#define OP_31_XOP_LXVDSX 332
|
|
|
|
|
|
|
|
|
|
/* VSX Vector Store Instructions */
|
|
|
|
|
#define OP_31_XOP_STXVD2X 972
|
|
|
|
|
#define OP_31_XOP_STXVW4X 908
|
|
|
|
|
|
|
|
|
|
#define OP_31_XOP_LFSX 535
|
|
|
|
|
#define OP_31_XOP_LFSUX 567
|
|
|
|
|
#define OP_31_XOP_LFDX 599
|
|
|
|
|
#define OP_31_XOP_LFDUX 631
|
2013-04-28 12:20:07 +07:00
|
|
|
|
2018-02-04 03:24:26 +07:00
|
|
|
/* VMX Vector Load Instructions */
|
|
|
|
|
#define OP_31_XOP_LVX 103
|
|
|
|
|
|
|
|
|
|
/* VMX Vector Store Instructions */
|
|
|
|
|
#define OP_31_XOP_STVX 231
|
|
|
|
|
|
2018-05-23 14:04:04 +07:00
|
|
|
#define OP_31 31
|
2013-04-28 12:20:07 +07:00
|
|
|
#define OP_LWZ 32
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
#define OP_STFS 52
|
|
|
|
|
#define OP_STFSU 53
|
|
|
|
|
#define OP_STFD 54
|
|
|
|
|
#define OP_STFDU 55
|
2013-04-28 12:20:07 +07:00
|
|
|
#define OP_LD 58
|
|
|
|
|
#define OP_LWZU 33
|
|
|
|
|
#define OP_LBZ 34
|
|
|
|
|
#define OP_LBZU 35
|
|
|
|
|
#define OP_STW 36
|
|
|
|
|
#define OP_STWU 37
|
|
|
|
|
#define OP_STD 62
|
|
|
|
|
#define OP_STB 38
|
|
|
|
|
#define OP_STBU 39
|
|
|
|
|
#define OP_LHZ 40
|
|
|
|
|
#define OP_LHZU 41
|
|
|
|
|
#define OP_LHA 42
|
|
|
|
|
#define OP_LHAU 43
|
|
|
|
|
#define OP_STH 44
|
|
|
|
|
#define OP_STHU 45
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
#define OP_LMW 46
|
|
|
|
|
#define OP_STMW 47
|
|
|
|
|
#define OP_LFS 48
|
|
|
|
|
#define OP_LFSU 49
|
|
|
|
|
#define OP_LFD 50
|
|
|
|
|
#define OP_LFDU 51
|
|
|
|
|
#define OP_STFS 52
|
|
|
|
|
#define OP_STFSU 53
|
|
|
|
|
#define OP_STFD 54
|
|
|
|
|
#define OP_STFDU 55
|
|
|
|
|
#define OP_LQ 56
|
2013-04-28 12:20:07 +07:00
|
|
|
|
2009-02-11 03:10:44 +07:00
|
|
|
/* sorted alphabetically */
|
2013-04-23 02:42:40 +07:00
|
|
|
#define PPC_INST_BHRBE 0x7c00025c
|
|
|
|
|
#define PPC_INST_CLRBHRB 0x7c00035c
|
2017-06-08 22:36:09 +07:00
|
|
|
#define PPC_INST_COPY 0x7c20060c
|
2016-04-26 07:28:50 +07:00
|
|
|
#define PPC_INST_CP_ABORT 0x7c00068c
|
2017-08-04 08:12:18 +07:00
|
|
|
#define PPC_INST_DARN 0x7c0005e6
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_DCBA 0x7c0005ec
|
|
|
|
|
#define PPC_INST_DCBA_MASK 0xfc0007fe
|
|
|
|
|
#define PPC_INST_DCBAL 0x7c2005ec
|
|
|
|
|
#define PPC_INST_DCBZL 0x7c2007ec
|
2012-10-02 22:52:19 +07:00
|
|
|
#define PPC_INST_ICBT 0x7c00002c
|
2015-05-08 00:49:13 +07:00
|
|
|
#define PPC_INST_ICSWX 0x7c00032d
|
|
|
|
|
#define PPC_INST_ICSWEPX 0x7c00076d
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_ISEL 0x7c00001e
|
|
|
|
|
#define PPC_INST_ISEL_MASK 0xfc00003e
|
2010-02-10 08:02:36 +07:00
|
|
|
#define PPC_INST_LDARX 0x7c0000a8
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_STDCX 0x7c0001ad
|
powerpc: Handle most loads and stores in instruction emulation code
This extends the instruction emulation infrastructure in sstep.c to
handle all the load and store instructions defined in the Power ISA
v3.0, except for the atomic memory operations, ldmx (which was never
implemented), lfdp/stfdp, and the vector element load/stores.
The instructions added are:
Integer loads and stores: lbarx, lharx, lqarx, stbcx., sthcx., stqcx.,
lq, stq.
VSX loads and stores: lxsiwzx, lxsiwax, stxsiwx, lxvx, lxvl, lxvll,
lxvdsx, lxvwsx, stxvx, stxvl, stxvll, lxsspx, lxsdx, stxsspx, stxsdx,
lxvw4x, lxsibzx, lxvh8x, lxsihzx, lxvb16x, stxvw4x, stxsibx, stxvh8x,
stxsihx, stxvb16x, lxsd, lxssp, lxv, stxsd, stxssp, stxv.
These instructions are handled both in the analyse_instr phase and in
the emulate_step phase.
The code for lxvd2ux and stxvd2ux has been taken out, as those
instructions were never implemented in any processor and have been
taken out of the architecture, and their opcodes have been reused for
other instructions in POWER9 (lxvb16x and stxvb16x).
The emulation for the VSX loads and stores uses helper functions
which don't access registers or memory directly, which can hopefully
be reused by KVM later.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-30 11:12:27 +07:00
|
|
|
#define PPC_INST_LQARX 0x7c000228
|
|
|
|
|
#define PPC_INST_STQCX 0x7c00016d
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_LSWI 0x7c0004aa
|
|
|
|
|
#define PPC_INST_LSWX 0x7c00042a
|
2010-03-11 12:33:25 +07:00
|
|
|
#define PPC_INST_LWARX 0x7c000028
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_STWCX 0x7c00012d
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_LWSYNC 0x7c2004ac
|
2013-07-04 04:26:47 +07:00
|
|
|
#define PPC_INST_SYNC 0x7c0004ac
|
|
|
|
|
#define PPC_INST_SYNC_MASK 0xfc0007fe
|
2016-05-17 19:01:39 +07:00
|
|
|
#define PPC_INST_ISYNC 0x4c00012c
|
2009-04-30 03:58:01 +07:00
|
|
|
#define PPC_INST_LXVD2X 0x7c000698
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_MCRXR 0x7c000400
|
|
|
|
|
#define PPC_INST_MCRXR_MASK 0xfc0007fe
|
|
|
|
|
#define PPC_INST_MFSPR_PVR 0x7c1f42a6
|
2017-01-19 10:19:10 +07:00
|
|
|
#define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe
|
2011-12-08 14:20:27 +07:00
|
|
|
#define PPC_INST_MFTMR 0x7c0002dc
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_MSGSND 0x7c00019c
|
2015-03-19 15:29:01 +07:00
|
|
|
#define PPC_INST_MSGCLR 0x7c0001dc
|
2017-04-13 17:16:24 +07:00
|
|
|
#define PPC_INST_MSGSYNC 0x7c0006ec
|
2012-11-15 01:49:44 +07:00
|
|
|
#define PPC_INST_MSGSNDP 0x7c00011c
|
2017-06-13 20:05:48 +07:00
|
|
|
#define PPC_INST_MSGCLRP 0x7c00015c
|
KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
POWER9 has hardware bugs relating to transactional memory and thread
reconfiguration (changes to hardware SMT mode). Specifically, the core
does not have enough storage to store a complete checkpoint of all the
architected state for all four threads. The DD2.2 version of POWER9
includes hardware modifications designed to allow hypervisor software
to implement workarounds for these problems. This patch implements
those workarounds in KVM code so that KVM guests see a full, working
transactional memory implementation.
The problems center around the use of TM suspended state, where the
CPU has a checkpointed state but execution is not transactional. The
workaround is to implement a "fake suspend" state, which looks to the
guest like suspended state but the CPU does not store a checkpoint.
In this state, any instruction that would cause a transition to
transactional state (rfid, rfebb, mtmsrd, tresume) or would use the
checkpointed state (treclaim) causes a "soft patch" interrupt (vector
0x1500) to the hypervisor so that it can be emulated. The trechkpt
instruction also causes a soft patch interrupt.
On POWER9 DD2.2, we avoid returning to the guest in any state which
would require a checkpoint to be present. The trechkpt in the guest
entry path which would normally create that checkpoint is replaced by
either a transition to fake suspend state, if the guest is in suspend
state, or a rollback to the pre-transactional state if the guest is in
transactional state. Fake suspend state is indicated by a flag in the
PACA plus a new bit in the PSSCR. The new PSSCR bit is write-only and
reads back as 0.
On exit from the guest, if the guest is in fake suspend state, we still
do the treclaim instruction as we would in real suspend state, in order
to get into non-transactional state, but we do not save the resulting
register state since there was no checkpoint.
Emulation of the instructions that cause a softpatch interrupt is
handled in two paths. If the guest is in real suspend mode, we call
kvmhv_p9_tm_emulation_early() to handle the cases where the guest is
transitioning to transactional state. This is called before we do the
treclaim in the guest exit path; because we haven't done treclaim, we
can get back to the guest with the transaction still active. If the
instruction is a case that kvmhv_p9_tm_emulation_early() doesn't
handle, or if the guest is in fake suspend state, then we proceed to
do the complete guest exit path and subsequently call
kvmhv_p9_tm_emulation() in host context with the MMU on. This handles
all the cases including the cases that generate program interrupts
(illegal instruction or TM Bad Thing) and facility unavailable
interrupts.
The emulation is reasonably straightforward and is mostly concerned
with checking for exception conditions and updating the state of
registers such as MSR and CR0. The treclaim emulation takes care to
ensure that the TEXASR register gets updated as if it were the guest
treclaim instruction that had done failure recording, not the treclaim
done in hypervisor state in the guest exit path.
With this, the KVM_CAP_PPC_HTM capability returns true (1) even if
transactional memory is not available to host userspace.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-03-21 17:32:01 +07:00
|
|
|
#define PPC_INST_MTMSRD 0x7c000164
|
2011-12-08 14:20:27 +07:00
|
|
|
#define PPC_INST_MTTMR 0x7c0003dc
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_NOP 0x60000000
|
2017-06-08 22:36:09 +07:00
|
|
|
#define PPC_INST_PASTE 0x7c20070d
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_POPCNTB 0x7c0000f4
|
|
|
|
|
#define PPC_INST_POPCNTB_MASK 0xfc0007fe
|
2010-12-08 02:58:17 +07:00
|
|
|
#define PPC_INST_POPCNTD 0x7c0003f4
|
|
|
|
|
#define PPC_INST_POPCNTW 0x7c0002f4
|
KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
POWER9 has hardware bugs relating to transactional memory and thread
reconfiguration (changes to hardware SMT mode). Specifically, the core
does not have enough storage to store a complete checkpoint of all the
architected state for all four threads. The DD2.2 version of POWER9
includes hardware modifications designed to allow hypervisor software
to implement workarounds for these problems. This patch implements
those workarounds in KVM code so that KVM guests see a full, working
transactional memory implementation.
The problems center around the use of TM suspended state, where the
CPU has a checkpointed state but execution is not transactional. The
workaround is to implement a "fake suspend" state, which looks to the
guest like suspended state but the CPU does not store a checkpoint.
In this state, any instruction that would cause a transition to
transactional state (rfid, rfebb, mtmsrd, tresume) or would use the
checkpointed state (treclaim) causes a "soft patch" interrupt (vector
0x1500) to the hypervisor so that it can be emulated. The trechkpt
instruction also causes a soft patch interrupt.
On POWER9 DD2.2, we avoid returning to the guest in any state which
would require a checkpoint to be present. The trechkpt in the guest
entry path which would normally create that checkpoint is replaced by
either a transition to fake suspend state, if the guest is in suspend
state, or a rollback to the pre-transactional state if the guest is in
transactional state. Fake suspend state is indicated by a flag in the
PACA plus a new bit in the PSSCR. The new PSSCR bit is write-only and
reads back as 0.
On exit from the guest, if the guest is in fake suspend state, we still
do the treclaim instruction as we would in real suspend state, in order
to get into non-transactional state, but we do not save the resulting
register state since there was no checkpoint.
Emulation of the instructions that cause a softpatch interrupt is
handled in two paths. If the guest is in real suspend mode, we call
kvmhv_p9_tm_emulation_early() to handle the cases where the guest is
transitioning to transactional state. This is called before we do the
treclaim in the guest exit path; because we haven't done treclaim, we
can get back to the guest with the transaction still active. If the
instruction is a case that kvmhv_p9_tm_emulation_early() doesn't
handle, or if the guest is in fake suspend state, then we proceed to
do the complete guest exit path and subsequently call
kvmhv_p9_tm_emulation() in host context with the MMU on. This handles
all the cases including the cases that generate program interrupts
(illegal instruction or TM Bad Thing) and facility unavailable
interrupts.
The emulation is reasonably straightforward and is mostly concerned
with checking for exception conditions and updating the state of
registers such as MSR and CR0. The treclaim emulation takes care to
ensure that the TEXASR register gets updated as if it were the guest
treclaim instruction that had done failure recording, not the treclaim
done in hypervisor state in the guest exit path.
With this, the KVM_CAP_PPC_HTM capability returns true (1) even if
transactional memory is not available to host userspace.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-03-21 17:32:01 +07:00
|
|
|
#define PPC_INST_RFEBB 0x4c000124
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_RFCI 0x4c000066
|
|
|
|
|
#define PPC_INST_RFDI 0x4c00004e
|
KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
POWER9 has hardware bugs relating to transactional memory and thread
reconfiguration (changes to hardware SMT mode). Specifically, the core
does not have enough storage to store a complete checkpoint of all the
architected state for all four threads. The DD2.2 version of POWER9
includes hardware modifications designed to allow hypervisor software
to implement workarounds for these problems. This patch implements
those workarounds in KVM code so that KVM guests see a full, working
transactional memory implementation.
The problems center around the use of TM suspended state, where the
CPU has a checkpointed state but execution is not transactional. The
workaround is to implement a "fake suspend" state, which looks to the
guest like suspended state but the CPU does not store a checkpoint.
In this state, any instruction that would cause a transition to
transactional state (rfid, rfebb, mtmsrd, tresume) or would use the
checkpointed state (treclaim) causes a "soft patch" interrupt (vector
0x1500) to the hypervisor so that it can be emulated. The trechkpt
instruction also causes a soft patch interrupt.
On POWER9 DD2.2, we avoid returning to the guest in any state which
would require a checkpoint to be present. The trechkpt in the guest
entry path which would normally create that checkpoint is replaced by
either a transition to fake suspend state, if the guest is in suspend
state, or a rollback to the pre-transactional state if the guest is in
transactional state. Fake suspend state is indicated by a flag in the
PACA plus a new bit in the PSSCR. The new PSSCR bit is write-only and
reads back as 0.
On exit from the guest, if the guest is in fake suspend state, we still
do the treclaim instruction as we would in real suspend state, in order
to get into non-transactional state, but we do not save the resulting
register state since there was no checkpoint.
Emulation of the instructions that cause a softpatch interrupt is
handled in two paths. If the guest is in real suspend mode, we call
kvmhv_p9_tm_emulation_early() to handle the cases where the guest is
transitioning to transactional state. This is called before we do the
treclaim in the guest exit path; because we haven't done treclaim, we
can get back to the guest with the transaction still active. If the
instruction is a case that kvmhv_p9_tm_emulation_early() doesn't
handle, or if the guest is in fake suspend state, then we proceed to
do the complete guest exit path and subsequently call
kvmhv_p9_tm_emulation() in host context with the MMU on. This handles
all the cases including the cases that generate program interrupts
(illegal instruction or TM Bad Thing) and facility unavailable
interrupts.
The emulation is reasonably straightforward and is mostly concerned
with checking for exception conditions and updating the state of
registers such as MSR and CR0. The treclaim emulation takes care to
ensure that the TEXASR register gets updated as if it were the guest
treclaim instruction that had done failure recording, not the treclaim
done in hypervisor state in the guest exit path.
With this, the KVM_CAP_PPC_HTM capability returns true (1) even if
transactional memory is not available to host userspace.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-03-21 17:32:01 +07:00
|
|
|
#define PPC_INST_RFID 0x4c000024
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_RFMCI 0x4c00004c
|
2018-01-12 19:45:23 +07:00
|
|
|
#define PPC_INST_MFSPR 0x7c0002a6
|
2011-03-02 22:18:48 +07:00
|
|
|
#define PPC_INST_MFSPR_DSCR 0x7c1102a6
|
2017-01-19 10:19:10 +07:00
|
|
|
#define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe
|
2011-03-02 22:18:48 +07:00
|
|
|
#define PPC_INST_MTSPR_DSCR 0x7c1103a6
|
2017-01-19 10:19:10 +07:00
|
|
|
#define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe
|
2013-05-02 03:06:33 +07:00
|
|
|
#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
|
2017-01-19 10:19:10 +07:00
|
|
|
#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe
|
2013-05-02 03:06:33 +07:00
|
|
|
#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
|
2017-01-19 10:19:10 +07:00
|
|
|
#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe
|
2016-07-01 05:19:45 +07:00
|
|
|
#define PPC_INST_MFVSRD 0x7c000066
|
|
|
|
|
#define PPC_INST_MTVSRD 0x7c000166
|
2018-11-10 00:33:28 +07:00
|
|
|
#define PPC_INST_SC 0x44000002
|
KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 19:36:37 +07:00
|
|
|
#define PPC_INST_SLBFEE 0x7c0007a7
|
2016-07-13 16:35:27 +07:00
|
|
|
#define PPC_INST_SLBIA 0x7c0003e4
|
2009-02-11 03:10:44 +07:00
|
|
|
|
|
|
|
|
#define PPC_INST_STRING 0x7c00042a
|
|
|
|
|
#define PPC_INST_STRING_MASK 0xfc0007fe
|
|
|
|
|
#define PPC_INST_STRING_GEN_MASK 0xfc00067e
|
|
|
|
|
|
|
|
|
|
#define PPC_INST_STSWI 0x7c0005aa
|
|
|
|
|
#define PPC_INST_STSWX 0x7c00052a
|
2009-04-30 03:58:01 +07:00
|
|
|
#define PPC_INST_STXVD2X 0x7c000798
|
2009-04-30 03:58:01 +07:00
|
|
|
#define PPC_INST_TLBIE 0x7c000264
|
2016-07-13 16:35:20 +07:00
|
|
|
#define PPC_INST_TLBIEL 0x7c000224
|
2009-04-07 03:25:52 +07:00
|
|
|
#define PPC_INST_TLBILX 0x7c000024
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_INST_WAIT 0x7c00007c
|
2009-07-24 06:15:11 +07:00
|
|
|
#define PPC_INST_TLBIVAX 0x7c000624
|
|
|
|
|
#define PPC_INST_TLBSRX_DOT 0x7c0006a5
|
2016-07-01 05:19:45 +07:00
|
|
|
#define PPC_INST_VPMSUMW 0x10000488
|
|
|
|
|
#define PPC_INST_VPMSUMD 0x100004c8
|
2017-08-04 10:42:32 +07:00
|
|
|
#define PPC_INST_VPERMXOR 0x1000002d
|
2017-08-30 11:12:24 +07:00
|
|
|
#define PPC_INST_XXLOR 0xf0000490
|
2013-09-23 09:04:39 +07:00
|
|
|
#define PPC_INST_XXSWAPD 0xf0000250
|
2012-09-10 07:35:26 +07:00
|
|
|
#define PPC_INST_XVCPSGNDP 0xf0000780
|
2013-02-13 23:21:30 +07:00
|
|
|
#define PPC_INST_TRECHKPT 0x7c0007dd
|
|
|
|
|
#define PPC_INST_TRECLAIM 0x7c00075d
|
|
|
|
|
#define PPC_INST_TABORT 0x7c00071d
|
KVM: PPC: Book3S HV: Work around transactional memory bugs in POWER9
POWER9 has hardware bugs relating to transactional memory and thread
reconfiguration (changes to hardware SMT mode). Specifically, the core
does not have enough storage to store a complete checkpoint of all the
architected state for all four threads. The DD2.2 version of POWER9
includes hardware modifications designed to allow hypervisor software
to implement workarounds for these problems. This patch implements
those workarounds in KVM code so that KVM guests see a full, working
transactional memory implementation.
The problems center around the use of TM suspended state, where the
CPU has a checkpointed state but execution is not transactional. The
workaround is to implement a "fake suspend" state, which looks to the
guest like suspended state but the CPU does not store a checkpoint.
In this state, any instruction that would cause a transition to
transactional state (rfid, rfebb, mtmsrd, tresume) or would use the
checkpointed state (treclaim) causes a "soft patch" interrupt (vector
0x1500) to the hypervisor so that it can be emulated. The trechkpt
instruction also causes a soft patch interrupt.
On POWER9 DD2.2, we avoid returning to the guest in any state which
would require a checkpoint to be present. The trechkpt in the guest
entry path which would normally create that checkpoint is replaced by
either a transition to fake suspend state, if the guest is in suspend
state, or a rollback to the pre-transactional state if the guest is in
transactional state. Fake suspend state is indicated by a flag in the
PACA plus a new bit in the PSSCR. The new PSSCR bit is write-only and
reads back as 0.
On exit from the guest, if the guest is in fake suspend state, we still
do the treclaim instruction as we would in real suspend state, in order
to get into non-transactional state, but we do not save the resulting
register state since there was no checkpoint.
Emulation of the instructions that cause a softpatch interrupt is
handled in two paths. If the guest is in real suspend mode, we call
kvmhv_p9_tm_emulation_early() to handle the cases where the guest is
transitioning to transactional state. This is called before we do the
treclaim in the guest exit path; because we haven't done treclaim, we
can get back to the guest with the transaction still active. If the
instruction is a case that kvmhv_p9_tm_emulation_early() doesn't
handle, or if the guest is in fake suspend state, then we proceed to
do the complete guest exit path and subsequently call
kvmhv_p9_tm_emulation() in host context with the MMU on. This handles
all the cases including the cases that generate program interrupts
(illegal instruction or TM Bad Thing) and facility unavailable
interrupts.
The emulation is reasonably straightforward and is mostly concerned
with checking for exception conditions and updating the state of
registers such as MSR and CR0. The treclaim emulation takes care to
ensure that the TEXASR register gets updated as if it were the guest
treclaim instruction that had done failure recording, not the treclaim
done in hypervisor state in the guest exit path.
With this, the KVM_CAP_PPC_HTM capability returns true (1) even if
transactional memory is not available to host userspace.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-03-21 17:32:01 +07:00
|
|
|
#define PPC_INST_TSR 0x7c0005dd
|
2009-02-11 03:10:44 +07:00
|
|
|
|
2011-01-24 14:42:41 +07:00
|
|
|
#define PPC_INST_NAP 0x4c000364
|
|
|
|
|
#define PPC_INST_SLEEP 0x4c0003a4
|
2014-12-10 01:56:53 +07:00
|
|
|
#define PPC_INST_WINKLE 0x4c0003e4
|
2011-01-24 14:42:41 +07:00
|
|
|
|
2016-07-08 13:20:49 +07:00
|
|
|
#define PPC_INST_STOP 0x4c0002e4
|
|
|
|
|
|
2011-04-15 05:31:56 +07:00
|
|
|
/* A2 specific instructions */
|
|
|
|
|
#define PPC_INST_ERATWE 0x7c0001a6
|
|
|
|
|
#define PPC_INST_ERATRE 0x7c000166
|
|
|
|
|
#define PPC_INST_ERATILX 0x7c000066
|
|
|
|
|
#define PPC_INST_ERATIVAX 0x7c000666
|
|
|
|
|
#define PPC_INST_ERATSX 0x7c000126
|
|
|
|
|
#define PPC_INST_ERATSX_DOT 0x7c000127
|
|
|
|
|
|
2011-07-20 22:51:00 +07:00
|
|
|
/* Misc instructions for BPF compiler */
|
2014-10-30 13:12:15 +07:00
|
|
|
#define PPC_INST_LBZ 0x88000000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_LD 0xe8000000
|
|
|
|
|
#define PPC_INST_LHZ 0xa0000000
|
|
|
|
|
#define PPC_INST_LWZ 0x80000000
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_LHBRX 0x7c00062c
|
|
|
|
|
#define PPC_INST_LDBRX 0x7c000428
|
|
|
|
|
#define PPC_INST_STB 0x98000000
|
|
|
|
|
#define PPC_INST_STH 0xb0000000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_STD 0xf8000000
|
|
|
|
|
#define PPC_INST_STDU 0xf8000001
|
2015-02-17 14:04:39 +07:00
|
|
|
#define PPC_INST_STW 0x90000000
|
|
|
|
|
#define PPC_INST_STWU 0x94000000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_MFLR 0x7c0802a6
|
|
|
|
|
#define PPC_INST_MTLR 0x7c0803a6
|
2016-09-24 03:35:01 +07:00
|
|
|
#define PPC_INST_MTCTR 0x7c0903a6
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_CMPWI 0x2c000000
|
|
|
|
|
#define PPC_INST_CMPDI 0x2c200000
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_CMPW 0x7c000000
|
|
|
|
|
#define PPC_INST_CMPD 0x7c200000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_CMPLW 0x7c000040
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_CMPLD 0x7c200040
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_CMPLWI 0x28000000
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_CMPLDI 0x28200000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_ADDI 0x38000000
|
|
|
|
|
#define PPC_INST_ADDIS 0x3c000000
|
|
|
|
|
#define PPC_INST_ADD 0x7c000214
|
|
|
|
|
#define PPC_INST_SUB 0x7c000050
|
|
|
|
|
#define PPC_INST_BLR 0x4e800020
|
|
|
|
|
#define PPC_INST_BLRL 0x4e800021
|
2016-09-24 03:35:01 +07:00
|
|
|
#define PPC_INST_BCTR 0x4e800420
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_MULLD 0x7c0001d2
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_MULLW 0x7c0001d6
|
|
|
|
|
#define PPC_INST_MULHWU 0x7c000016
|
|
|
|
|
#define PPC_INST_MULLI 0x1c000000
|
2013-09-28 15:22:00 +07:00
|
|
|
#define PPC_INST_DIVWU 0x7c000396
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_DIVD 0x7c0003d2
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_RLWINM 0x54000000
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_RLWIMI 0x50000000
|
|
|
|
|
#define PPC_INST_RLDICL 0x78000000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_RLDICR 0x78000004
|
|
|
|
|
#define PPC_INST_SLW 0x7c000030
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_SLD 0x7c000036
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_SRW 0x7c000430
|
2018-12-06 01:52:31 +07:00
|
|
|
#define PPC_INST_SRAW 0x7c000630
|
|
|
|
|
#define PPC_INST_SRAWI 0x7c000670
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_SRD 0x7c000436
|
|
|
|
|
#define PPC_INST_SRAD 0x7c000634
|
|
|
|
|
#define PPC_INST_SRADI 0x7c000674
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_AND 0x7c000038
|
|
|
|
|
#define PPC_INST_ANDDOT 0x7c000039
|
|
|
|
|
#define PPC_INST_OR 0x7c000378
|
2012-11-08 18:39:41 +07:00
|
|
|
#define PPC_INST_XOR 0x7c000278
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_ANDI 0x70000000
|
|
|
|
|
#define PPC_INST_ORI 0x60000000
|
|
|
|
|
#define PPC_INST_ORIS 0x64000000
|
2012-11-08 18:39:41 +07:00
|
|
|
#define PPC_INST_XORI 0x68000000
|
|
|
|
|
#define PPC_INST_XORIS 0x6c000000
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_NEG 0x7c0000d0
|
2016-06-22 23:25:07 +07:00
|
|
|
#define PPC_INST_EXTSW 0x7c0007b4
|
2011-07-20 22:51:00 +07:00
|
|
|
#define PPC_INST_BRANCH 0x48000000
|
|
|
|
|
#define PPC_INST_BRANCH_COND 0x40800000
|
2012-06-25 20:33:13 +07:00
|
|
|
#define PPC_INST_LBZCIX 0x7c0006aa
|
|
|
|
|
#define PPC_INST_STBCIX 0x7c0007aa
|
2017-02-14 16:16:43 +07:00
|
|
|
#define PPC_INST_LWZX 0x7c00002e
|
|
|
|
|
#define PPC_INST_LFSX 0x7c00042e
|
|
|
|
|
#define PPC_INST_STFSX 0x7c00052e
|
|
|
|
|
#define PPC_INST_LFDX 0x7c0004ae
|
|
|
|
|
#define PPC_INST_STFDX 0x7c0005ae
|
|
|
|
|
#define PPC_INST_LVX 0x7c0000ce
|
|
|
|
|
#define PPC_INST_STVX 0x7c0001ce
|
2018-06-07 08:57:52 +07:00
|
|
|
#define PPC_INST_VCMPEQUD 0x100000c7
|
|
|
|
|
#define PPC_INST_VCMPEQUB 0x10000006
|
2011-07-20 22:51:00 +07:00
|
|
|
|
2009-02-11 03:10:44 +07:00
|
|
|
/* macros to insert fields into opcodes */
|
2012-06-25 20:33:20 +07:00
|
|
|
#define ___PPC_RA(a) (((a) & 0x1f) << 16)
|
|
|
|
|
#define ___PPC_RB(b) (((b) & 0x1f) << 11)
|
|
|
|
|
#define ___PPC_RS(s) (((s) & 0x1f) << 21)
|
|
|
|
|
#define ___PPC_RT(t) ___PPC_RS(t)
|
2016-07-13 16:35:20 +07:00
|
|
|
#define ___PPC_R(r) (((r) & 0x1) << 16)
|
|
|
|
|
#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
|
|
|
|
|
#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
|
2012-06-25 20:33:23 +07:00
|
|
|
#define __PPC_RA(a) ___PPC_RA(__REG_##a)
|
2012-06-25 20:33:24 +07:00
|
|
|
#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
|
2012-06-25 20:33:23 +07:00
|
|
|
#define __PPC_RB(b) ___PPC_RB(__REG_##b)
|
|
|
|
|
#define __PPC_RS(s) ___PPC_RS(__REG_##s)
|
|
|
|
|
#define __PPC_RT(t) ___PPC_RT(__REG_##t)
|
powerpc: Emulate most Book I instructions in emulate_step()
This extends the emulate_step() function to handle a large proportion
of the Book I instructions implemented on current 64-bit server
processors. The aim is to handle all the load and store instructions
used in the kernel, plus all of the instructions that appear between
l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
The new code can emulate user mode instructions, and checks the
effective address for a load or store if the saved state is for
user mode. It doesn't handle little-endian mode at present.
For floating-point, Altivec/VMX and VSX instructions, it checks
that the saved MSR has the enable bit for the relevant facility
set, and if so, assumes that the FP/VMX/VSX registers contain
valid state, and does loads or stores directly to/from the
FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
Instructions supported now include:
* Loads and stores, including some but not all VMX and VSX instructions,
and lmw/stmw
* Atomic loads and stores (l[dw]arx, st[dw]cx.)
* Arithmetic instructions (add, subtract, multiply, divide, etc.)
* Compare instructions
* Rotate and mask instructions
* Shift instructions
* Logical instructions (and, or, xor, etc.)
* Condition register logical instructions
* mtcrf, cntlz[wd], exts[bhw]
* isync, sync, lwsync, ptesync, eieio
* Cache operations (dcbf, dcbst, dcbt, dcbtst)
The overflow-checking arithmetic instructions are not included, but
they appear not to be ever used in C code.
This uses decimal values for the minor opcodes in the switch statements
because that is what appears in the Power ISA specification, thus it is
easier to check that they are correct if they are in decimal.
If this is used to single-step an instruction where a data breakpoint
interrupt occurred, then there is the possibility that the instruction
is a lwarx or ldarx. In that case we have to be careful not to lose the
reservation until we get to the matching st[wd]cx., or we'll never make
forward progress. One alternative is to try to arrange that we can
return from interrupts and handle data breakpoint interrupts without
losing the reservation, which means not using any spinlocks, mutexes,
or atomic ops (including bitops). That seems rather fragile. The
other alternative is to emulate the larx/stcx and all the instructions
in between. This is why this commit adds support for a wide range
of integer instructions.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2010-06-15 11:48:58 +07:00
|
|
|
#define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
|
|
|
|
|
#define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
|
2009-04-30 03:58:01 +07:00
|
|
|
#define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
|
powerpc: Emulate most Book I instructions in emulate_step()
This extends the emulate_step() function to handle a large proportion
of the Book I instructions implemented on current 64-bit server
processors. The aim is to handle all the load and store instructions
used in the kernel, plus all of the instructions that appear between
l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
The new code can emulate user mode instructions, and checks the
effective address for a load or store if the saved state is for
user mode. It doesn't handle little-endian mode at present.
For floating-point, Altivec/VMX and VSX instructions, it checks
that the saved MSR has the enable bit for the relevant facility
set, and if so, assumes that the FP/VMX/VSX registers contain
valid state, and does loads or stores directly to/from the
FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
Instructions supported now include:
* Loads and stores, including some but not all VMX and VSX instructions,
and lmw/stmw
* Atomic loads and stores (l[dw]arx, st[dw]cx.)
* Arithmetic instructions (add, subtract, multiply, divide, etc.)
* Compare instructions
* Rotate and mask instructions
* Shift instructions
* Logical instructions (and, or, xor, etc.)
* Condition register logical instructions
* mtcrf, cntlz[wd], exts[bhw]
* isync, sync, lwsync, ptesync, eieio
* Cache operations (dcbf, dcbst, dcbt, dcbtst)
The overflow-checking arithmetic instructions are not included, but
they appear not to be ever used in C code.
This uses decimal values for the minor opcodes in the switch statements
because that is what appears in the Power ISA specification, thus it is
easier to check that they are correct if they are in decimal.
If this is used to single-step an instruction where a data breakpoint
interrupt occurred, then there is the possibility that the instruction
is a lwarx or ldarx. In that case we have to be careful not to lose the
reservation until we get to the matching st[wd]cx., or we'll never make
forward progress. One alternative is to try to arrange that we can
return from interrupts and handle data breakpoint interrupts without
losing the reservation, which means not using any spinlocks, mutexes,
or atomic ops (including bitops). That seems rather fragile. The
other alternative is to emulate the larx/stcx and all the instructions
in between. This is why this commit adds support for a wide range
of integer instructions.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2010-06-15 11:48:58 +07:00
|
|
|
#define __PPC_XT(s) __PPC_XS(s)
|
2009-04-30 03:58:01 +07:00
|
|
|
#define __PPC_T_TLB(t) (((t) & 0x3) << 21)
|
|
|
|
|
#define __PPC_WC(w) (((w) & 0x3) << 21)
|
2011-04-15 05:31:56 +07:00
|
|
|
#define __PPC_WS(w) (((w) & 0x1f) << 11)
|
2011-07-20 22:51:00 +07:00
|
|
|
#define __PPC_SH(s) __PPC_WS(s)
|
2017-02-08 15:57:29 +07:00
|
|
|
#define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4))
|
2011-07-20 22:51:00 +07:00
|
|
|
#define __PPC_MB(s) (((s) & 0x1f) << 6)
|
|
|
|
|
#define __PPC_ME(s) (((s) & 0x1f) << 1)
|
2016-06-22 23:25:04 +07:00
|
|
|
#define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20))
|
|
|
|
|
#define __PPC_ME64(s) __PPC_MB64(s)
|
2011-07-20 22:51:00 +07:00
|
|
|
#define __PPC_BI(s) (((s) & 0x1f) << 16)
|
2012-10-02 22:52:19 +07:00
|
|
|
#define __PPC_CT(t) (((t) & 0x0f) << 21)
|
2018-01-12 19:45:23 +07:00
|
|
|
#define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
|
2018-06-07 08:57:52 +07:00
|
|
|
#define __PPC_RC21 (0x1 << 10)
|
2011-04-15 05:31:56 +07:00
|
|
|
|
2010-02-10 07:57:28 +07:00
|
|
|
/*
|
2010-03-11 12:33:25 +07:00
|
|
|
* Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
|
|
|
|
|
* larx with EH set as an illegal instruction.
|
2010-02-10 07:57:28 +07:00
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
#define __PPC_EH(eh) (((eh) & 0x1) << 0)
|
|
|
|
|
#else
|
|
|
|
|
#define __PPC_EH(eh) 0
|
|
|
|
|
#endif
|
2009-02-11 03:10:44 +07:00
|
|
|
|
|
|
|
|
/* Deal with instructions that older assemblers aren't aware of */
|
2016-04-26 07:28:50 +07:00
|
|
|
#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
|
2017-06-08 22:36:09 +07:00
|
|
|
#define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \
|
|
|
|
|
___PPC_RA(a) | ___PPC_RB(b))
|
2017-08-04 08:12:18 +07:00
|
|
|
#define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \
|
|
|
|
|
___PPC_RT(t) | \
|
|
|
|
|
(((l) & 0x3) << 16))
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \
|
|
|
|
|
__PPC_RA(a) | __PPC_RB(b))
|
|
|
|
|
#define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \
|
|
|
|
|
__PPC_RA(a) | __PPC_RB(b))
|
powerpc: Handle most loads and stores in instruction emulation code
This extends the instruction emulation infrastructure in sstep.c to
handle all the load and store instructions defined in the Power ISA
v3.0, except for the atomic memory operations, ldmx (which was never
implemented), lfdp/stfdp, and the vector element load/stores.
The instructions added are:
Integer loads and stores: lbarx, lharx, lqarx, stbcx., sthcx., stqcx.,
lq, stq.
VSX loads and stores: lxsiwzx, lxsiwax, stxsiwx, lxvx, lxvl, lxvll,
lxvdsx, lxvwsx, stxvx, stxvl, stxvll, lxsspx, lxsdx, stxsspx, stxsdx,
lxvw4x, lxsibzx, lxvh8x, lxsihzx, lxvb16x, stxvw4x, stxsibx, stxvh8x,
stxsihx, stxvb16x, lxsd, lxssp, lxv, stxsd, stxssp, stxv.
These instructions are handled both in the analyse_instr phase and in
the emulate_step phase.
The code for lxvd2ux and stxvd2ux has been taken out, as those
instructions were never implemented in any processor and have been
taken out of the architecture, and their opcodes have been reused for
other instructions in POWER9 (lxvb16x and stxvb16x).
The emulation for the VSX loads and stores uses helper functions
which don't access registers or memory directly, which can hopefully
be reused by KVM later.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-30 11:12:27 +07:00
|
|
|
#define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \
|
|
|
|
|
___PPC_RT(t) | ___PPC_RA(a) | \
|
|
|
|
|
___PPC_RB(b) | __PPC_EH(eh))
|
2010-02-10 08:02:36 +07:00
|
|
|
#define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \
|
2012-06-25 20:33:21 +07:00
|
|
|
___PPC_RT(t) | ___PPC_RA(a) | \
|
|
|
|
|
___PPC_RB(b) | __PPC_EH(eh))
|
2010-02-10 07:57:28 +07:00
|
|
|
#define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \
|
2012-06-25 20:33:21 +07:00
|
|
|
___PPC_RT(t) | ___PPC_RA(a) | \
|
|
|
|
|
___PPC_RB(b) | __PPC_EH(eh))
|
powerpc: Handle most loads and stores in instruction emulation code
This extends the instruction emulation infrastructure in sstep.c to
handle all the load and store instructions defined in the Power ISA
v3.0, except for the atomic memory operations, ldmx (which was never
implemented), lfdp/stfdp, and the vector element load/stores.
The instructions added are:
Integer loads and stores: lbarx, lharx, lqarx, stbcx., sthcx., stqcx.,
lq, stq.
VSX loads and stores: lxsiwzx, lxsiwax, stxsiwx, lxvx, lxvl, lxvll,
lxvdsx, lxvwsx, stxvx, stxvl, stxvll, lxsspx, lxsdx, stxsspx, stxsdx,
lxvw4x, lxsibzx, lxvh8x, lxsihzx, lxvb16x, stxvw4x, stxsibx, stxvh8x,
stxsihx, stxvb16x, lxsd, lxssp, lxv, stxsd, stxssp, stxv.
These instructions are handled both in the analyse_instr phase and in
the emulate_step phase.
The code for lxvd2ux and stxvd2ux has been taken out, as those
instructions were never implemented in any processor and have been
taken out of the architecture, and their opcodes have been reused for
other instructions in POWER9 (lxvb16x and stxvb16x).
The emulation for the VSX loads and stores uses helper functions
which don't access registers or memory directly, which can hopefully
be reused by KVM later.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2017-08-30 11:12:27 +07:00
|
|
|
#define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \
|
|
|
|
|
___PPC_RT(t) | ___PPC_RA(a) | \
|
|
|
|
|
___PPC_RB(b))
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \
|
2012-06-25 20:33:21 +07:00
|
|
|
___PPC_RB(b))
|
2017-04-13 17:16:24 +07:00
|
|
|
#define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC)
|
2015-03-19 15:29:01 +07:00
|
|
|
#define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \
|
|
|
|
|
___PPC_RB(b))
|
2012-11-15 01:49:44 +07:00
|
|
|
#define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \
|
|
|
|
|
___PPC_RB(b))
|
2017-06-13 20:05:48 +07:00
|
|
|
#define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \
|
|
|
|
|
___PPC_RB(b))
|
2017-08-29 13:23:40 +07:00
|
|
|
#define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \
|
|
|
|
|
___PPC_RA(a) | ___PPC_RB(b))
|
2010-12-08 02:58:17 +07:00
|
|
|
#define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
|
|
|
|
|
__PPC_RA(a) | __PPC_RS(s))
|
|
|
|
|
#define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
|
|
|
|
|
__PPC_RA(a) | __PPC_RS(s))
|
|
|
|
|
#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
|
|
|
|
|
__PPC_RA(a) | __PPC_RS(s))
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
|
|
|
|
|
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
|
|
|
|
|
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
|
|
|
|
|
#define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
|
2009-02-11 03:10:44 +07:00
|
|
|
#define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b)
|
|
|
|
|
#define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b)
|
|
|
|
|
#define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b)
|
|
|
|
|
#define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \
|
|
|
|
|
__PPC_WC(w))
|
2009-04-30 03:58:01 +07:00
|
|
|
#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
|
2012-06-25 20:33:21 +07:00
|
|
|
___PPC_RB(a) | ___PPC_RS(lp))
|
2016-07-13 16:35:20 +07:00
|
|
|
#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
|
|
|
|
|
stringify_in_c(.long PPC_INST_TLBIE | \
|
|
|
|
|
___PPC_RB(rb) | ___PPC_RS(rs) | \
|
|
|
|
|
___PPC_RIC(ric) | ___PPC_PRS(prs) | \
|
|
|
|
|
___PPC_R(r))
|
|
|
|
|
#define PPC_TLBIEL(rb,rs,ric,prs,r) \
|
|
|
|
|
stringify_in_c(.long PPC_INST_TLBIEL | \
|
|
|
|
|
___PPC_RB(rb) | ___PPC_RS(rs) | \
|
|
|
|
|
___PPC_RIC(ric) | ___PPC_PRS(prs) | \
|
|
|
|
|
___PPC_R(r))
|
2009-07-24 06:15:11 +07:00
|
|
|
#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_RA0(a) | __PPC_RB(b))
|
2009-07-24 06:15:11 +07:00
|
|
|
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_RA0(a) | __PPC_RB(b))
|
2009-02-11 03:10:44 +07:00
|
|
|
|
2011-04-15 05:31:56 +07:00
|
|
|
#define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \
|
|
|
|
|
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
|
|
|
|
#define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \
|
|
|
|
|
__PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
|
|
|
|
|
#define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_T_TLB(t) | __PPC_RA0(a) | \
|
2011-04-15 05:31:56 +07:00
|
|
|
__PPC_RB(b))
|
|
|
|
|
#define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
|
2011-04-15 05:31:56 +07:00
|
|
|
#define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
|
2011-04-15 05:31:56 +07:00
|
|
|
#define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
|
2012-06-25 20:33:25 +07:00
|
|
|
__PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
|
KVM: PPC: Implement MMIO emulation support for Book3S HV guests
This provides the low-level support for MMIO emulation in Book3S HV
guests. When the guest tries to map a page which is not covered by
any memslot, that page is taken to be an MMIO emulation page. Instead
of inserting a valid HPTE, we insert an HPTE that has the valid bit
clear but another hypervisor software-use bit set, which we call
HPTE_V_ABSENT, to indicate that this is an absent page. An
absent page is treated much like a valid page as far as guest hcalls
(H_ENTER, H_REMOVE, H_READ etc.) are concerned, except of course that
an absent HPTE doesn't need to be invalidated with tlbie since it
was never valid as far as the hardware is concerned.
When the guest accesses a page for which there is an absent HPTE, it
will take a hypervisor data storage interrupt (HDSI) since we now set
the VPM1 bit in the LPCR. Our HDSI handler for HPTE-not-present faults
looks up the hash table and if it finds an absent HPTE mapping the
requested virtual address, will switch to kernel mode and handle the
fault in kvmppc_book3s_hv_page_fault(), which at present just calls
kvmppc_hv_emulate_mmio() to set up the MMIO emulation.
This is based on an earlier patch by Benjamin Herrenschmidt, but since
heavily reworked.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
2011-12-12 19:36:37 +07:00
|
|
|
#define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
|
|
|
|
|
__PPC_RT(t) | __PPC_RB(b))
|
2018-11-06 15:25:18 +07:00
|
|
|
#define __PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \
|
|
|
|
|
___PPC_RT(t) | ___PPC_RB(b))
|
2012-10-02 22:52:19 +07:00
|
|
|
#define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \
|
|
|
|
|
__PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
|
2012-06-25 20:33:13 +07:00
|
|
|
/* PASemi instructions */
|
|
|
|
|
#define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \
|
|
|
|
|
__PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
|
|
|
|
|
#define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \
|
|
|
|
|
__PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
|
2011-04-15 05:31:56 +07:00
|
|
|
|
2009-04-30 03:58:01 +07:00
|
|
|
/*
|
|
|
|
|
* Define what the VSX XX1 form instructions will look like, then add
|
|
|
|
|
* the 128 bit load store instructions based on that.
|
|
|
|
|
*/
|
|
|
|
|
#define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
|
powerpc: Emulate most Book I instructions in emulate_step()
This extends the emulate_step() function to handle a large proportion
of the Book I instructions implemented on current 64-bit server
processors. The aim is to handle all the load and store instructions
used in the kernel, plus all of the instructions that appear between
l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
The new code can emulate user mode instructions, and checks the
effective address for a load or store if the saved state is for
user mode. It doesn't handle little-endian mode at present.
For floating-point, Altivec/VMX and VSX instructions, it checks
that the saved MSR has the enable bit for the relevant facility
set, and if so, assumes that the FP/VMX/VSX registers contain
valid state, and does loads or stores directly to/from the
FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
Instructions supported now include:
* Loads and stores, including some but not all VMX and VSX instructions,
and lmw/stmw
* Atomic loads and stores (l[dw]arx, st[dw]cx.)
* Arithmetic instructions (add, subtract, multiply, divide, etc.)
* Compare instructions
* Rotate and mask instructions
* Shift instructions
* Logical instructions (and, or, xor, etc.)
* Condition register logical instructions
* mtcrf, cntlz[wd], exts[bhw]
* isync, sync, lwsync, ptesync, eieio
* Cache operations (dcbf, dcbst, dcbt, dcbtst)
The overflow-checking arithmetic instructions are not included, but
they appear not to be ever used in C code.
This uses decimal values for the minor opcodes in the switch statements
because that is what appears in the Power ISA specification, thus it is
easier to check that they are correct if they are in decimal.
If this is used to single-step an instruction where a data breakpoint
interrupt occurred, then there is the possibility that the instruction
is a lwarx or ldarx. In that case we have to be careful not to lose the
reservation until we get to the matching st[wd]cx., or we'll never make
forward progress. One alternative is to try to arrange that we can
return from interrupts and handle data breakpoint interrupts without
losing the reservation, which means not using any spinlocks, mutexes,
or atomic ops (including bitops). That seems rather fragile. The
other alternative is to emulate the larx/stcx and all the instructions
in between. This is why this commit adds support for a wide range
of integer instructions.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2010-06-15 11:48:58 +07:00
|
|
|
#define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
|
2009-04-30 03:58:01 +07:00
|
|
|
#define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \
|
2012-06-25 20:33:19 +07:00
|
|
|
VSX_XX1((s), a, b))
|
2009-04-30 03:58:01 +07:00
|
|
|
#define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \
|
2012-06-25 20:33:19 +07:00
|
|
|
VSX_XX1((s), a, b))
|
2016-07-01 05:19:45 +07:00
|
|
|
#define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \
|
|
|
|
|
VSX_XX1((t)+32, a, R0))
|
|
|
|
|
#define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \
|
|
|
|
|
VSX_XX1((t)+32, a, R0))
|
|
|
|
|
#define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \
|
|
|
|
|
VSX_XX3((t), a, b))
|
|
|
|
|
#define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \
|
|
|
|
|
VSX_XX3((t), a, b))
|
powerpc: Emulate most Book I instructions in emulate_step()
This extends the emulate_step() function to handle a large proportion
of the Book I instructions implemented on current 64-bit server
processors. The aim is to handle all the load and store instructions
used in the kernel, plus all of the instructions that appear between
l[wd]arx and st[wd]cx., so this handles the Altivec/VMX lvx and stvx
and the VSX lxv2dx and stxv2dx instructions (implemented in POWER7).
The new code can emulate user mode instructions, and checks the
effective address for a load or store if the saved state is for
user mode. It doesn't handle little-endian mode at present.
For floating-point, Altivec/VMX and VSX instructions, it checks
that the saved MSR has the enable bit for the relevant facility
set, and if so, assumes that the FP/VMX/VSX registers contain
valid state, and does loads or stores directly to/from the
FP/VMX/VSX registers, using assembly helpers in ldstfp.S.
Instructions supported now include:
* Loads and stores, including some but not all VMX and VSX instructions,
and lmw/stmw
* Atomic loads and stores (l[dw]arx, st[dw]cx.)
* Arithmetic instructions (add, subtract, multiply, divide, etc.)
* Compare instructions
* Rotate and mask instructions
* Shift instructions
* Logical instructions (and, or, xor, etc.)
* Condition register logical instructions
* mtcrf, cntlz[wd], exts[bhw]
* isync, sync, lwsync, ptesync, eieio
* Cache operations (dcbf, dcbst, dcbt, dcbtst)
The overflow-checking arithmetic instructions are not included, but
they appear not to be ever used in C code.
This uses decimal values for the minor opcodes in the switch statements
because that is what appears in the Power ISA specification, thus it is
easier to check that they are correct if they are in decimal.
If this is used to single-step an instruction where a data breakpoint
interrupt occurred, then there is the possibility that the instruction
is a lwarx or ldarx. In that case we have to be careful not to lose the
reservation until we get to the matching st[wd]cx., or we'll never make
forward progress. One alternative is to try to arrange that we can
return from interrupts and handle data breakpoint interrupts without
losing the reservation, which means not using any spinlocks, mutexes,
or atomic ops (including bitops). That seems rather fragile. The
other alternative is to emulate the larx/stcx and all the instructions
in between. This is why this commit adds support for a wide range
of integer instructions.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2010-06-15 11:48:58 +07:00
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#define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \
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2012-06-25 20:33:19 +07:00
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VSX_XX3((t), a, b))
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2013-09-23 09:04:39 +07:00
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#define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \
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VSX_XX3((t), a, a))
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2012-09-10 07:35:26 +07:00
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#define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
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VSX_XX3((t), (a), (b))))
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2009-04-30 03:58:01 +07:00
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2017-08-04 10:42:32 +07:00
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#define VPERMXOR(vrt, vra, vrb, vrc) \
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stringify_in_c(.long (PPC_INST_VPERMXOR | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
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2011-01-24 14:42:41 +07:00
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#define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
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#define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
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2014-12-10 01:56:53 +07:00
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#define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE)
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2011-01-24 14:42:41 +07:00
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2016-07-08 13:20:49 +07:00
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#define PPC_STOP stringify_in_c(.long PPC_INST_STOP)
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2013-04-23 02:42:40 +07:00
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/* BHRB instructions */
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#define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB)
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#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
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__PPC_RT(r) | \
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(((n) & 0x3ff) << 11))
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2013-02-13 23:21:30 +07:00
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/* Transactional memory instructions */
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#define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT)
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#define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \
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| __PPC_RA(r))
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#define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \
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| __PPC_RA(r))
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2011-12-08 14:20:27 +07:00
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/* book3e thread control instructions */
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#define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
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#define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \
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TMRN(tmr) | ___PPC_RS(r))
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#define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \
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TMRN(tmr) | ___PPC_RT(r))
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2015-05-08 00:49:13 +07:00
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/* Coprocessor instructions */
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#define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \
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___PPC_RS(s) | \
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___PPC_RA(a) | \
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___PPC_RB(b))
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#define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \
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___PPC_RS(s) | \
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___PPC_RA(a) | \
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___PPC_RB(b))
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2016-07-13 16:35:27 +07:00
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#define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \
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((IH & 0x7) << 21))
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2016-11-18 10:08:56 +07:00
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#define PPC_INVALIDATE_ERAT PPC_SLBIA(7)
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2015-05-08 00:49:13 +07:00
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2018-06-07 08:57:52 +07:00
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#define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | __PPC_RC21)
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#define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB | \
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___PPC_RT(vrt) | ___PPC_RA(vra) | \
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___PPC_RB(vrb) | __PPC_RC21)
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2009-02-11 03:10:44 +07:00
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#endif /* _ASM_POWERPC_PPC_OPCODE_H */
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