chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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/*
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* This file is part of the Chelsio T6 Crypto driver for Linux.
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*
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* Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Written and Maintained by:
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* Manoj Malviya (manojmalviya@chelsio.com)
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* Atul Gupta (atul.gupta@chelsio.com)
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* Jitendra Lulla (jlulla@chelsio.com)
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* Yeshaswi M R Gowda (yeshaswi@chelsio.com)
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* Harsh Jain (harsh@chelsio.com)
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*/
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#define pr_fmt(fmt) "chcr:" fmt
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/crypto.h>
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#include <linux/cryptohash.h>
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#include <linux/skbuff.h>
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#include <linux/rtnetlink.h>
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#include <linux/highmem.h>
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#include <linux/scatterlist.h>
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#include <crypto/aes.h>
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#include <crypto/algapi.h>
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#include <crypto/hash.h>
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2017-08-22 15:08:15 +07:00
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#include <crypto/gcm.h>
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chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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#include <crypto/sha.h>
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2016-11-29 20:30:43 +07:00
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#include <crypto/authenc.h>
|
2017-06-15 14:13:43 +07:00
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#include <crypto/ctr.h>
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#include <crypto/gf128mul.h>
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2016-11-29 20:30:43 +07:00
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#include <crypto/internal/aead.h>
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#include <crypto/null.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/aead.h>
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#include <crypto/scatterwalk.h>
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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#include <crypto/internal/hash.h>
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#include "t4fw_api.h"
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#include "t4_msg.h"
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#include "chcr_core.h"
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#include "chcr_algo.h"
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#include "chcr_crypto.h"
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2017-10-08 15:07:23 +07:00
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#define IV AES_BLOCK_SIZE
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2017-11-30 18:32:08 +07:00
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static unsigned int sgl_ent_len[] = {
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0, 0, 16, 24, 40, 48, 64, 72, 88,
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96, 112, 120, 136, 144, 160, 168, 184,
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192, 208, 216, 232, 240, 256, 264, 280,
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288, 304, 312, 328, 336, 352, 360, 376
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};
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2017-11-16 18:27:08 +07:00
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2017-11-30 18:32:08 +07:00
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static unsigned int dsgl_ent_len[] = {
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0, 32, 32, 48, 48, 64, 64, 80, 80,
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112, 112, 128, 128, 144, 144, 160, 160,
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192, 192, 208, 208, 224, 224, 240, 240,
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272, 272, 288, 288, 304, 304, 320, 320
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};
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2017-11-16 18:27:08 +07:00
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static u32 round_constant[11] = {
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0x01000000, 0x02000000, 0x04000000, 0x08000000,
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0x10000000, 0x20000000, 0x40000000, 0x80000000,
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0x1B000000, 0x36000000, 0x6C000000
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};
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static int chcr_handle_cipher_resp(struct ablkcipher_request *req,
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unsigned char *input, int err);
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2016-11-29 20:30:43 +07:00
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static inline struct chcr_aead_ctx *AEAD_CTX(struct chcr_context *ctx)
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{
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return ctx->crypto_ctx->aeadctx;
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}
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|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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static inline struct ablk_ctx *ABLK_CTX(struct chcr_context *ctx)
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{
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return ctx->crypto_ctx->ablkctx;
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}
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static inline struct hmac_ctx *HMAC_CTX(struct chcr_context *ctx)
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{
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return ctx->crypto_ctx->hmacctx;
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}
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2016-11-29 20:30:43 +07:00
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static inline struct chcr_gcm_ctx *GCM_CTX(struct chcr_aead_ctx *gctx)
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{
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return gctx->ctx->gcm;
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}
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static inline struct chcr_authenc_ctx *AUTHENC_CTX(struct chcr_aead_ctx *gctx)
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{
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return gctx->ctx->authenc;
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}
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|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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static inline struct uld_ctx *ULD_CTX(struct chcr_context *ctx)
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{
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return ctx->dev->u_ctx;
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}
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static inline int is_ofld_imm(const struct sk_buff *skb)
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{
|
2017-10-08 15:07:23 +07:00
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return (skb->len <= SGE_MAX_WR_LEN);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
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}
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|
|
2017-10-08 15:07:23 +07:00
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static int sg_nents_xlen(struct scatterlist *sg, unsigned int reqlen,
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unsigned int entlen,
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unsigned int skip)
|
2017-10-08 15:07:22 +07:00
|
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{
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int nents = 0;
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unsigned int less;
|
2017-10-08 15:07:23 +07:00
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unsigned int skip_len = 0;
|
2017-10-08 15:07:22 +07:00
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2017-10-08 15:07:23 +07:00
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while (sg && skip) {
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if (sg_dma_len(sg) <= skip) {
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skip -= sg_dma_len(sg);
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skip_len = 0;
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sg = sg_next(sg);
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} else {
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skip_len = skip;
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skip = 0;
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}
|
2017-10-08 15:07:22 +07:00
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}
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|
2017-10-08 15:07:23 +07:00
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while (sg && reqlen) {
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less = min(reqlen, sg_dma_len(sg) - skip_len);
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nents += DIV_ROUND_UP(less, entlen);
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reqlen -= less;
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skip_len = 0;
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sg = sg_next(sg);
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}
|
2017-10-08 15:07:22 +07:00
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return nents;
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}
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|
2017-10-08 15:07:23 +07:00
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static inline void chcr_handle_ahash_resp(struct ahash_request *req,
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unsigned char *input,
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int err)
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{
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struct chcr_ahash_req_ctx *reqctx = ahash_request_ctx(req);
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int digestsize, updated_digestsize;
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct uld_ctx *u_ctx = ULD_CTX(h_ctx(tfm));
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if (input == NULL)
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goto out;
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digestsize = crypto_ahash_digestsize(crypto_ahash_reqtfm(req));
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if (reqctx->is_sg_map)
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chcr_hash_dma_unmap(&u_ctx->lldi.pdev->dev, req);
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if (reqctx->dma_addr)
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dma_unmap_single(&u_ctx->lldi.pdev->dev, reqctx->dma_addr,
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reqctx->dma_len, DMA_TO_DEVICE);
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reqctx->dma_addr = 0;
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updated_digestsize = digestsize;
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if (digestsize == SHA224_DIGEST_SIZE)
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updated_digestsize = SHA256_DIGEST_SIZE;
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else if (digestsize == SHA384_DIGEST_SIZE)
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updated_digestsize = SHA512_DIGEST_SIZE;
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if (reqctx->result == 1) {
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reqctx->result = 0;
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memcpy(req->result, input + sizeof(struct cpl_fw6_pld),
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digestsize);
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} else {
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memcpy(reqctx->partial_hash, input + sizeof(struct cpl_fw6_pld),
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updated_digestsize);
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}
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out:
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req->base.complete(&req->base, err);
|
2017-11-16 18:27:08 +07:00
|
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}
|
2017-10-08 15:07:23 +07:00
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|
2017-11-16 18:27:08 +07:00
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static inline int get_aead_subtype(struct crypto_aead *aead)
|
2017-10-08 15:07:23 +07:00
|
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{
|
2017-11-16 18:27:08 +07:00
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struct aead_alg *alg = crypto_aead_alg(aead);
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struct chcr_alg_template *chcr_crypto_alg =
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container_of(alg, struct chcr_alg_template, alg.aead);
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return chcr_crypto_alg->type & CRYPTO_ALG_SUB_TYPE_MASK;
|
2017-10-08 15:07:23 +07:00
|
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}
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|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_verify_tag(struct aead_request *req, u8 *input, int *err)
|
2016-11-29 20:30:43 +07:00
|
|
|
{
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|
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|
u8 temp[SHA512_DIGEST_SIZE];
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|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
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|
|
int authsize = crypto_aead_authsize(tfm);
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|
|
struct cpl_fw6_pld *fw6_pld;
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|
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int cmp = 0;
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|
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|
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fw6_pld = (struct cpl_fw6_pld *)input;
|
|
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if ((get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106) ||
|
|
|
|
(get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_GCM)) {
|
2017-06-15 14:13:42 +07:00
|
|
|
cmp = crypto_memneq(&fw6_pld->data[2], (fw6_pld + 1), authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
} else {
|
|
|
|
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src), temp,
|
|
|
|
authsize, req->assoclen +
|
|
|
|
req->cryptlen - authsize);
|
2017-06-15 14:13:42 +07:00
|
|
|
cmp = crypto_memneq(temp, (fw6_pld + 1), authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
if (cmp)
|
|
|
|
*err = -EBADMSG;
|
|
|
|
else
|
|
|
|
*err = 0;
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
static inline void chcr_handle_aead_resp(struct aead_request *req,
|
|
|
|
unsigned char *input,
|
|
|
|
int err)
|
|
|
|
{
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(a_ctx(tfm));
|
|
|
|
|
|
|
|
chcr_aead_dma_unmap(&u_ctx->lldi.pdev->dev, req, reqctx->op);
|
|
|
|
if (reqctx->b0_dma)
|
|
|
|
dma_unmap_single(&u_ctx->lldi.pdev->dev, reqctx->b0_dma,
|
|
|
|
reqctx->b0_len, DMA_BIDIRECTIONAL);
|
|
|
|
if (reqctx->verify == VERIFY_SW) {
|
|
|
|
chcr_verify_tag(req, input, &err);
|
|
|
|
reqctx->verify = VERIFY_HW;
|
|
|
|
}
|
|
|
|
req->base.complete(&req->base, err);
|
|
|
|
}
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
/*
|
|
|
|
* chcr_handle_resp - Unmap the DMA buffers associated with the request
|
|
|
|
* @req: crypto request
|
|
|
|
*/
|
|
|
|
int chcr_handle_resp(struct crypto_async_request *req, unsigned char *input,
|
2016-11-29 20:30:43 +07:00
|
|
|
int err)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
|
|
|
struct crypto_tfm *tfm = req->tfm;
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
2017-06-15 14:13:44 +07:00
|
|
|
struct adapter *adap = padap(ctx->dev);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
switch (tfm->__crt_alg->cra_flags & CRYPTO_ALG_TYPE_MASK) {
|
2016-11-29 20:30:43 +07:00
|
|
|
case CRYPTO_ALG_TYPE_AEAD:
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_handle_aead_resp(aead_request_cast(req), input, err);
|
2016-11-29 20:30:43 +07:00
|
|
|
break;
|
|
|
|
|
2017-01-27 17:39:09 +07:00
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_handle_cipher_resp(ablkcipher_request_cast(req),
|
|
|
|
input, err);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_handle_ahash_resp(ahash_request_cast(req), input, err);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.complete);
|
2016-11-29 20:30:43 +07:00
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
static void get_aes_decrypt_key(unsigned char *dec_key,
|
2016-11-29 20:30:35 +07:00
|
|
|
const unsigned char *key,
|
|
|
|
unsigned int keylength)
|
|
|
|
{
|
|
|
|
u32 temp;
|
|
|
|
u32 w_ring[MAX_NK];
|
|
|
|
int i, j, k;
|
|
|
|
u8 nr, nk;
|
|
|
|
|
|
|
|
switch (keylength) {
|
|
|
|
case AES_KEYLENGTH_128BIT:
|
|
|
|
nk = KEYLENGTH_4BYTES;
|
|
|
|
nr = NUMBER_OF_ROUNDS_10;
|
|
|
|
break;
|
|
|
|
case AES_KEYLENGTH_192BIT:
|
|
|
|
nk = KEYLENGTH_6BYTES;
|
|
|
|
nr = NUMBER_OF_ROUNDS_12;
|
|
|
|
break;
|
|
|
|
case AES_KEYLENGTH_256BIT:
|
|
|
|
nk = KEYLENGTH_8BYTES;
|
|
|
|
nr = NUMBER_OF_ROUNDS_14;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (i = 0; i < nk; i++)
|
|
|
|
w_ring[i] = be32_to_cpu(*(u32 *)&key[4 * i]);
|
|
|
|
|
|
|
|
i = 0;
|
|
|
|
temp = w_ring[nk - 1];
|
|
|
|
while (i + nk < (nr + 1) * 4) {
|
|
|
|
if (!(i % nk)) {
|
|
|
|
/* RotWord(temp) */
|
|
|
|
temp = (temp << 8) | (temp >> 24);
|
|
|
|
temp = aes_ks_subword(temp);
|
|
|
|
temp ^= round_constant[i / nk];
|
|
|
|
} else if (nk == 8 && (i % 4 == 0)) {
|
|
|
|
temp = aes_ks_subword(temp);
|
|
|
|
}
|
|
|
|
w_ring[i % nk] ^= temp;
|
|
|
|
temp = w_ring[i % nk];
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
i--;
|
|
|
|
for (k = 0, j = i % nk; k < nk; k++) {
|
|
|
|
*((u32 *)dec_key + k) = htonl(w_ring[j]);
|
|
|
|
j--;
|
|
|
|
if (j < 0)
|
|
|
|
j += nk;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
static struct crypto_shash *chcr_alloc_shash(unsigned int ds)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2017-04-14 01:25:15 +07:00
|
|
|
struct crypto_shash *base_hash = ERR_PTR(-EINVAL);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
switch (ds) {
|
|
|
|
case SHA1_DIGEST_SIZE:
|
2016-11-29 20:30:41 +07:00
|
|
|
base_hash = crypto_alloc_shash("sha1", 0, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
case SHA224_DIGEST_SIZE:
|
2016-11-29 20:30:41 +07:00
|
|
|
base_hash = crypto_alloc_shash("sha224", 0, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
case SHA256_DIGEST_SIZE:
|
2016-11-29 20:30:41 +07:00
|
|
|
base_hash = crypto_alloc_shash("sha256", 0, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
case SHA384_DIGEST_SIZE:
|
2016-11-29 20:30:41 +07:00
|
|
|
base_hash = crypto_alloc_shash("sha384", 0, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
case SHA512_DIGEST_SIZE:
|
2016-11-29 20:30:41 +07:00
|
|
|
base_hash = crypto_alloc_shash("sha512", 0, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
return base_hash;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_compute_partial_hash(struct shash_desc *desc,
|
|
|
|
char *iopad, char *result_hash,
|
|
|
|
int digest_size)
|
|
|
|
{
|
|
|
|
struct sha1_state sha1_st;
|
|
|
|
struct sha256_state sha256_st;
|
|
|
|
struct sha512_state sha512_st;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
if (digest_size == SHA1_DIGEST_SIZE) {
|
|
|
|
error = crypto_shash_init(desc) ?:
|
|
|
|
crypto_shash_update(desc, iopad, SHA1_BLOCK_SIZE) ?:
|
|
|
|
crypto_shash_export(desc, (void *)&sha1_st);
|
|
|
|
memcpy(result_hash, sha1_st.state, SHA1_DIGEST_SIZE);
|
|
|
|
} else if (digest_size == SHA224_DIGEST_SIZE) {
|
|
|
|
error = crypto_shash_init(desc) ?:
|
|
|
|
crypto_shash_update(desc, iopad, SHA256_BLOCK_SIZE) ?:
|
|
|
|
crypto_shash_export(desc, (void *)&sha256_st);
|
|
|
|
memcpy(result_hash, sha256_st.state, SHA256_DIGEST_SIZE);
|
|
|
|
|
|
|
|
} else if (digest_size == SHA256_DIGEST_SIZE) {
|
|
|
|
error = crypto_shash_init(desc) ?:
|
|
|
|
crypto_shash_update(desc, iopad, SHA256_BLOCK_SIZE) ?:
|
|
|
|
crypto_shash_export(desc, (void *)&sha256_st);
|
|
|
|
memcpy(result_hash, sha256_st.state, SHA256_DIGEST_SIZE);
|
|
|
|
|
|
|
|
} else if (digest_size == SHA384_DIGEST_SIZE) {
|
|
|
|
error = crypto_shash_init(desc) ?:
|
|
|
|
crypto_shash_update(desc, iopad, SHA512_BLOCK_SIZE) ?:
|
|
|
|
crypto_shash_export(desc, (void *)&sha512_st);
|
|
|
|
memcpy(result_hash, sha512_st.state, SHA512_DIGEST_SIZE);
|
|
|
|
|
|
|
|
} else if (digest_size == SHA512_DIGEST_SIZE) {
|
|
|
|
error = crypto_shash_init(desc) ?:
|
|
|
|
crypto_shash_update(desc, iopad, SHA512_BLOCK_SIZE) ?:
|
|
|
|
crypto_shash_export(desc, (void *)&sha512_st);
|
|
|
|
memcpy(result_hash, sha512_st.state, SHA512_DIGEST_SIZE);
|
|
|
|
} else {
|
|
|
|
error = -EINVAL;
|
|
|
|
pr_err("Unknown digest size %d\n", digest_size);
|
|
|
|
}
|
|
|
|
return error;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void chcr_change_order(char *buf, int ds)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (ds == SHA512_DIGEST_SIZE) {
|
|
|
|
for (i = 0; i < (ds / sizeof(u64)); i++)
|
|
|
|
*((__be64 *)buf + i) =
|
|
|
|
cpu_to_be64(*((u64 *)buf + i));
|
|
|
|
} else {
|
|
|
|
for (i = 0; i < (ds / sizeof(u32)); i++)
|
|
|
|
*((__be32 *)buf + i) =
|
|
|
|
cpu_to_be32(*((u32 *)buf + i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int is_hmac(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
|
|
|
struct chcr_alg_template *chcr_crypto_alg =
|
|
|
|
container_of(__crypto_ahash_alg(alg), struct chcr_alg_template,
|
|
|
|
alg.hash);
|
2016-11-29 20:30:42 +07:00
|
|
|
if (chcr_crypto_alg->type == CRYPTO_ALG_TYPE_HMAC)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
static inline void dsgl_walk_init(struct dsgl_walk *walk,
|
|
|
|
struct cpl_rx_phys_dsgl *dsgl)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
walk->dsgl = dsgl;
|
|
|
|
walk->nents = 0;
|
|
|
|
walk->to = (struct phys_sge_pairs *)(dsgl + 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dsgl_walk_end(struct dsgl_walk *walk, unsigned short qid)
|
|
|
|
{
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl;
|
|
|
|
|
|
|
|
phys_cpl = walk->dsgl;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
phys_cpl->op_to_tid = htonl(CPL_RX_PHYS_DSGL_OPCODE_V(CPL_RX_PHYS_DSGL)
|
|
|
|
| CPL_RX_PHYS_DSGL_ISRDMA_V(0));
|
2017-10-08 15:07:23 +07:00
|
|
|
phys_cpl->pcirlxorder_to_noofsgentr =
|
|
|
|
htonl(CPL_RX_PHYS_DSGL_PCIRLXORDER_V(0) |
|
|
|
|
CPL_RX_PHYS_DSGL_PCINOSNOOP_V(0) |
|
|
|
|
CPL_RX_PHYS_DSGL_PCITPHNTENB_V(0) |
|
|
|
|
CPL_RX_PHYS_DSGL_PCITPHNT_V(0) |
|
|
|
|
CPL_RX_PHYS_DSGL_DCAID_V(0) |
|
|
|
|
CPL_RX_PHYS_DSGL_NOOFSGENTR_V(walk->nents));
|
|
|
|
phys_cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR;
|
|
|
|
phys_cpl->rss_hdr_int.qid = htons(qid);
|
|
|
|
phys_cpl->rss_hdr_int.hash_val = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dsgl_walk_add_page(struct dsgl_walk *walk,
|
|
|
|
size_t size,
|
|
|
|
dma_addr_t *addr)
|
|
|
|
{
|
|
|
|
int j;
|
|
|
|
|
|
|
|
if (!size)
|
|
|
|
return;
|
|
|
|
j = walk->nents;
|
|
|
|
walk->to->len[j % 8] = htons(size);
|
|
|
|
walk->to->addr[j % 8] = cpu_to_be64(*addr);
|
|
|
|
j++;
|
|
|
|
if ((j % 8) == 0)
|
|
|
|
walk->to++;
|
|
|
|
walk->nents = j;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dsgl_walk_add_sg(struct dsgl_walk *walk,
|
|
|
|
struct scatterlist *sg,
|
|
|
|
unsigned int slen,
|
|
|
|
unsigned int skip)
|
|
|
|
{
|
|
|
|
int skip_len = 0;
|
|
|
|
unsigned int left_size = slen, len = 0;
|
|
|
|
unsigned int j = walk->nents;
|
|
|
|
int offset, ent_len;
|
|
|
|
|
|
|
|
if (!slen)
|
|
|
|
return;
|
|
|
|
while (sg && skip) {
|
|
|
|
if (sg_dma_len(sg) <= skip) {
|
|
|
|
skip -= sg_dma_len(sg);
|
|
|
|
skip_len = 0;
|
|
|
|
sg = sg_next(sg);
|
|
|
|
} else {
|
|
|
|
skip_len = skip;
|
|
|
|
skip = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:22 +07:00
|
|
|
while (left_size && sg) {
|
2017-10-08 15:07:23 +07:00
|
|
|
len = min_t(u32, left_size, sg_dma_len(sg) - skip_len);
|
2017-10-08 15:07:22 +07:00
|
|
|
offset = 0;
|
|
|
|
while (len) {
|
2017-10-08 15:07:23 +07:00
|
|
|
ent_len = min_t(u32, len, CHCR_DST_SG_SIZE);
|
|
|
|
walk->to->len[j % 8] = htons(ent_len);
|
|
|
|
walk->to->addr[j % 8] = cpu_to_be64(sg_dma_address(sg) +
|
|
|
|
offset + skip_len);
|
2017-10-08 15:07:22 +07:00
|
|
|
offset += ent_len;
|
|
|
|
len -= ent_len;
|
|
|
|
j++;
|
|
|
|
if ((j % 8) == 0)
|
2017-10-08 15:07:23 +07:00
|
|
|
walk->to++;
|
2017-10-08 15:07:22 +07:00
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
walk->last_sg = sg;
|
|
|
|
walk->last_sg_len = min_t(u32, left_size, sg_dma_len(sg) -
|
|
|
|
skip_len) + skip_len;
|
|
|
|
left_size -= min_t(u32, left_size, sg_dma_len(sg) - skip_len);
|
|
|
|
skip_len = 0;
|
2017-10-08 15:07:22 +07:00
|
|
|
sg = sg_next(sg);
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
walk->nents = j;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void ulptx_walk_init(struct ulptx_walk *walk,
|
|
|
|
struct ulptx_sgl *ulp)
|
|
|
|
{
|
|
|
|
walk->sgl = ulp;
|
|
|
|
walk->nents = 0;
|
|
|
|
walk->pair_idx = 0;
|
|
|
|
walk->pair = ulp->sge;
|
|
|
|
walk->last_sg = NULL;
|
|
|
|
walk->last_sg_len = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void ulptx_walk_end(struct ulptx_walk *walk)
|
|
|
|
{
|
|
|
|
walk->sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
|
|
|
|
ULPTX_NSGE_V(walk->nents));
|
|
|
|
}
|
2017-10-08 15:07:22 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
|
|
|
|
static inline void ulptx_walk_add_page(struct ulptx_walk *walk,
|
|
|
|
size_t size,
|
|
|
|
dma_addr_t *addr)
|
|
|
|
{
|
|
|
|
if (!size)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (walk->nents == 0) {
|
|
|
|
walk->sgl->len0 = cpu_to_be32(size);
|
|
|
|
walk->sgl->addr0 = cpu_to_be64(*addr);
|
|
|
|
} else {
|
|
|
|
walk->pair->addr[walk->pair_idx] = cpu_to_be64(*addr);
|
|
|
|
walk->pair->len[walk->pair_idx] = cpu_to_be32(size);
|
|
|
|
walk->pair_idx = !walk->pair_idx;
|
|
|
|
if (!walk->pair_idx)
|
|
|
|
walk->pair++;
|
|
|
|
}
|
|
|
|
walk->nents++;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
static void ulptx_walk_add_sg(struct ulptx_walk *walk,
|
2016-11-29 20:30:40 +07:00
|
|
|
struct scatterlist *sg,
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int len,
|
|
|
|
unsigned int skip)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
int small;
|
|
|
|
int skip_len = 0;
|
|
|
|
unsigned int sgmin;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
if (!len)
|
|
|
|
return;
|
|
|
|
|
|
|
|
while (sg && skip) {
|
|
|
|
if (sg_dma_len(sg) <= skip) {
|
|
|
|
skip -= sg_dma_len(sg);
|
|
|
|
skip_len = 0;
|
|
|
|
sg = sg_next(sg);
|
|
|
|
} else {
|
|
|
|
skip_len = skip;
|
|
|
|
skip = 0;
|
|
|
|
}
|
|
|
|
}
|
2018-01-11 18:15:49 +07:00
|
|
|
WARN(!sg, "SG should not be null here\n");
|
|
|
|
if (sg && (walk->nents == 0)) {
|
2017-10-08 15:07:23 +07:00
|
|
|
small = min_t(unsigned int, sg_dma_len(sg) - skip_len, len);
|
|
|
|
sgmin = min_t(unsigned int, small, CHCR_SRC_SG_SIZE);
|
|
|
|
walk->sgl->len0 = cpu_to_be32(sgmin);
|
|
|
|
walk->sgl->addr0 = cpu_to_be64(sg_dma_address(sg) + skip_len);
|
|
|
|
walk->nents++;
|
|
|
|
len -= sgmin;
|
|
|
|
walk->last_sg = sg;
|
|
|
|
walk->last_sg_len = sgmin + skip_len;
|
|
|
|
skip_len += sgmin;
|
|
|
|
if (sg_dma_len(sg) == skip_len) {
|
|
|
|
sg = sg_next(sg);
|
|
|
|
skip_len = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
while (sg && len) {
|
|
|
|
small = min(sg_dma_len(sg) - skip_len, len);
|
|
|
|
sgmin = min_t(unsigned int, small, CHCR_SRC_SG_SIZE);
|
|
|
|
walk->pair->len[walk->pair_idx] = cpu_to_be32(sgmin);
|
|
|
|
walk->pair->addr[walk->pair_idx] =
|
|
|
|
cpu_to_be64(sg_dma_address(sg) + skip_len);
|
|
|
|
walk->pair_idx = !walk->pair_idx;
|
|
|
|
walk->nents++;
|
|
|
|
if (!walk->pair_idx)
|
|
|
|
walk->pair++;
|
|
|
|
len -= sgmin;
|
|
|
|
skip_len += sgmin;
|
|
|
|
walk->last_sg = sg;
|
|
|
|
walk->last_sg_len = skip_len;
|
|
|
|
if (sg_dma_len(sg) == skip_len) {
|
|
|
|
sg = sg_next(sg);
|
|
|
|
skip_len = 0;
|
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int get_cryptoalg_subtype(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
|
|
|
struct chcr_alg_template *chcr_crypto_alg =
|
|
|
|
container_of(alg, struct chcr_alg_template, alg.crypto);
|
|
|
|
|
|
|
|
return chcr_crypto_alg->type & CRYPTO_ALG_SUB_TYPE_MASK;
|
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
static int cxgb4_is_crypto_q_full(struct net_device *dev, unsigned int idx)
|
|
|
|
{
|
|
|
|
struct adapter *adap = netdev2adap(dev);
|
|
|
|
struct sge_uld_txq_info *txq_info =
|
|
|
|
adap->sge.uld_txq_info[CXGB4_TX_CRYPTO];
|
|
|
|
struct sge_uld_txq *txq;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
local_bh_disable();
|
|
|
|
txq = &txq_info->uldtxq[idx];
|
|
|
|
spin_lock(&txq->sendq.lock);
|
|
|
|
if (txq->full)
|
|
|
|
ret = -1;
|
|
|
|
spin_unlock(&txq->sendq.lock);
|
|
|
|
local_bh_enable();
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
static int generate_copy_rrkey(struct ablk_ctx *ablkctx,
|
|
|
|
struct _key_ctx *key_ctx)
|
|
|
|
{
|
|
|
|
if (ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CBC) {
|
2016-11-29 20:30:39 +07:00
|
|
|
memcpy(key_ctx->key, ablkctx->rrkey, ablkctx->enckey_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
} else {
|
|
|
|
memcpy(key_ctx->key,
|
|
|
|
ablkctx->key + (ablkctx->enckey_len >> 1),
|
|
|
|
ablkctx->enckey_len >> 1);
|
2016-11-29 20:30:39 +07:00
|
|
|
memcpy(key_ctx->key + (ablkctx->enckey_len >> 1),
|
|
|
|
ablkctx->rrkey, ablkctx->enckey_len >> 1);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
2017-06-15 14:13:43 +07:00
|
|
|
static int chcr_sg_ent_in_wr(struct scatterlist *src,
|
|
|
|
struct scatterlist *dst,
|
|
|
|
unsigned int minsg,
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int space,
|
|
|
|
unsigned int srcskip,
|
|
|
|
unsigned int dstskip)
|
2017-06-15 14:13:43 +07:00
|
|
|
{
|
|
|
|
int srclen = 0, dstlen = 0;
|
2017-10-08 15:07:23 +07:00
|
|
|
int srcsg = minsg, dstsg = minsg;
|
2017-10-08 15:07:22 +07:00
|
|
|
int offset = 0, less;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
if (sg_dma_len(src) == srcskip) {
|
|
|
|
src = sg_next(src);
|
|
|
|
srcskip = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sg_dma_len(dst) == dstskip) {
|
|
|
|
dst = sg_next(dst);
|
|
|
|
dstskip = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (src && dst &&
|
2017-06-15 14:13:43 +07:00
|
|
|
space > (sgl_ent_len[srcsg + 1] + dsgl_ent_len[dstsg])) {
|
2017-10-08 15:07:23 +07:00
|
|
|
srclen += (sg_dma_len(src) - srcskip);
|
2017-06-15 14:13:43 +07:00
|
|
|
srcsg++;
|
2017-10-08 15:07:22 +07:00
|
|
|
offset = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
while (dst && ((dstsg + 1) <= MAX_DSGL_ENT) &&
|
|
|
|
space > (sgl_ent_len[srcsg] + dsgl_ent_len[dstsg + 1])) {
|
|
|
|
if (srclen <= dstlen)
|
|
|
|
break;
|
2017-10-08 15:07:23 +07:00
|
|
|
less = min_t(unsigned int, sg_dma_len(dst) - offset -
|
2018-01-11 18:15:48 +07:00
|
|
|
dstskip, CHCR_DST_SG_SIZE);
|
2017-10-08 15:07:22 +07:00
|
|
|
dstlen += less;
|
|
|
|
offset += less;
|
2017-10-08 15:07:23 +07:00
|
|
|
if (offset == sg_dma_len(dst)) {
|
2017-10-08 15:07:22 +07:00
|
|
|
dst = sg_next(dst);
|
|
|
|
offset = 0;
|
|
|
|
}
|
2017-06-15 14:13:43 +07:00
|
|
|
dstsg++;
|
2017-10-08 15:07:23 +07:00
|
|
|
dstskip = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
src = sg_next(src);
|
2018-01-11 18:15:48 +07:00
|
|
|
srcskip = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
return min(srclen, dstlen);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_cipher_fallback(struct crypto_skcipher *cipher,
|
|
|
|
u32 flags,
|
|
|
|
struct scatterlist *src,
|
|
|
|
struct scatterlist *dst,
|
|
|
|
unsigned int nbytes,
|
|
|
|
u8 *iv,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
SKCIPHER_REQUEST_ON_STACK(subreq, cipher);
|
|
|
|
skcipher_request_set_tfm(subreq, cipher);
|
|
|
|
skcipher_request_set_callback(subreq, flags, NULL, NULL);
|
|
|
|
skcipher_request_set_crypt(subreq, src, dst,
|
|
|
|
nbytes, iv);
|
|
|
|
|
|
|
|
err = op_type ? crypto_skcipher_decrypt(subreq) :
|
|
|
|
crypto_skcipher_encrypt(subreq);
|
|
|
|
skcipher_request_zero(subreq);
|
|
|
|
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
static inline void create_wreq(struct chcr_context *ctx,
|
2016-11-29 20:30:36 +07:00
|
|
|
struct chcr_wr *chcr_req,
|
2017-10-08 15:07:23 +07:00
|
|
|
struct crypto_async_request *req,
|
|
|
|
unsigned int imm,
|
2017-10-08 15:07:18 +07:00
|
|
|
int hash_sz,
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int len16,
|
2017-06-15 14:13:39 +07:00
|
|
|
unsigned int sc_len,
|
|
|
|
unsigned int lcb)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(ctx);
|
2017-04-10 19:54:00 +07:00
|
|
|
int qid = u_ctx->lldi.rxq_ids[ctx->rx_qidx];
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
|
2017-10-08 15:07:18 +07:00
|
|
|
chcr_req->wreq.op_to_cctx_size = FILL_WR_OP_CCTX_SIZE;
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->wreq.pld_size_hash_size =
|
2017-10-08 15:07:18 +07:00
|
|
|
htonl(FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(hash_sz));
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->wreq.len16_pkd =
|
2017-10-08 15:07:23 +07:00
|
|
|
htonl(FW_CRYPTO_LOOKASIDE_WR_LEN16_V(DIV_ROUND_UP(len16, 16)));
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->wreq.cookie = cpu_to_be64((uintptr_t)req);
|
|
|
|
chcr_req->wreq.rx_chid_to_rx_q_id =
|
2017-01-27 17:39:05 +07:00
|
|
|
FILL_WR_RX_Q_ID(ctx->dev->rx_channel_id, qid,
|
2017-10-08 15:07:18 +07:00
|
|
|
!!lcb, ctx->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-01-27 17:39:05 +07:00
|
|
|
chcr_req->ulptx.cmd_dest = FILL_ULPTX_CMD_DEST(ctx->dev->tx_channel_id,
|
|
|
|
qid);
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_req->ulptx.len = htonl((DIV_ROUND_UP(len16, 16) -
|
|
|
|
((sizeof(chcr_req->wreq)) >> 4)));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_req->sc_imm.cmd_more = FILL_CMD_MORE(!imm);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sc_imm.len = cpu_to_be32(sizeof(struct cpl_tx_sec_pdu) +
|
2017-10-08 15:07:23 +07:00
|
|
|
sizeof(chcr_req->key_ctx) + sc_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* create_cipher_wr - form the WR for cipher operations
|
|
|
|
* @req: cipher req.
|
|
|
|
* @ctx: crypto driver context of the request.
|
|
|
|
* @qid: ingress qid where response of this WR should be received.
|
|
|
|
* @op_type: encryption or decryption
|
|
|
|
*/
|
2017-06-15 14:13:43 +07:00
|
|
|
static struct sk_buff *create_cipher_wr(struct cipher_wr_param *wrparam)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2017-06-15 14:13:43 +07:00
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(wrparam->req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(tfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
struct sk_buff *skb = NULL;
|
2016-11-29 20:30:36 +07:00
|
|
|
struct chcr_wr *chcr_req;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ulptx_sgl *ulptx;
|
2017-06-15 14:13:43 +07:00
|
|
|
struct chcr_blkcipher_req_ctx *reqctx =
|
|
|
|
ablkcipher_request_ctx(wrparam->req);
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int temp = 0, transhdr_len, dst_size;
|
2017-06-15 14:13:43 +07:00
|
|
|
int error;
|
2017-10-08 15:07:22 +07:00
|
|
|
int nents;
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int kctx_len;
|
2017-06-15 14:13:43 +07:00
|
|
|
gfp_t flags = wrparam->req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
|
|
|
|
GFP_KERNEL : GFP_ATOMIC;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct adapter *adap = padap(c_ctx(tfm)->dev);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
nents = sg_nents_xlen(reqctx->dstsg, wrparam->bytes, CHCR_DST_SG_SIZE,
|
|
|
|
reqctx->dst_ofst);
|
|
|
|
dst_size = get_space_for_phys_dsgl(nents + 1);
|
2016-11-29 20:30:36 +07:00
|
|
|
kctx_len = (DIV_ROUND_UP(ablkctx->enckey_len, 16) * 16);
|
2017-10-08 15:07:23 +07:00
|
|
|
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dst_size);
|
|
|
|
nents = sg_nents_xlen(reqctx->srcsg, wrparam->bytes,
|
|
|
|
CHCR_SRC_SG_SIZE, reqctx->src_ofst);
|
|
|
|
temp = reqctx->imm ? (DIV_ROUND_UP((IV + wrparam->req->nbytes), 16)
|
|
|
|
* 16) : (sgl_len(nents + MIN_CIPHER_SG) * 8);
|
|
|
|
transhdr_len += temp;
|
|
|
|
transhdr_len = DIV_ROUND_UP(transhdr_len, 16) * 16;
|
|
|
|
skb = alloc_skb(SGE_MAX_WR_LEN, flags);
|
2017-06-15 14:13:43 +07:00
|
|
|
if (!skb) {
|
|
|
|
error = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
net: introduce __skb_put_[zero, data, u8]
follow Johannes Berg, semantic patch file as below,
@@
identifier p, p2;
expression len;
expression skb;
type t, t2;
@@
(
-p = __skb_put(skb, len);
+p = __skb_put_zero(skb, len);
|
-p = (t)__skb_put(skb, len);
+p = __skb_put_zero(skb, len);
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, len);
|
-memset(p, 0, len);
)
@@
identifier p;
expression len;
expression skb;
type t;
@@
(
-t p = __skb_put(skb, len);
+t p = __skb_put_zero(skb, len);
)
... when != p
(
-memset(p, 0, len);
)
@@
type t, t2;
identifier p, p2;
expression skb;
@@
t *p;
...
(
-p = __skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
|
-p = (t *)__skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, sizeof(*p));
|
-memset(p, 0, sizeof(*p));
)
@@
expression skb, len;
@@
-memset(__skb_put(skb, len), 0, len);
+__skb_put_zero(skb, len);
@@
expression skb, len, data;
@@
-memcpy(__skb_put(skb, len), data, len);
+__skb_put_data(skb, data, len);
@@
expression SKB, C, S;
typedef u8;
identifier fn = {__skb_put};
fresh identifier fn2 = fn ## "_u8";
@@
- *(u8 *)fn(SKB, S) = C;
+ fn2(SKB, C);
Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18 21:48:17 +07:00
|
|
|
chcr_req = __skb_put_zero(skb, transhdr_len);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.op_ivinsrtofst =
|
2017-10-08 15:07:23 +07:00
|
|
|
FILL_SEC_CPL_OP_IVINSR(c_ctx(tfm)->dev->rx_channel_id, 2, 1);
|
2016-11-29 20:30:36 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_req->sec_cpl.pldlen = htonl(IV + wrparam->bytes);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.aadstart_cipherstop_hi =
|
2017-10-08 15:07:23 +07:00
|
|
|
FILL_SEC_CPL_CIPHERSTOP_HI(0, 0, IV + 1, 0);
|
2016-11-29 20:30:36 +07:00
|
|
|
|
|
|
|
chcr_req->sec_cpl.cipherstop_lo_authinsert =
|
|
|
|
FILL_SEC_CPL_AUTHINSERT(0, 0, 0, 0);
|
2017-06-15 14:13:43 +07:00
|
|
|
chcr_req->sec_cpl.seqno_numivs = FILL_SEC_CPL_SCMD0_SEQNO(reqctx->op, 0,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
ablkctx->ciph_mode,
|
2017-10-08 15:07:23 +07:00
|
|
|
0, 0, IV >> 1);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 0,
|
2017-10-08 15:07:23 +07:00
|
|
|
0, 0, dst_size);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->key_ctx.ctx_hdr = ablkctx->key_ctx_hdr;
|
2017-06-15 14:13:43 +07:00
|
|
|
if ((reqctx->op == CHCR_DECRYPT_OP) &&
|
|
|
|
(!(get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
|
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR)) &&
|
|
|
|
(!(get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
|
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR_RFC3686))) {
|
2016-11-29 20:30:36 +07:00
|
|
|
generate_copy_rrkey(ablkctx, &chcr_req->key_ctx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
} else {
|
2017-06-15 14:13:43 +07:00
|
|
|
if ((ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CBC) ||
|
|
|
|
(ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CTR)) {
|
2016-11-29 20:30:36 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key, ablkctx->key,
|
|
|
|
ablkctx->enckey_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
} else {
|
2016-11-29 20:30:36 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key, ablkctx->key +
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
(ablkctx->enckey_len >> 1),
|
|
|
|
ablkctx->enckey_len >> 1);
|
2016-11-29 20:30:36 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key +
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
(ablkctx->enckey_len >> 1),
|
|
|
|
ablkctx->key,
|
|
|
|
ablkctx->enckey_len >> 1);
|
|
|
|
}
|
|
|
|
}
|
2016-11-29 20:30:36 +07:00
|
|
|
phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)(chcr_req + 1) + kctx_len);
|
2017-10-08 15:07:23 +07:00
|
|
|
ulptx = (struct ulptx_sgl *)((u8 *)(phys_cpl + 1) + dst_size);
|
|
|
|
chcr_add_cipher_src_ent(wrparam->req, ulptx, wrparam);
|
|
|
|
chcr_add_cipher_dst_ent(wrparam->req, phys_cpl, wrparam, wrparam->qid);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.cipher_rqst);
|
2017-10-08 15:07:23 +07:00
|
|
|
temp = sizeof(struct cpl_rx_phys_dsgl) + dst_size + kctx_len
|
|
|
|
+(reqctx->imm ? (IV + wrparam->bytes) : 0);
|
|
|
|
create_wreq(c_ctx(tfm), chcr_req, &(wrparam->req->base), reqctx->imm, 0,
|
|
|
|
transhdr_len, temp,
|
2017-06-15 14:13:39 +07:00
|
|
|
ablkctx->ciph_mode == CHCR_SCMD_CIPHER_MODE_AES_CBC);
|
2016-11-29 20:30:42 +07:00
|
|
|
reqctx->skb = skb;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
return skb;
|
2017-06-15 14:13:43 +07:00
|
|
|
err:
|
|
|
|
return ERR_PTR(error);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int chcr_keyctx_ck_size(unsigned int keylen)
|
|
|
|
{
|
|
|
|
int ck_size = 0;
|
|
|
|
|
|
|
|
if (keylen == AES_KEYSIZE_128)
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
else if (keylen == AES_KEYSIZE_192)
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
|
|
|
|
else if (keylen == AES_KEYSIZE_256)
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
|
|
|
|
else
|
|
|
|
ck_size = 0;
|
|
|
|
|
|
|
|
return ck_size;
|
|
|
|
}
|
|
|
|
static int chcr_cipher_fallback_setkey(struct crypto_ablkcipher *cipher,
|
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
|
|
|
struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(cipher));
|
2017-06-15 14:13:43 +07:00
|
|
|
int err = 0;
|
|
|
|
|
|
|
|
crypto_skcipher_clear_flags(ablkctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_skcipher_set_flags(ablkctx->sw_cipher, cipher->base.crt_flags &
|
|
|
|
CRYPTO_TFM_REQ_MASK);
|
|
|
|
err = crypto_skcipher_setkey(ablkctx->sw_cipher, key, keylen);
|
|
|
|
tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
|
|
|
|
tfm->crt_flags |=
|
|
|
|
crypto_skcipher_get_flags(ablkctx->sw_cipher) &
|
|
|
|
CRYPTO_TFM_RES_MASK;
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
static int chcr_aes_cbc_setkey(struct crypto_ablkcipher *cipher,
|
|
|
|
const u8 *key,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(cipher));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int ck_size, context_size;
|
|
|
|
u16 alignment = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
int err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_cipher_fallback_setkey(cipher, key, keylen);
|
|
|
|
if (err)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
goto badkey_err;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
ck_size = chcr_keyctx_ck_size(keylen);
|
|
|
|
alignment = ck_size == CHCR_KEYCTX_CIPHER_KEY_SIZE_192 ? 8 : 0;
|
2016-11-29 20:30:39 +07:00
|
|
|
memcpy(ablkctx->key, key, keylen);
|
|
|
|
ablkctx->enckey_len = keylen;
|
|
|
|
get_aes_decrypt_key(ablkctx->rrkey, ablkctx->key, keylen << 3);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD +
|
|
|
|
keylen + alignment) >> 4;
|
|
|
|
|
|
|
|
ablkctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, CHCR_KEYCTX_NO_KEY,
|
|
|
|
0, 0, context_size);
|
|
|
|
ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC;
|
|
|
|
return 0;
|
|
|
|
badkey_err:
|
2017-06-15 14:13:43 +07:00
|
|
|
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
ablkctx->enckey_len = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
static int chcr_aes_ctr_setkey(struct crypto_ablkcipher *cipher,
|
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(cipher));
|
2017-06-15 14:13:43 +07:00
|
|
|
unsigned int ck_size, context_size;
|
|
|
|
u16 alignment = 0;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
err = chcr_cipher_fallback_setkey(cipher, key, keylen);
|
|
|
|
if (err)
|
|
|
|
goto badkey_err;
|
|
|
|
ck_size = chcr_keyctx_ck_size(keylen);
|
|
|
|
alignment = (ck_size == CHCR_KEYCTX_CIPHER_KEY_SIZE_192) ? 8 : 0;
|
|
|
|
memcpy(ablkctx->key, key, keylen);
|
|
|
|
ablkctx->enckey_len = keylen;
|
|
|
|
context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD +
|
|
|
|
keylen + alignment) >> 4;
|
|
|
|
|
|
|
|
ablkctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, CHCR_KEYCTX_NO_KEY,
|
|
|
|
0, 0, context_size);
|
|
|
|
ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
badkey_err:
|
|
|
|
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
ablkctx->enckey_len = 0;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_aes_rfc3686_setkey(struct crypto_ablkcipher *cipher,
|
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(cipher));
|
2017-06-15 14:13:43 +07:00
|
|
|
unsigned int ck_size, context_size;
|
|
|
|
u16 alignment = 0;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (keylen < CTR_RFC3686_NONCE_SIZE)
|
|
|
|
return -EINVAL;
|
|
|
|
memcpy(ablkctx->nonce, key + (keylen - CTR_RFC3686_NONCE_SIZE),
|
|
|
|
CTR_RFC3686_NONCE_SIZE);
|
|
|
|
|
|
|
|
keylen -= CTR_RFC3686_NONCE_SIZE;
|
|
|
|
err = chcr_cipher_fallback_setkey(cipher, key, keylen);
|
|
|
|
if (err)
|
|
|
|
goto badkey_err;
|
|
|
|
|
|
|
|
ck_size = chcr_keyctx_ck_size(keylen);
|
|
|
|
alignment = (ck_size == CHCR_KEYCTX_CIPHER_KEY_SIZE_192) ? 8 : 0;
|
|
|
|
memcpy(ablkctx->key, key, keylen);
|
|
|
|
ablkctx->enckey_len = keylen;
|
|
|
|
context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD +
|
|
|
|
keylen + alignment) >> 4;
|
|
|
|
|
|
|
|
ablkctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, CHCR_KEYCTX_NO_KEY,
|
|
|
|
0, 0, context_size);
|
|
|
|
ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
badkey_err:
|
|
|
|
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
ablkctx->enckey_len = 0;
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
static void ctr_add_iv(u8 *dstiv, u8 *srciv, u32 add)
|
|
|
|
{
|
|
|
|
unsigned int size = AES_BLOCK_SIZE;
|
|
|
|
__be32 *b = (__be32 *)(dstiv + size);
|
|
|
|
u32 c, prev;
|
|
|
|
|
|
|
|
memcpy(dstiv, srciv, AES_BLOCK_SIZE);
|
|
|
|
for (; size >= 4; size -= 4) {
|
|
|
|
prev = be32_to_cpu(*--b);
|
|
|
|
c = prev + add;
|
|
|
|
*b = cpu_to_be32(c);
|
|
|
|
if (prev < c)
|
|
|
|
break;
|
|
|
|
add = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned int adjust_ctr_overflow(u8 *iv, u32 bytes)
|
|
|
|
{
|
|
|
|
__be32 *b = (__be32 *)(iv + AES_BLOCK_SIZE);
|
|
|
|
u64 c;
|
|
|
|
u32 temp = be32_to_cpu(*--b);
|
|
|
|
|
|
|
|
temp = ~temp;
|
|
|
|
c = (u64)temp + 1; // No of block can processed withou overflow
|
|
|
|
if ((bytes / AES_BLOCK_SIZE) > c)
|
|
|
|
bytes = c * AES_BLOCK_SIZE;
|
|
|
|
return bytes;
|
|
|
|
}
|
|
|
|
|
2018-01-11 18:15:50 +07:00
|
|
|
static int chcr_update_tweak(struct ablkcipher_request *req, u8 *iv,
|
|
|
|
u32 isfinal)
|
2017-06-15 14:13:43 +07:00
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(tfm));
|
2017-06-15 14:13:43 +07:00
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
struct crypto_cipher *cipher;
|
|
|
|
int ret, i;
|
|
|
|
u8 *key;
|
|
|
|
unsigned int keylen;
|
2017-10-08 15:07:21 +07:00
|
|
|
int round = reqctx->last_req_len / AES_BLOCK_SIZE;
|
|
|
|
int round8 = round / 8;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
2017-06-23 21:15:11 +07:00
|
|
|
cipher = ablkctx->aes_generic;
|
2017-10-08 15:07:21 +07:00
|
|
|
memcpy(iv, reqctx->iv, AES_BLOCK_SIZE);
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
keylen = ablkctx->enckey_len / 2;
|
|
|
|
key = ablkctx->key + keylen;
|
|
|
|
ret = crypto_cipher_setkey(cipher, key, keylen);
|
|
|
|
if (ret)
|
2017-06-23 21:15:11 +07:00
|
|
|
goto out;
|
2017-10-08 15:07:23 +07:00
|
|
|
/*H/W sends the encrypted IV in dsgl when AADIVDROP bit is 0*/
|
2017-10-08 15:07:21 +07:00
|
|
|
for (i = 0; i < round8; i++)
|
|
|
|
gf128mul_x8_ble((le128 *)iv, (le128 *)iv);
|
|
|
|
|
|
|
|
for (i = 0; i < (round % 8); i++)
|
2017-06-15 14:13:43 +07:00
|
|
|
gf128mul_x_ble((le128 *)iv, (le128 *)iv);
|
|
|
|
|
2018-01-11 18:15:50 +07:00
|
|
|
if (!isfinal)
|
|
|
|
crypto_cipher_decrypt_one(cipher, iv, iv);
|
2017-06-15 14:13:43 +07:00
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_update_cipher_iv(struct ablkcipher_request *req,
|
|
|
|
struct cpl_fw6_pld *fw6_pld, u8 *iv)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
int subtype = get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm));
|
2016-11-18 18:07:40 +07:00
|
|
|
int ret = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR)
|
|
|
|
ctr_add_iv(iv, req->info, (reqctx->processed /
|
|
|
|
AES_BLOCK_SIZE));
|
|
|
|
else if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_RFC3686)
|
|
|
|
*(__be32 *)(reqctx->iv + CTR_RFC3686_NONCE_SIZE +
|
|
|
|
CTR_RFC3686_IV_SIZE) = cpu_to_be32((reqctx->processed /
|
|
|
|
AES_BLOCK_SIZE) + 1);
|
|
|
|
else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS)
|
2018-01-11 18:15:50 +07:00
|
|
|
ret = chcr_update_tweak(req, iv, 0);
|
2017-06-15 14:13:43 +07:00
|
|
|
else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) {
|
|
|
|
if (reqctx->op)
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src), iv,
|
|
|
|
16,
|
|
|
|
reqctx->processed - AES_BLOCK_SIZE);
|
|
|
|
else
|
|
|
|
memcpy(iv, &fw6_pld->data[2], AES_BLOCK_SIZE);
|
|
|
|
}
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
return ret;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
/* We need separate function for final iv because in rfc3686 Initial counter
|
|
|
|
* starts from 1 and buffer size of iv is 8 byte only which remains constant
|
|
|
|
* for subsequent update requests
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int chcr_final_cipher_iv(struct ablkcipher_request *req,
|
|
|
|
struct cpl_fw6_pld *fw6_pld, u8 *iv)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
int subtype = get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm));
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR)
|
|
|
|
ctr_add_iv(iv, req->info, (reqctx->processed /
|
|
|
|
AES_BLOCK_SIZE));
|
|
|
|
else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS)
|
2018-01-11 18:15:50 +07:00
|
|
|
ret = chcr_update_tweak(req, iv, 1);
|
2017-06-15 14:13:43 +07:00
|
|
|
else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) {
|
|
|
|
if (reqctx->op)
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src), iv,
|
|
|
|
16,
|
|
|
|
reqctx->processed - AES_BLOCK_SIZE);
|
|
|
|
else
|
|
|
|
memcpy(iv, &fw6_pld->data[2], AES_BLOCK_SIZE);
|
|
|
|
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_handle_cipher_resp(struct ablkcipher_request *req,
|
|
|
|
unsigned char *input, int err)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(c_ctx(tfm));
|
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(tfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
struct sk_buff *skb;
|
2017-06-15 14:13:43 +07:00
|
|
|
struct cpl_fw6_pld *fw6_pld = (struct cpl_fw6_pld *)input;
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
struct cipher_wr_param wrparam;
|
|
|
|
int bytes;
|
|
|
|
|
|
|
|
if (err)
|
2017-10-08 15:07:23 +07:00
|
|
|
goto unmap;
|
2017-06-15 14:13:43 +07:00
|
|
|
if (req->nbytes == reqctx->processed) {
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_cipher_dma_unmap(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
req);
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_final_cipher_iv(req, fw6_pld, req->info);
|
|
|
|
goto complete;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
c_ctx(tfm)->tx_qidx))) {
|
2017-06-15 14:13:43 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
|
|
|
|
err = -EBUSY;
|
2017-10-08 15:07:23 +07:00
|
|
|
goto unmap;
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
if (!reqctx->imm) {
|
|
|
|
bytes = chcr_sg_ent_in_wr(reqctx->srcsg, reqctx->dstsg, 1,
|
|
|
|
SPACE_LEFT(ablkctx->enckey_len),
|
|
|
|
reqctx->src_ofst, reqctx->dst_ofst);
|
2018-01-11 18:15:48 +07:00
|
|
|
if ((bytes + reqctx->processed) >= req->nbytes)
|
|
|
|
bytes = req->nbytes - reqctx->processed;
|
|
|
|
else
|
|
|
|
bytes = ROUND_16(bytes);
|
2017-10-08 15:07:23 +07:00
|
|
|
} else {
|
|
|
|
/*CTR mode counter overfloa*/
|
|
|
|
bytes = req->nbytes - reqctx->processed;
|
|
|
|
}
|
|
|
|
dma_sync_single_for_cpu(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
reqctx->iv_dma, IV, DMA_BIDIRECTIONAL);
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_update_cipher_iv(req, fw6_pld, reqctx->iv);
|
2017-10-08 15:07:23 +07:00
|
|
|
dma_sync_single_for_device(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
reqctx->iv_dma, IV, DMA_BIDIRECTIONAL);
|
2017-06-15 14:13:43 +07:00
|
|
|
if (err)
|
2017-10-08 15:07:23 +07:00
|
|
|
goto unmap;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
if (unlikely(bytes == 0)) {
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_cipher_dma_unmap(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
req);
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_cipher_fallback(ablkctx->sw_cipher,
|
|
|
|
req->base.flags,
|
2017-10-08 15:07:23 +07:00
|
|
|
req->src,
|
|
|
|
req->dst,
|
|
|
|
req->nbytes,
|
|
|
|
req->info,
|
2017-06-15 14:13:43 +07:00
|
|
|
reqctx->op);
|
|
|
|
goto complete;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
|
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR)
|
|
|
|
bytes = adjust_ctr_overflow(reqctx->iv, bytes);
|
2017-10-08 15:07:23 +07:00
|
|
|
wrparam.qid = u_ctx->lldi.rxq_ids[c_ctx(tfm)->rx_qidx];
|
2017-06-15 14:13:43 +07:00
|
|
|
wrparam.req = req;
|
|
|
|
wrparam.bytes = bytes;
|
|
|
|
skb = create_cipher_wr(&wrparam);
|
|
|
|
if (IS_ERR(skb)) {
|
|
|
|
pr_err("chcr : %s : Failed to form WR. No memory\n", __func__);
|
|
|
|
err = PTR_ERR(skb);
|
2017-10-08 15:07:23 +07:00
|
|
|
goto unmap;
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, c_ctx(tfm)->tx_qidx);
|
2017-06-15 14:13:43 +07:00
|
|
|
chcr_send_wr(skb);
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->last_req_len = bytes;
|
|
|
|
reqctx->processed += bytes;
|
2017-06-15 14:13:43 +07:00
|
|
|
return 0;
|
2017-10-08 15:07:23 +07:00
|
|
|
unmap:
|
|
|
|
chcr_cipher_dma_unmap(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev, req);
|
2017-06-15 14:13:43 +07:00
|
|
|
complete:
|
|
|
|
req->base.complete(&req->base, err);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int process_cipher(struct ablkcipher_request *req,
|
|
|
|
unsigned short qid,
|
|
|
|
struct sk_buff **skb,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(tfm));
|
2017-06-15 14:13:43 +07:00
|
|
|
struct cipher_wr_param wrparam;
|
2017-10-08 15:07:22 +07:00
|
|
|
int bytes, err = -EINVAL;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
reqctx->processed = 0;
|
|
|
|
if (!req->info)
|
|
|
|
goto error;
|
|
|
|
if ((ablkctx->enckey_len == 0) || (ivsize > AES_BLOCK_SIZE) ||
|
|
|
|
(req->nbytes == 0) ||
|
|
|
|
(req->nbytes % crypto_ablkcipher_blocksize(tfm))) {
|
|
|
|
pr_err("AES: Invalid value of Key Len %d nbytes %d IV Len %d\n",
|
|
|
|
ablkctx->enckey_len, req->nbytes, ivsize);
|
|
|
|
goto error;
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_cipher_dma_map(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev, req);
|
|
|
|
if (req->nbytes < (SGE_MAX_WR_LEN - (sizeof(struct chcr_wr) +
|
|
|
|
AES_MIN_KEY_SIZE +
|
|
|
|
sizeof(struct cpl_rx_phys_dsgl) +
|
|
|
|
/*Min dsgl size*/
|
|
|
|
32))) {
|
|
|
|
/* Can be sent as Imm*/
|
|
|
|
unsigned int dnents = 0, transhdr_len, phys_dsgl, kctx_len;
|
|
|
|
|
|
|
|
dnents = sg_nents_xlen(req->dst, req->nbytes,
|
|
|
|
CHCR_DST_SG_SIZE, 0);
|
|
|
|
dnents += 1; // IV
|
|
|
|
phys_dsgl = get_space_for_phys_dsgl(dnents);
|
|
|
|
kctx_len = (DIV_ROUND_UP(ablkctx->enckey_len, 16) * 16);
|
|
|
|
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, phys_dsgl);
|
|
|
|
reqctx->imm = (transhdr_len + IV + req->nbytes) <=
|
|
|
|
SGE_MAX_WR_LEN;
|
|
|
|
bytes = IV + req->nbytes;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
reqctx->imm = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!reqctx->imm) {
|
|
|
|
bytes = chcr_sg_ent_in_wr(req->src, req->dst,
|
|
|
|
MIN_CIPHER_SG,
|
|
|
|
SPACE_LEFT(ablkctx->enckey_len),
|
|
|
|
0, 0);
|
2018-01-11 18:15:48 +07:00
|
|
|
if ((bytes + reqctx->processed) >= req->nbytes)
|
|
|
|
bytes = req->nbytes - reqctx->processed;
|
|
|
|
else
|
|
|
|
bytes = ROUND_16(bytes);
|
2017-10-08 15:07:23 +07:00
|
|
|
} else {
|
2017-06-15 14:13:43 +07:00
|
|
|
bytes = req->nbytes;
|
2017-10-08 15:07:23 +07:00
|
|
|
}
|
2017-06-15 14:13:43 +07:00
|
|
|
if (get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
|
2018-01-11 18:15:48 +07:00
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR) {
|
2017-06-15 14:13:43 +07:00
|
|
|
bytes = adjust_ctr_overflow(req->info, bytes);
|
|
|
|
}
|
|
|
|
if (get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
|
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR_RFC3686) {
|
|
|
|
memcpy(reqctx->iv, ablkctx->nonce, CTR_RFC3686_NONCE_SIZE);
|
|
|
|
memcpy(reqctx->iv + CTR_RFC3686_NONCE_SIZE, req->info,
|
|
|
|
CTR_RFC3686_IV_SIZE);
|
|
|
|
|
|
|
|
/* initialize counter portion of counter block */
|
|
|
|
*(__be32 *)(reqctx->iv + CTR_RFC3686_NONCE_SIZE +
|
|
|
|
CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
memcpy(reqctx->iv, req->info, IV);
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
if (unlikely(bytes == 0)) {
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_cipher_dma_unmap(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
req);
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_cipher_fallback(ablkctx->sw_cipher,
|
|
|
|
req->base.flags,
|
|
|
|
req->src,
|
|
|
|
req->dst,
|
|
|
|
req->nbytes,
|
|
|
|
req->info,
|
|
|
|
op_type);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
reqctx->op = op_type;
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->srcsg = req->src;
|
|
|
|
reqctx->dstsg = req->dst;
|
|
|
|
reqctx->src_ofst = 0;
|
|
|
|
reqctx->dst_ofst = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
wrparam.qid = qid;
|
|
|
|
wrparam.req = req;
|
|
|
|
wrparam.bytes = bytes;
|
|
|
|
*skb = create_cipher_wr(&wrparam);
|
|
|
|
if (IS_ERR(*skb)) {
|
|
|
|
err = PTR_ERR(*skb);
|
2017-10-08 15:07:23 +07:00
|
|
|
goto unmap;
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->processed = bytes;
|
|
|
|
reqctx->last_req_len = bytes;
|
2017-06-15 14:13:43 +07:00
|
|
|
|
|
|
|
return 0;
|
2017-10-08 15:07:23 +07:00
|
|
|
unmap:
|
|
|
|
chcr_cipher_dma_unmap(&ULD_CTX(c_ctx(tfm))->lldi.pdev->dev, req);
|
2017-06-15 14:13:43 +07:00
|
|
|
error:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_aes_encrypt(struct ablkcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
|
|
|
struct sk_buff *skb = NULL;
|
|
|
|
int err;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(c_ctx(tfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
c_ctx(tfm)->tx_qidx))) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
err = process_cipher(req, u_ctx->lldi.rxq_ids[c_ctx(tfm)->rx_qidx],
|
|
|
|
&skb, CHCR_ENCRYPT_OP);
|
2017-06-15 14:13:43 +07:00
|
|
|
if (err || !skb)
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, c_ctx(tfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_aes_decrypt(struct ablkcipher_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(c_ctx(tfm));
|
2017-06-15 14:13:43 +07:00
|
|
|
struct sk_buff *skb = NULL;
|
|
|
|
int err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
c_ctx(tfm)->tx_qidx))) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
err = process_cipher(req, u_ctx->lldi.rxq_ids[c_ctx(tfm)->rx_qidx],
|
|
|
|
&skb, CHCR_DECRYPT_OP);
|
2017-06-15 14:13:43 +07:00
|
|
|
if (err || !skb)
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, c_ctx(tfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_device_init(struct chcr_context *ctx)
|
|
|
|
{
|
2017-06-15 14:13:47 +07:00
|
|
|
struct uld_ctx *u_ctx = NULL;
|
2017-04-10 19:54:00 +07:00
|
|
|
struct adapter *adap;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int id;
|
2017-04-10 19:54:00 +07:00
|
|
|
int txq_perchan, txq_idx, ntxq;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
int err = 0, rxq_perchan, rxq_idx;
|
|
|
|
|
|
|
|
id = smp_processor_id();
|
|
|
|
if (!ctx->dev) {
|
2017-06-15 14:13:47 +07:00
|
|
|
u_ctx = assign_chcr_device();
|
|
|
|
if (!u_ctx) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
pr_err("chcr device assignment fails\n");
|
|
|
|
goto out;
|
|
|
|
}
|
2017-06-15 14:13:47 +07:00
|
|
|
ctx->dev = u_ctx->dev;
|
2017-04-10 19:54:00 +07:00
|
|
|
adap = padap(ctx->dev);
|
|
|
|
ntxq = min_not_zero((unsigned int)u_ctx->lldi.nrxq,
|
|
|
|
adap->vres.ncrypto_fc);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
rxq_perchan = u_ctx->lldi.nrxq / u_ctx->lldi.nchan;
|
2017-04-10 19:54:00 +07:00
|
|
|
txq_perchan = ntxq / u_ctx->lldi.nchan;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
rxq_idx = ctx->dev->tx_channel_id * rxq_perchan;
|
|
|
|
rxq_idx += id % rxq_perchan;
|
2017-04-10 19:54:00 +07:00
|
|
|
txq_idx = ctx->dev->tx_channel_id * txq_perchan;
|
|
|
|
txq_idx += id % txq_perchan;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
spin_lock(&ctx->dev->lock_chcr_dev);
|
2017-04-10 19:54:00 +07:00
|
|
|
ctx->rx_qidx = rxq_idx;
|
|
|
|
ctx->tx_qidx = txq_idx;
|
2016-11-18 18:07:40 +07:00
|
|
|
ctx->dev->tx_channel_id = !ctx->dev->tx_channel_id;
|
2017-01-27 17:39:05 +07:00
|
|
|
ctx->dev->rx_channel_id = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
spin_unlock(&ctx->dev->lock_chcr_dev);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
2017-06-15 14:13:43 +07:00
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
|
|
|
|
|
|
|
|
ablkctx->sw_cipher = crypto_alloc_skcipher(alg->cra_name, 0,
|
|
|
|
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
|
|
|
|
if (IS_ERR(ablkctx->sw_cipher)) {
|
|
|
|
pr_err("failed to allocate fallback for %s\n", alg->cra_name);
|
|
|
|
return PTR_ERR(ablkctx->sw_cipher);
|
|
|
|
}
|
2017-06-23 21:15:11 +07:00
|
|
|
|
|
|
|
if (get_cryptoalg_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_XTS) {
|
|
|
|
/* To update tweak*/
|
|
|
|
ablkctx->aes_generic = crypto_alloc_cipher("aes-generic", 0, 0);
|
|
|
|
if (IS_ERR(ablkctx->aes_generic)) {
|
|
|
|
pr_err("failed to allocate aes cipher for tweak\n");
|
|
|
|
return PTR_ERR(ablkctx->aes_generic);
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
ablkctx->aes_generic = NULL;
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct chcr_blkcipher_req_ctx);
|
|
|
|
return chcr_device_init(crypto_tfm_ctx(tfm));
|
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
static int chcr_rfc3686_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct crypto_alg *alg = tfm->__crt_alg;
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
|
|
|
|
|
|
|
|
/*RFC3686 initialises IV counter value to 1, rfc3686(ctr(aes))
|
|
|
|
* cannot be used as fallback in chcr_handle_cipher_response
|
|
|
|
*/
|
|
|
|
ablkctx->sw_cipher = crypto_alloc_skcipher("ctr(aes)", 0,
|
|
|
|
CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK);
|
|
|
|
if (IS_ERR(ablkctx->sw_cipher)) {
|
|
|
|
pr_err("failed to allocate fallback for %s\n", alg->cra_name);
|
|
|
|
return PTR_ERR(ablkctx->sw_cipher);
|
|
|
|
}
|
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct chcr_blkcipher_req_ctx);
|
|
|
|
return chcr_device_init(crypto_tfm_ctx(tfm));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void chcr_cra_exit(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(ctx);
|
|
|
|
|
|
|
|
crypto_free_skcipher(ablkctx->sw_cipher);
|
2017-06-23 21:15:11 +07:00
|
|
|
if (ablkctx->aes_generic)
|
|
|
|
crypto_free_cipher(ablkctx->aes_generic);
|
2017-06-15 14:13:43 +07:00
|
|
|
}
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
static int get_alg_config(struct algo_param *params,
|
|
|
|
unsigned int auth_size)
|
|
|
|
{
|
|
|
|
switch (auth_size) {
|
|
|
|
case SHA1_DIGEST_SIZE:
|
|
|
|
params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160;
|
|
|
|
params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA1;
|
|
|
|
params->result_size = SHA1_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case SHA224_DIGEST_SIZE:
|
|
|
|
params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
|
|
|
|
params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA224;
|
|
|
|
params->result_size = SHA256_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case SHA256_DIGEST_SIZE:
|
|
|
|
params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
|
|
|
|
params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA256;
|
|
|
|
params->result_size = SHA256_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case SHA384_DIGEST_SIZE:
|
|
|
|
params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
|
|
|
|
params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384;
|
|
|
|
params->result_size = SHA512_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
case SHA512_DIGEST_SIZE:
|
|
|
|
params->mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512;
|
|
|
|
params->auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512;
|
|
|
|
params->result_size = SHA512_DIGEST_SIZE;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_err("chcr : ERROR, unsupported digest size\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
static inline void chcr_free_shash(struct crypto_shash *base_hash)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
2016-11-29 20:30:41 +07:00
|
|
|
crypto_free_shash(base_hash);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2016-11-29 20:30:36 +07:00
|
|
|
* create_hash_wr - Create hash work request
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
* @req - Cipher req base
|
|
|
|
*/
|
2016-11-29 20:30:36 +07:00
|
|
|
static struct sk_buff *create_hash_wr(struct ahash_request *req,
|
2016-11-29 20:30:43 +07:00
|
|
|
struct hash_wr_param *param)
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct hmac_ctx *hmacctx = HMAC_CTX(h_ctx(tfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
struct sk_buff *skb = NULL;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct uld_ctx *u_ctx = ULD_CTX(h_ctx(tfm));
|
2016-11-29 20:30:36 +07:00
|
|
|
struct chcr_wr *chcr_req;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ulptx_sgl *ulptx;
|
|
|
|
unsigned int nents = 0, transhdr_len, iopad_alignment = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int digestsize = crypto_ahash_digestsize(tfm);
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int kctx_len = 0, temp = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
u8 hash_size_in_response = 0;
|
2016-11-29 20:30:36 +07:00
|
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
|
|
|
|
GFP_ATOMIC;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct adapter *adap = padap(h_ctx(tfm)->dev);
|
|
|
|
int error = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
iopad_alignment = KEYCTX_ALIGN_PAD(digestsize);
|
2016-11-29 20:30:36 +07:00
|
|
|
kctx_len = param->alg_prm.result_size + iopad_alignment;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (param->opad_needed)
|
|
|
|
kctx_len += param->alg_prm.result_size + iopad_alignment;
|
|
|
|
|
|
|
|
if (req_ctx->result)
|
|
|
|
hash_size_in_response = digestsize;
|
|
|
|
else
|
|
|
|
hash_size_in_response = param->alg_prm.result_size;
|
|
|
|
transhdr_len = HASH_TRANSHDR_SIZE(kctx_len);
|
2017-10-08 15:07:23 +07:00
|
|
|
req_ctx->imm = (transhdr_len + param->bfr_len + param->sg_len) <=
|
|
|
|
SGE_MAX_WR_LEN;
|
|
|
|
nents = sg_nents_xlen(req->src, param->sg_len, CHCR_SRC_SG_SIZE, 0);
|
|
|
|
nents += param->bfr_len ? 1 : 0;
|
|
|
|
transhdr_len += req_ctx->imm ? (DIV_ROUND_UP((param->bfr_len +
|
|
|
|
param->sg_len), 16) * 16) :
|
|
|
|
(sgl_len(nents) * 8);
|
|
|
|
transhdr_len = DIV_ROUND_UP(transhdr_len, 16) * 16;
|
|
|
|
|
|
|
|
skb = alloc_skb(SGE_MAX_WR_LEN, flags);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!skb)
|
2017-10-08 15:07:23 +07:00
|
|
|
return ERR_PTR(-ENOMEM);
|
net: introduce __skb_put_[zero, data, u8]
follow Johannes Berg, semantic patch file as below,
@@
identifier p, p2;
expression len;
expression skb;
type t, t2;
@@
(
-p = __skb_put(skb, len);
+p = __skb_put_zero(skb, len);
|
-p = (t)__skb_put(skb, len);
+p = __skb_put_zero(skb, len);
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, len);
|
-memset(p, 0, len);
)
@@
identifier p;
expression len;
expression skb;
type t;
@@
(
-t p = __skb_put(skb, len);
+t p = __skb_put_zero(skb, len);
)
... when != p
(
-memset(p, 0, len);
)
@@
type t, t2;
identifier p, p2;
expression skb;
@@
t *p;
...
(
-p = __skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
|
-p = (t *)__skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, sizeof(*p));
|
-memset(p, 0, sizeof(*p));
)
@@
expression skb, len;
@@
-memset(__skb_put(skb, len), 0, len);
+__skb_put_zero(skb, len);
@@
expression skb, len, data;
@@
-memcpy(__skb_put(skb, len), data, len);
+__skb_put_data(skb, data, len);
@@
expression SKB, C, S;
typedef u8;
identifier fn = {__skb_put};
fresh identifier fn2 = fn ## "_u8";
@@
- *(u8 *)fn(SKB, S) = C;
+ fn2(SKB, C);
Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18 21:48:17 +07:00
|
|
|
chcr_req = __skb_put_zero(skb, transhdr_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.op_ivinsrtofst =
|
2017-10-08 15:07:23 +07:00
|
|
|
FILL_SEC_CPL_OP_IVINSR(h_ctx(tfm)->dev->rx_channel_id, 2, 0);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.pldlen = htonl(param->bfr_len + param->sg_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.aadstart_cipherstop_hi =
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
FILL_SEC_CPL_CIPHERSTOP_HI(0, 0, 0, 0);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.cipherstop_lo_authinsert =
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
FILL_SEC_CPL_AUTHINSERT(0, 1, 0, 0);
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.seqno_numivs =
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
FILL_SEC_CPL_SCMD0_SEQNO(0, 0, 0, param->alg_prm.auth_mode,
|
2016-11-29 20:30:36 +07:00
|
|
|
param->opad_needed, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->sec_cpl.ivgen_hdrlen =
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
FILL_SEC_CPL_IVGEN_HDRLEN(param->last, param->more, 0, 1, 0, 0);
|
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key, req_ctx->partial_hash,
|
|
|
|
param->alg_prm.result_size);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
if (param->opad_needed)
|
2016-11-29 20:30:36 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key +
|
|
|
|
((param->alg_prm.result_size <= 32) ? 32 :
|
|
|
|
CHCR_HASH_MAX_DIGEST_SIZE),
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
hmacctx->opad, param->alg_prm.result_size);
|
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
chcr_req->key_ctx.ctx_hdr = FILL_KEY_CTX_HDR(CHCR_KEYCTX_NO_KEY,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
param->alg_prm.mk_size, 0,
|
|
|
|
param->opad_needed,
|
2016-11-29 20:30:36 +07:00
|
|
|
((kctx_len +
|
|
|
|
sizeof(chcr_req->key_ctx)) >> 4));
|
|
|
|
chcr_req->sec_cpl.scmd1 = cpu_to_be64((u64)param->scmd1);
|
2017-10-08 15:07:23 +07:00
|
|
|
ulptx = (struct ulptx_sgl *)((u8 *)(chcr_req + 1) + kctx_len +
|
|
|
|
DUMMY_BYTES);
|
|
|
|
if (param->bfr_len != 0) {
|
|
|
|
req_ctx->dma_addr = dma_map_single(&u_ctx->lldi.pdev->dev,
|
|
|
|
req_ctx->reqbfr, param->bfr_len,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(&u_ctx->lldi.pdev->dev,
|
|
|
|
req_ctx->dma_addr)) {
|
|
|
|
error = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
req_ctx->dma_len = param->bfr_len;
|
|
|
|
} else {
|
|
|
|
req_ctx->dma_addr = 0;
|
|
|
|
}
|
|
|
|
chcr_add_hash_src_ent(req, ulptx, param);
|
|
|
|
/* Request upto max wr size */
|
|
|
|
temp = kctx_len + DUMMY_BYTES + (req_ctx->imm ? (param->sg_len
|
|
|
|
+ param->bfr_len) : 0);
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.digest_rqst);
|
2017-10-08 15:07:23 +07:00
|
|
|
create_wreq(h_ctx(tfm), chcr_req, &req->base, req_ctx->imm,
|
|
|
|
hash_size_in_response, transhdr_len,
|
|
|
|
temp, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
req_ctx->skb = skb;
|
|
|
|
return skb;
|
2017-10-08 15:07:23 +07:00
|
|
|
err:
|
|
|
|
kfree_skb(skb);
|
|
|
|
return ERR_PTR(error);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_update(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct uld_ctx *u_ctx = NULL;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
u8 remainder = 0, bs;
|
|
|
|
unsigned int nbytes = req->nbytes;
|
|
|
|
struct hash_wr_param params;
|
2017-10-08 15:07:23 +07:00
|
|
|
int error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
u_ctx = ULD_CTX(h_ctx(rtfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
h_ctx(rtfm)->tx_qidx))) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:38 +07:00
|
|
|
if (nbytes + req_ctx->reqlen >= bs) {
|
|
|
|
remainder = (nbytes + req_ctx->reqlen) % bs;
|
|
|
|
nbytes = nbytes + req_ctx->reqlen - remainder;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
} else {
|
2016-11-29 20:30:38 +07:00
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src), req_ctx->reqbfr
|
|
|
|
+ req_ctx->reqlen, nbytes, 0);
|
|
|
|
req_ctx->reqlen += nbytes;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
return 0;
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
error = chcr_hash_dma_map(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
if (error)
|
|
|
|
return -ENOMEM;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
params.opad_needed = 0;
|
|
|
|
params.more = 1;
|
|
|
|
params.last = 0;
|
2016-11-29 20:30:38 +07:00
|
|
|
params.sg_len = nbytes - req_ctx->reqlen;
|
|
|
|
params.bfr_len = req_ctx->reqlen;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
params.scmd1 = 0;
|
|
|
|
get_alg_config(¶ms.alg_prm, crypto_ahash_digestsize(rtfm));
|
|
|
|
req_ctx->result = 0;
|
|
|
|
req_ctx->data_len += params.sg_len + params.bfr_len;
|
2016-11-29 20:30:36 +07:00
|
|
|
skb = create_hash_wr(req, ¶ms);
|
2017-10-08 15:07:23 +07:00
|
|
|
if (IS_ERR(skb)) {
|
|
|
|
error = PTR_ERR(skb);
|
|
|
|
goto unmap;
|
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:38 +07:00
|
|
|
if (remainder) {
|
|
|
|
/* Swap buffers */
|
2017-11-03 23:58:23 +07:00
|
|
|
swap(req_ctx->reqbfr, req_ctx->skbfr);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src),
|
2016-11-29 20:30:38 +07:00
|
|
|
req_ctx->reqbfr, remainder, req->nbytes -
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
remainder);
|
2016-11-29 20:30:38 +07:00
|
|
|
}
|
|
|
|
req_ctx->reqlen = remainder;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, h_ctx(rtfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
|
|
|
|
return -EINPROGRESS;
|
2017-10-08 15:07:23 +07:00
|
|
|
unmap:
|
|
|
|
chcr_hash_dma_unmap(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
return error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void create_last_hash_block(char *bfr_ptr, unsigned int bs, u64 scmd1)
|
|
|
|
{
|
|
|
|
memset(bfr_ptr, 0, bs);
|
|
|
|
*bfr_ptr = 0x80;
|
|
|
|
if (bs == 64)
|
|
|
|
*(__be64 *)(bfr_ptr + 56) = cpu_to_be64(scmd1 << 3);
|
|
|
|
else
|
|
|
|
*(__be64 *)(bfr_ptr + 120) = cpu_to_be64(scmd1 << 3);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_final(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct hash_wr_param params;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct uld_ctx *u_ctx = NULL;
|
|
|
|
u8 bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
u_ctx = ULD_CTX(h_ctx(rtfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (is_hmac(crypto_ahash_tfm(rtfm)))
|
|
|
|
params.opad_needed = 1;
|
|
|
|
else
|
|
|
|
params.opad_needed = 0;
|
|
|
|
params.sg_len = 0;
|
|
|
|
get_alg_config(¶ms.alg_prm, crypto_ahash_digestsize(rtfm));
|
|
|
|
req_ctx->result = 1;
|
2016-11-29 20:30:38 +07:00
|
|
|
params.bfr_len = req_ctx->reqlen;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
req_ctx->data_len += params.bfr_len + params.sg_len;
|
2016-11-29 20:30:38 +07:00
|
|
|
if (req_ctx->reqlen == 0) {
|
|
|
|
create_last_hash_block(req_ctx->reqbfr, bs, req_ctx->data_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
params.last = 0;
|
|
|
|
params.more = 1;
|
|
|
|
params.scmd1 = 0;
|
|
|
|
params.bfr_len = bs;
|
|
|
|
|
|
|
|
} else {
|
|
|
|
params.scmd1 = req_ctx->data_len;
|
|
|
|
params.last = 1;
|
|
|
|
params.more = 0;
|
|
|
|
}
|
2016-11-29 20:30:36 +07:00
|
|
|
skb = create_hash_wr(req, ¶ms);
|
2017-10-08 15:07:19 +07:00
|
|
|
if (IS_ERR(skb))
|
|
|
|
return PTR_ERR(skb);
|
2016-11-29 20:30:36 +07:00
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, h_ctx(rtfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_finup(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct uld_ctx *u_ctx = NULL;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct hash_wr_param params;
|
|
|
|
u8 bs;
|
2017-10-08 15:07:23 +07:00
|
|
|
int error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
|
2017-10-08 15:07:23 +07:00
|
|
|
u_ctx = ULD_CTX(h_ctx(rtfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
h_ctx(rtfm)->tx_qidx))) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_hmac(crypto_ahash_tfm(rtfm)))
|
|
|
|
params.opad_needed = 1;
|
|
|
|
else
|
|
|
|
params.opad_needed = 0;
|
|
|
|
|
|
|
|
params.sg_len = req->nbytes;
|
2016-11-29 20:30:38 +07:00
|
|
|
params.bfr_len = req_ctx->reqlen;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
get_alg_config(¶ms.alg_prm, crypto_ahash_digestsize(rtfm));
|
|
|
|
req_ctx->data_len += params.bfr_len + params.sg_len;
|
|
|
|
req_ctx->result = 1;
|
2016-11-29 20:30:38 +07:00
|
|
|
if ((req_ctx->reqlen + req->nbytes) == 0) {
|
|
|
|
create_last_hash_block(req_ctx->reqbfr, bs, req_ctx->data_len);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
params.last = 0;
|
|
|
|
params.more = 1;
|
|
|
|
params.scmd1 = 0;
|
|
|
|
params.bfr_len = bs;
|
|
|
|
} else {
|
|
|
|
params.scmd1 = req_ctx->data_len;
|
|
|
|
params.last = 1;
|
|
|
|
params.more = 0;
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
error = chcr_hash_dma_map(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
if (error)
|
|
|
|
return -ENOMEM;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
skb = create_hash_wr(req, ¶ms);
|
2017-10-08 15:07:23 +07:00
|
|
|
if (IS_ERR(skb)) {
|
|
|
|
error = PTR_ERR(skb);
|
|
|
|
goto unmap;
|
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, h_ctx(rtfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
|
|
|
|
return -EINPROGRESS;
|
2017-10-08 15:07:23 +07:00
|
|
|
unmap:
|
|
|
|
chcr_hash_dma_unmap(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
return error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_digest(struct ahash_request *req)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
struct crypto_ahash *rtfm = crypto_ahash_reqtfm(req);
|
|
|
|
struct uld_ctx *u_ctx = NULL;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
struct hash_wr_param params;
|
|
|
|
u8 bs;
|
2017-10-08 15:07:23 +07:00
|
|
|
int error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
rtfm->init(req);
|
|
|
|
bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
u_ctx = ULD_CTX(h_ctx(rtfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (unlikely(cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
2017-10-08 15:07:23 +07:00
|
|
|
h_ctx(rtfm)->tx_qidx))) {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_hmac(crypto_ahash_tfm(rtfm)))
|
|
|
|
params.opad_needed = 1;
|
|
|
|
else
|
|
|
|
params.opad_needed = 0;
|
2017-10-08 15:07:23 +07:00
|
|
|
error = chcr_hash_dma_map(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
if (error)
|
|
|
|
return -ENOMEM;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
|
|
|
params.last = 0;
|
|
|
|
params.more = 0;
|
|
|
|
params.sg_len = req->nbytes;
|
|
|
|
params.bfr_len = 0;
|
|
|
|
params.scmd1 = 0;
|
|
|
|
get_alg_config(¶ms.alg_prm, crypto_ahash_digestsize(rtfm));
|
|
|
|
req_ctx->result = 1;
|
|
|
|
req_ctx->data_len += params.bfr_len + params.sg_len;
|
|
|
|
|
2016-11-29 20:30:38 +07:00
|
|
|
if (req->nbytes == 0) {
|
|
|
|
create_last_hash_block(req_ctx->reqbfr, bs, 0);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
params.more = 1;
|
|
|
|
params.bfr_len = bs;
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:36 +07:00
|
|
|
skb = create_hash_wr(req, ¶ms);
|
2017-10-08 15:07:23 +07:00
|
|
|
if (IS_ERR(skb)) {
|
|
|
|
error = PTR_ERR(skb);
|
|
|
|
goto unmap;
|
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
2017-10-08 15:07:23 +07:00
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, h_ctx(rtfm)->tx_qidx);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
chcr_send_wr(skb);
|
|
|
|
return -EINPROGRESS;
|
2017-10-08 15:07:23 +07:00
|
|
|
unmap:
|
|
|
|
chcr_hash_dma_unmap(&u_ctx->lldi.pdev->dev, req);
|
|
|
|
return error;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_export(struct ahash_request *areq, void *out)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct chcr_ahash_req_ctx *state = out;
|
|
|
|
|
2016-11-29 20:30:38 +07:00
|
|
|
state->reqlen = req_ctx->reqlen;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
state->data_len = req_ctx->data_len;
|
2017-10-08 15:07:23 +07:00
|
|
|
state->is_sg_map = 0;
|
|
|
|
state->result = 0;
|
2016-11-29 20:30:38 +07:00
|
|
|
memcpy(state->bfr1, req_ctx->reqbfr, req_ctx->reqlen);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
memcpy(state->partial_hash, req_ctx->partial_hash,
|
|
|
|
CHCR_HASH_MAX_DIGEST_SIZE);
|
2016-11-29 20:30:38 +07:00
|
|
|
return 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_import(struct ahash_request *areq, const void *in)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct chcr_ahash_req_ctx *state = (struct chcr_ahash_req_ctx *)in;
|
|
|
|
|
2016-11-29 20:30:38 +07:00
|
|
|
req_ctx->reqlen = state->reqlen;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
req_ctx->data_len = state->data_len;
|
2016-11-29 20:30:38 +07:00
|
|
|
req_ctx->reqbfr = req_ctx->bfr1;
|
|
|
|
req_ctx->skbfr = req_ctx->bfr2;
|
2017-10-08 15:07:23 +07:00
|
|
|
req_ctx->is_sg_map = 0;
|
|
|
|
req_ctx->result = 0;
|
2016-11-29 20:30:38 +07:00
|
|
|
memcpy(req_ctx->bfr1, state->bfr1, CHCR_HASH_MAX_BLOCK_SIZE_128);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
memcpy(req_ctx->partial_hash, state->partial_hash,
|
|
|
|
CHCR_HASH_MAX_DIGEST_SIZE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct hmac_ctx *hmacctx = HMAC_CTX(h_ctx(tfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int digestsize = crypto_ahash_digestsize(tfm);
|
|
|
|
unsigned int bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
|
|
|
|
unsigned int i, err = 0, updated_digestsize;
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
SHASH_DESC_ON_STACK(shash, hmacctx->base_hash);
|
|
|
|
|
|
|
|
/* use the key to calculate the ipad and opad. ipad will sent with the
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
* first request's data. opad will be sent with the final hash result
|
|
|
|
* ipad in hmacctx->ipad and opad in hmacctx->opad location
|
|
|
|
*/
|
2016-11-29 20:30:41 +07:00
|
|
|
shash->tfm = hmacctx->base_hash;
|
|
|
|
shash->flags = crypto_shash_get_flags(hmacctx->base_hash);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
if (keylen > bs) {
|
2016-11-29 20:30:41 +07:00
|
|
|
err = crypto_shash_digest(shash, key, keylen,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
hmacctx->ipad);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
keylen = digestsize;
|
|
|
|
} else {
|
|
|
|
memcpy(hmacctx->ipad, key, keylen);
|
|
|
|
}
|
|
|
|
memset(hmacctx->ipad + keylen, 0, bs - keylen);
|
|
|
|
memcpy(hmacctx->opad, hmacctx->ipad, bs);
|
|
|
|
|
|
|
|
for (i = 0; i < bs / sizeof(int); i++) {
|
|
|
|
*((unsigned int *)(&hmacctx->ipad) + i) ^= IPAD_DATA;
|
|
|
|
*((unsigned int *)(&hmacctx->opad) + i) ^= OPAD_DATA;
|
|
|
|
}
|
|
|
|
|
|
|
|
updated_digestsize = digestsize;
|
|
|
|
if (digestsize == SHA224_DIGEST_SIZE)
|
|
|
|
updated_digestsize = SHA256_DIGEST_SIZE;
|
|
|
|
else if (digestsize == SHA384_DIGEST_SIZE)
|
|
|
|
updated_digestsize = SHA512_DIGEST_SIZE;
|
2016-11-29 20:30:41 +07:00
|
|
|
err = chcr_compute_partial_hash(shash, hmacctx->ipad,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
hmacctx->ipad, digestsize);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
chcr_change_order(hmacctx->ipad, updated_digestsize);
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
err = chcr_compute_partial_hash(shash, hmacctx->opad,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
hmacctx->opad, digestsize);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
chcr_change_order(hmacctx->opad, updated_digestsize);
|
|
|
|
out:
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
static int chcr_aes_xts_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int key_len)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(cipher));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned short context_size = 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
int err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
|
2017-06-15 14:13:43 +07:00
|
|
|
err = chcr_cipher_fallback_setkey(cipher, key, key_len);
|
|
|
|
if (err)
|
|
|
|
goto badkey_err;
|
2016-11-29 20:30:39 +07:00
|
|
|
|
|
|
|
memcpy(ablkctx->key, key, key_len);
|
|
|
|
ablkctx->enckey_len = key_len;
|
|
|
|
get_aes_decrypt_key(ablkctx->rrkey, ablkctx->key, key_len << 2);
|
|
|
|
context_size = (KEY_CONTEXT_HDR_SALT_AND_PAD + key_len) >> 4;
|
|
|
|
ablkctx->key_ctx_hdr =
|
|
|
|
FILL_KEY_CTX_HDR((key_len == AES_KEYSIZE_256) ?
|
|
|
|
CHCR_KEYCTX_CIPHER_KEY_SIZE_128 :
|
|
|
|
CHCR_KEYCTX_CIPHER_KEY_SIZE_256,
|
|
|
|
CHCR_KEYCTX_NO_KEY, 1,
|
|
|
|
0, context_size);
|
|
|
|
ablkctx->ciph_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS;
|
|
|
|
return 0;
|
2017-06-15 14:13:43 +07:00
|
|
|
badkey_err:
|
|
|
|
crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
ablkctx->enckey_len = 0;
|
|
|
|
|
|
|
|
return err;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_sha_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
|
|
|
|
int digestsize = crypto_ahash_digestsize(tfm);
|
|
|
|
|
|
|
|
req_ctx->data_len = 0;
|
2016-11-29 20:30:38 +07:00
|
|
|
req_ctx->reqlen = 0;
|
|
|
|
req_ctx->reqbfr = req_ctx->bfr1;
|
|
|
|
req_ctx->skbfr = req_ctx->bfr2;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
req_ctx->skb = NULL;
|
|
|
|
req_ctx->result = 0;
|
2017-10-08 15:07:23 +07:00
|
|
|
req_ctx->is_sg_map = 0;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
copy_hash_init_values(req_ctx->partial_hash, digestsize);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_sha_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct chcr_ahash_req_ctx));
|
|
|
|
return chcr_device_init(crypto_tfm_ctx(tfm));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_hmac_init(struct ahash_request *areq)
|
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
|
|
|
|
struct crypto_ahash *rtfm = crypto_ahash_reqtfm(areq);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct hmac_ctx *hmacctx = HMAC_CTX(h_ctx(rtfm));
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
unsigned int digestsize = crypto_ahash_digestsize(rtfm);
|
|
|
|
unsigned int bs = crypto_tfm_alg_blocksize(crypto_ahash_tfm(rtfm));
|
|
|
|
|
|
|
|
chcr_sha_init(areq);
|
|
|
|
req_ctx->data_len = bs;
|
|
|
|
if (is_hmac(crypto_ahash_tfm(rtfm))) {
|
|
|
|
if (digestsize == SHA224_DIGEST_SIZE)
|
|
|
|
memcpy(req_ctx->partial_hash, hmacctx->ipad,
|
|
|
|
SHA256_DIGEST_SIZE);
|
|
|
|
else if (digestsize == SHA384_DIGEST_SIZE)
|
|
|
|
memcpy(req_ctx->partial_hash, hmacctx->ipad,
|
|
|
|
SHA512_DIGEST_SIZE);
|
|
|
|
else
|
|
|
|
memcpy(req_ctx->partial_hash, hmacctx->ipad,
|
|
|
|
digestsize);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_hmac_cra_init(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
|
|
|
|
unsigned int digestsize =
|
|
|
|
crypto_ahash_digestsize(__crypto_ahash_cast(tfm));
|
|
|
|
|
|
|
|
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
|
|
|
sizeof(struct chcr_ahash_req_ctx));
|
2016-11-29 20:30:41 +07:00
|
|
|
hmacctx->base_hash = chcr_alloc_shash(digestsize);
|
|
|
|
if (IS_ERR(hmacctx->base_hash))
|
|
|
|
return PTR_ERR(hmacctx->base_hash);
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
return chcr_device_init(crypto_tfm_ctx(tfm));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void chcr_hmac_cra_exit(struct crypto_tfm *tfm)
|
|
|
|
{
|
|
|
|
struct chcr_context *ctx = crypto_tfm_ctx(tfm);
|
|
|
|
struct hmac_ctx *hmacctx = HMAC_CTX(ctx);
|
|
|
|
|
2016-11-29 20:30:41 +07:00
|
|
|
if (hmacctx->base_hash) {
|
|
|
|
chcr_free_shash(hmacctx->base_hash);
|
|
|
|
hmacctx->base_hash = NULL;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
static int chcr_aead_common_init(struct aead_request *req,
|
|
|
|
unsigned short op_type)
|
2016-11-29 20:30:43 +07:00
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
int error = -EINVAL;
|
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
/* validate key size */
|
|
|
|
if (aeadctx->enckey_len == 0)
|
|
|
|
goto err;
|
|
|
|
if (op_type && req->cryptlen < authsize)
|
|
|
|
goto err;
|
|
|
|
error = chcr_aead_dma_map(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req,
|
|
|
|
op_type);
|
|
|
|
if (error) {
|
|
|
|
error = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
reqctx->aad_nents = sg_nents_xlen(req->src, req->assoclen,
|
|
|
|
CHCR_SRC_SG_SIZE, 0);
|
|
|
|
reqctx->src_nents = sg_nents_xlen(req->src, req->cryptlen,
|
|
|
|
CHCR_SRC_SG_SIZE, req->assoclen);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
return error;
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
|
|
|
|
static int chcr_aead_need_fallback(struct aead_request *req, int dst_nents,
|
2017-04-10 19:54:01 +07:00
|
|
|
int aadmax, int wrlen,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
unsigned int authsize = crypto_aead_authsize(crypto_aead_reqtfm(req));
|
|
|
|
|
|
|
|
if (((req->cryptlen - (op_type ? authsize : 0)) == 0) ||
|
2017-10-08 15:07:23 +07:00
|
|
|
dst_nents > MAX_DSGL_ENT ||
|
2017-04-10 19:54:01 +07:00
|
|
|
(req->assoclen > aadmax) ||
|
2017-10-08 15:07:23 +07:00
|
|
|
(wrlen > SGE_MAX_WR_LEN))
|
2017-04-10 19:54:01 +07:00
|
|
|
return 1;
|
|
|
|
return 0;
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
static int chcr_aead_fallback(struct aead_request *req, unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2017-04-10 19:54:01 +07:00
|
|
|
struct aead_request *subreq = aead_request_ctx(req);
|
|
|
|
|
|
|
|
aead_request_set_tfm(subreq, aeadctx->sw_cipher);
|
|
|
|
aead_request_set_callback(subreq, req->base.flags,
|
|
|
|
req->base.complete, req->base.data);
|
|
|
|
aead_request_set_crypt(subreq, req->src, req->dst, req->cryptlen,
|
|
|
|
req->iv);
|
|
|
|
aead_request_set_ad(subreq, req->assoclen);
|
|
|
|
return op_type ? crypto_aead_decrypt(subreq) :
|
|
|
|
crypto_aead_encrypt(subreq);
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
static struct sk_buff *create_authenc_wr(struct aead_request *req,
|
|
|
|
unsigned short qid,
|
|
|
|
int size,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_authenc_ctx *actx = AUTHENC_CTX(aeadctx);
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct sk_buff *skb = NULL;
|
|
|
|
struct chcr_wr *chcr_req;
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ulptx_sgl *ulptx;
|
|
|
|
unsigned int transhdr_len;
|
2018-01-11 18:15:51 +07:00
|
|
|
unsigned int dst_size = 0, temp, subtype = get_aead_subtype(tfm);
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int kctx_len = 0, dnents;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int assoclen = req->assoclen;
|
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
2017-10-08 15:07:23 +07:00
|
|
|
int error = -EINVAL;
|
2016-11-29 20:30:43 +07:00
|
|
|
int null = 0;
|
|
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
|
|
|
|
GFP_ATOMIC;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct adapter *adap = padap(a_ctx(tfm)->dev);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
if (req->cryptlen == 0)
|
|
|
|
return NULL;
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->b0_dma = 0;
|
2018-01-11 18:15:51 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CBC_NULL ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
|
2016-11-29 20:30:43 +07:00
|
|
|
null = 1;
|
|
|
|
assoclen = 0;
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
dst_size = assoclen + req->cryptlen + (op_type ? -authsize :
|
|
|
|
authsize);
|
|
|
|
error = chcr_aead_common_init(req, op_type);
|
|
|
|
if (error)
|
|
|
|
return ERR_PTR(error);
|
|
|
|
if (dst_size) {
|
|
|
|
dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
|
|
|
|
dnents += sg_nents_xlen(req->dst, req->cryptlen +
|
|
|
|
(op_type ? -authsize : authsize), CHCR_DST_SG_SIZE,
|
|
|
|
req->assoclen);
|
|
|
|
dnents += MIN_AUTH_SG; // For IV
|
|
|
|
} else {
|
|
|
|
dnents = 0;
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
|
|
|
|
dst_size = get_space_for_phys_dsgl(dnents);
|
2016-11-29 20:30:43 +07:00
|
|
|
kctx_len = (ntohl(KEY_CONTEXT_CTX_LEN_V(aeadctx->key_ctx_hdr)) << 4)
|
|
|
|
- sizeof(chcr_req->key_ctx);
|
|
|
|
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dst_size);
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->imm = (transhdr_len + assoclen + IV + req->cryptlen) <
|
|
|
|
SGE_MAX_WR_LEN;
|
|
|
|
temp = reqctx->imm ? (DIV_ROUND_UP((assoclen + IV + req->cryptlen), 16)
|
|
|
|
* 16) : (sgl_len(reqctx->src_nents + reqctx->aad_nents
|
|
|
|
+ MIN_GCM_SG) * 8);
|
|
|
|
transhdr_len += temp;
|
|
|
|
transhdr_len = DIV_ROUND_UP(transhdr_len, 16) * 16;
|
|
|
|
|
|
|
|
if (chcr_aead_need_fallback(req, dnents, T6_MAX_AAD_SIZE,
|
|
|
|
transhdr_len, op_type)) {
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.fallback);
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req,
|
|
|
|
op_type);
|
2017-04-10 19:54:01 +07:00
|
|
|
return ERR_PTR(chcr_aead_fallback(req, op_type));
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
skb = alloc_skb(SGE_MAX_WR_LEN, flags);
|
2017-06-15 14:13:41 +07:00
|
|
|
if (!skb) {
|
|
|
|
error = -ENOMEM;
|
2016-11-29 20:30:43 +07:00
|
|
|
goto err;
|
2017-06-15 14:13:41 +07:00
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
|
net: introduce __skb_put_[zero, data, u8]
follow Johannes Berg, semantic patch file as below,
@@
identifier p, p2;
expression len;
expression skb;
type t, t2;
@@
(
-p = __skb_put(skb, len);
+p = __skb_put_zero(skb, len);
|
-p = (t)__skb_put(skb, len);
+p = __skb_put_zero(skb, len);
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, len);
|
-memset(p, 0, len);
)
@@
identifier p;
expression len;
expression skb;
type t;
@@
(
-t p = __skb_put(skb, len);
+t p = __skb_put_zero(skb, len);
)
... when != p
(
-memset(p, 0, len);
)
@@
type t, t2;
identifier p, p2;
expression skb;
@@
t *p;
...
(
-p = __skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
|
-p = (t *)__skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, sizeof(*p));
|
-memset(p, 0, sizeof(*p));
)
@@
expression skb, len;
@@
-memset(__skb_put(skb, len), 0, len);
+__skb_put_zero(skb, len);
@@
expression skb, len, data;
@@
-memcpy(__skb_put(skb, len), data, len);
+__skb_put_data(skb, data, len);
@@
expression SKB, C, S;
typedef u8;
identifier fn = {__skb_put};
fresh identifier fn2 = fn ## "_u8";
@@
- *(u8 *)fn(SKB, S) = C;
+ fn2(SKB, C);
Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18 21:48:17 +07:00
|
|
|
chcr_req = __skb_put_zero(skb, transhdr_len);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
temp = (op_type == CHCR_ENCRYPT_OP) ? 0 : authsize;
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Input order is AAD,IV and Payload. where IV should be included as
|
|
|
|
* the part of authdata. All other fields should be filled according
|
|
|
|
* to the hardware spec
|
|
|
|
*/
|
|
|
|
chcr_req->sec_cpl.op_ivinsrtofst =
|
2017-10-08 15:07:23 +07:00
|
|
|
FILL_SEC_CPL_OP_IVINSR(a_ctx(tfm)->dev->rx_channel_id, 2,
|
|
|
|
assoclen + 1);
|
|
|
|
chcr_req->sec_cpl.pldlen = htonl(assoclen + IV + req->cryptlen);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
|
|
|
|
assoclen ? 1 : 0, assoclen,
|
2017-10-08 15:07:23 +07:00
|
|
|
assoclen + IV + 1,
|
|
|
|
(temp & 0x1F0) >> 4);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.cipherstop_lo_authinsert = FILL_SEC_CPL_AUTHINSERT(
|
2017-10-08 15:07:23 +07:00
|
|
|
temp & 0xF,
|
|
|
|
null ? 0 : assoclen + IV + 1,
|
|
|
|
temp, temp);
|
2018-01-11 18:15:51 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA)
|
|
|
|
temp = CHCR_SCMD_CIPHER_MODE_AES_CTR;
|
|
|
|
else
|
|
|
|
temp = CHCR_SCMD_CIPHER_MODE_AES_CBC;
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.seqno_numivs = FILL_SEC_CPL_SCMD0_SEQNO(op_type,
|
|
|
|
(op_type == CHCR_ENCRYPT_OP) ? 1 : 0,
|
2018-01-11 18:15:51 +07:00
|
|
|
temp,
|
2016-11-29 20:30:43 +07:00
|
|
|
actx->auth_mode, aeadctx->hmac_ctrl,
|
2017-10-08 15:07:23 +07:00
|
|
|
IV >> 1);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 1,
|
2017-10-08 15:07:23 +07:00
|
|
|
0, 0, dst_size);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
chcr_req->key_ctx.ctx_hdr = aeadctx->key_ctx_hdr;
|
2018-01-11 18:15:51 +07:00
|
|
|
if (op_type == CHCR_ENCRYPT_OP ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL)
|
2016-11-29 20:30:43 +07:00
|
|
|
memcpy(chcr_req->key_ctx.key, aeadctx->key,
|
|
|
|
aeadctx->enckey_len);
|
|
|
|
else
|
|
|
|
memcpy(chcr_req->key_ctx.key, actx->dec_rrkey,
|
|
|
|
aeadctx->enckey_len);
|
|
|
|
|
|
|
|
memcpy(chcr_req->key_ctx.key + (DIV_ROUND_UP(aeadctx->enckey_len, 16) <<
|
|
|
|
4), actx->h_iopad, kctx_len -
|
|
|
|
(DIV_ROUND_UP(aeadctx->enckey_len, 16) << 4));
|
2018-01-11 18:15:51 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
|
|
|
|
memcpy(reqctx->iv, aeadctx->nonce, CTR_RFC3686_NONCE_SIZE);
|
|
|
|
memcpy(reqctx->iv + CTR_RFC3686_NONCE_SIZE, req->iv,
|
|
|
|
CTR_RFC3686_IV_SIZE);
|
|
|
|
*(__be32 *)(reqctx->iv + CTR_RFC3686_NONCE_SIZE +
|
|
|
|
CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
|
|
|
|
} else {
|
|
|
|
memcpy(reqctx->iv, req->iv, IV);
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)(chcr_req + 1) + kctx_len);
|
2017-10-08 15:07:23 +07:00
|
|
|
ulptx = (struct ulptx_sgl *)((u8 *)(phys_cpl + 1) + dst_size);
|
|
|
|
chcr_add_aead_dst_ent(req, phys_cpl, assoclen, op_type, qid);
|
|
|
|
chcr_add_aead_src_ent(req, ulptx, assoclen, op_type);
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.cipher_rqst);
|
2017-10-08 15:07:23 +07:00
|
|
|
temp = sizeof(struct cpl_rx_phys_dsgl) + dst_size +
|
|
|
|
kctx_len + (reqctx->imm ? (assoclen + IV + req->cryptlen) : 0);
|
|
|
|
create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, size,
|
|
|
|
transhdr_len, temp, 0);
|
2016-11-29 20:30:43 +07:00
|
|
|
reqctx->skb = skb;
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->op = op_type;
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
return skb;
|
|
|
|
err:
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req,
|
|
|
|
op_type);
|
|
|
|
|
2017-06-15 14:13:41 +07:00
|
|
|
return ERR_PTR(error);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
int chcr_aead_dma_map(struct device *dev,
|
|
|
|
struct aead_request *req,
|
|
|
|
unsigned short op_type)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
int error;
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
|
|
|
int dst_size;
|
|
|
|
|
|
|
|
dst_size = req->assoclen + req->cryptlen + (op_type ?
|
|
|
|
-authsize : authsize);
|
|
|
|
if (!req->cryptlen || !dst_size)
|
|
|
|
return 0;
|
|
|
|
reqctx->iv_dma = dma_map_single(dev, reqctx->iv, IV,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dev, reqctx->iv_dma))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
error = dma_map_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (!error)
|
|
|
|
goto err;
|
|
|
|
} else {
|
|
|
|
error = dma_map_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (!error)
|
|
|
|
goto err;
|
|
|
|
error = dma_map_sg(dev, req->dst, sg_nents(req->dst),
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
if (!error) {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
dma_unmap_single(dev, reqctx->iv_dma, IV, DMA_BIDIRECTIONAL);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_aead_dma_unmap(struct device *dev,
|
|
|
|
struct aead_request *req,
|
|
|
|
unsigned short op_type)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
|
|
|
int dst_size;
|
|
|
|
|
|
|
|
dst_size = req->assoclen + req->cryptlen + (op_type ?
|
|
|
|
-authsize : authsize);
|
|
|
|
if (!req->cryptlen || !dst_size)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dma_unmap_single(dev, reqctx->iv_dma, IV,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
} else {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
dma_unmap_sg(dev, req->dst, sg_nents(req->dst),
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_add_aead_src_ent(struct aead_request *req,
|
|
|
|
struct ulptx_sgl *ulptx,
|
|
|
|
unsigned int assoclen,
|
|
|
|
unsigned short op_type)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct ulptx_walk ulp_walk;
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
|
|
|
|
if (reqctx->imm) {
|
|
|
|
u8 *buf = (u8 *)ulptx;
|
|
|
|
|
|
|
|
if (reqctx->b0_dma) {
|
|
|
|
memcpy(buf, reqctx->scratch_pad, reqctx->b0_len);
|
|
|
|
buf += reqctx->b0_len;
|
|
|
|
}
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src),
|
|
|
|
buf, assoclen, 0);
|
|
|
|
buf += assoclen;
|
|
|
|
memcpy(buf, reqctx->iv, IV);
|
|
|
|
buf += IV;
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src),
|
|
|
|
buf, req->cryptlen, req->assoclen);
|
|
|
|
} else {
|
|
|
|
ulptx_walk_init(&ulp_walk, ulptx);
|
|
|
|
if (reqctx->b0_dma)
|
|
|
|
ulptx_walk_add_page(&ulp_walk, reqctx->b0_len,
|
|
|
|
&reqctx->b0_dma);
|
|
|
|
ulptx_walk_add_sg(&ulp_walk, req->src, assoclen, 0);
|
|
|
|
ulptx_walk_add_page(&ulp_walk, IV, &reqctx->iv_dma);
|
|
|
|
ulptx_walk_add_sg(&ulp_walk, req->src, req->cryptlen,
|
|
|
|
req->assoclen);
|
|
|
|
ulptx_walk_end(&ulp_walk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_add_aead_dst_ent(struct aead_request *req,
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl,
|
|
|
|
unsigned int assoclen,
|
|
|
|
unsigned short op_type,
|
|
|
|
unsigned short qid)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
struct dsgl_walk dsgl_walk;
|
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
|
|
|
u32 temp;
|
|
|
|
|
|
|
|
dsgl_walk_init(&dsgl_walk, phys_cpl);
|
|
|
|
if (reqctx->b0_dma)
|
|
|
|
dsgl_walk_add_page(&dsgl_walk, reqctx->b0_len, &reqctx->b0_dma);
|
|
|
|
dsgl_walk_add_sg(&dsgl_walk, req->dst, assoclen, 0);
|
|
|
|
dsgl_walk_add_page(&dsgl_walk, IV, &reqctx->iv_dma);
|
|
|
|
temp = req->cryptlen + (op_type ? -authsize : authsize);
|
|
|
|
dsgl_walk_add_sg(&dsgl_walk, req->dst, temp, req->assoclen);
|
|
|
|
dsgl_walk_end(&dsgl_walk, qid);
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_add_cipher_src_ent(struct ablkcipher_request *req,
|
|
|
|
struct ulptx_sgl *ulptx,
|
|
|
|
struct cipher_wr_param *wrparam)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct ulptx_walk ulp_walk;
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
|
|
|
|
if (reqctx->imm) {
|
|
|
|
u8 *buf = (u8 *)ulptx;
|
|
|
|
|
|
|
|
memcpy(buf, reqctx->iv, IV);
|
|
|
|
buf += IV;
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src),
|
|
|
|
buf, wrparam->bytes, reqctx->processed);
|
|
|
|
} else {
|
|
|
|
ulptx_walk_init(&ulp_walk, ulptx);
|
|
|
|
ulptx_walk_add_page(&ulp_walk, IV, &reqctx->iv_dma);
|
|
|
|
ulptx_walk_add_sg(&ulp_walk, reqctx->srcsg, wrparam->bytes,
|
|
|
|
reqctx->src_ofst);
|
|
|
|
reqctx->srcsg = ulp_walk.last_sg;
|
|
|
|
reqctx->src_ofst = ulp_walk.last_sg_len;
|
|
|
|
ulptx_walk_end(&ulp_walk);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_add_cipher_dst_ent(struct ablkcipher_request *req,
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl,
|
|
|
|
struct cipher_wr_param *wrparam,
|
|
|
|
unsigned short qid)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
struct dsgl_walk dsgl_walk;
|
|
|
|
|
|
|
|
dsgl_walk_init(&dsgl_walk, phys_cpl);
|
|
|
|
dsgl_walk_add_page(&dsgl_walk, IV, &reqctx->iv_dma);
|
|
|
|
dsgl_walk_add_sg(&dsgl_walk, reqctx->dstsg, wrparam->bytes,
|
|
|
|
reqctx->dst_ofst);
|
|
|
|
reqctx->dstsg = dsgl_walk.last_sg;
|
|
|
|
reqctx->dst_ofst = dsgl_walk.last_sg_len;
|
|
|
|
|
|
|
|
dsgl_walk_end(&dsgl_walk, qid);
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_add_hash_src_ent(struct ahash_request *req,
|
|
|
|
struct ulptx_sgl *ulptx,
|
|
|
|
struct hash_wr_param *param)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct ulptx_walk ulp_walk;
|
|
|
|
struct chcr_ahash_req_ctx *reqctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (reqctx->imm) {
|
|
|
|
u8 *buf = (u8 *)ulptx;
|
|
|
|
|
|
|
|
if (param->bfr_len) {
|
|
|
|
memcpy(buf, reqctx->reqbfr, param->bfr_len);
|
|
|
|
buf += param->bfr_len;
|
|
|
|
}
|
|
|
|
sg_pcopy_to_buffer(req->src, sg_nents(req->src),
|
|
|
|
buf, param->sg_len, 0);
|
|
|
|
} else {
|
|
|
|
ulptx_walk_init(&ulp_walk, ulptx);
|
|
|
|
if (param->bfr_len)
|
|
|
|
ulptx_walk_add_page(&ulp_walk, param->bfr_len,
|
|
|
|
&reqctx->dma_addr);
|
|
|
|
ulptx_walk_add_sg(&ulp_walk, req->src, param->sg_len,
|
2018-01-11 18:15:48 +07:00
|
|
|
0);
|
|
|
|
ulptx_walk_end(&ulp_walk);
|
2017-10-08 15:07:23 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
int chcr_hash_dma_map(struct device *dev,
|
|
|
|
struct ahash_request *req)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
int error = 0;
|
|
|
|
|
|
|
|
if (!req->nbytes)
|
|
|
|
return 0;
|
|
|
|
error = dma_map_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (!error)
|
2017-11-10 04:25:43 +07:00
|
|
|
return -ENOMEM;
|
2017-10-08 15:07:23 +07:00
|
|
|
req_ctx->is_sg_map = 1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
void chcr_hash_dma_unmap(struct device *dev,
|
|
|
|
struct ahash_request *req)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_ahash_req_ctx *req_ctx = ahash_request_ctx(req);
|
|
|
|
|
|
|
|
if (!req->nbytes)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
req_ctx->is_sg_map = 0;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2017-11-16 18:27:08 +07:00
|
|
|
int chcr_cipher_dma_map(struct device *dev,
|
|
|
|
struct ablkcipher_request *req)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
int error;
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
|
|
|
|
reqctx->iv_dma = dma_map_single(dev, reqctx->iv, IV,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(dev, reqctx->iv_dma))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
error = dma_map_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (!error)
|
|
|
|
goto err;
|
|
|
|
} else {
|
|
|
|
error = dma_map_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (!error)
|
|
|
|
goto err;
|
|
|
|
error = dma_map_sg(dev, req->dst, sg_nents(req->dst),
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
if (!error) {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
err:
|
|
|
|
dma_unmap_single(dev, reqctx->iv_dma, IV, DMA_BIDIRECTIONAL);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2017-11-16 18:27:08 +07:00
|
|
|
|
|
|
|
void chcr_cipher_dma_unmap(struct device *dev,
|
|
|
|
struct ablkcipher_request *req)
|
2017-10-08 15:07:23 +07:00
|
|
|
{
|
|
|
|
struct chcr_blkcipher_req_ctx *reqctx = ablkcipher_request_ctx(req);
|
|
|
|
|
|
|
|
dma_unmap_single(dev, reqctx->iv_dma, IV,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (req->src == req->dst) {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
} else {
|
|
|
|
dma_unmap_sg(dev, req->src, sg_nents(req->src),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
dma_unmap_sg(dev, req->dst, sg_nents(req->dst),
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
static int set_msg_len(u8 *block, unsigned int msglen, int csize)
|
|
|
|
{
|
|
|
|
__be32 data;
|
|
|
|
|
|
|
|
memset(block, 0, csize);
|
|
|
|
block += csize;
|
|
|
|
|
|
|
|
if (csize >= 4)
|
|
|
|
csize = 4;
|
|
|
|
else if (msglen > (unsigned int)(1 << (8 * csize)))
|
|
|
|
return -EOVERFLOW;
|
|
|
|
|
|
|
|
data = cpu_to_be32(msglen);
|
|
|
|
memcpy(block - csize, (u8 *)&data + 4 - csize, csize);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void generate_b0(struct aead_request *req,
|
|
|
|
struct chcr_aead_ctx *aeadctx,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
unsigned int l, lp, m;
|
|
|
|
int rc;
|
|
|
|
struct crypto_aead *aead = crypto_aead_reqtfm(req);
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
u8 *b0 = reqctx->scratch_pad;
|
|
|
|
|
|
|
|
m = crypto_aead_authsize(aead);
|
|
|
|
|
|
|
|
memcpy(b0, reqctx->iv, 16);
|
|
|
|
|
|
|
|
lp = b0[0];
|
|
|
|
l = lp + 1;
|
|
|
|
|
|
|
|
/* set m, bits 3-5 */
|
|
|
|
*b0 |= (8 * ((m - 2) / 2));
|
|
|
|
|
|
|
|
/* set adata, bit 6, if associated data is used */
|
|
|
|
if (req->assoclen)
|
|
|
|
*b0 |= 64;
|
|
|
|
rc = set_msg_len(b0 + 16 - l,
|
|
|
|
(op_type == CHCR_DECRYPT_OP) ?
|
|
|
|
req->cryptlen - m : req->cryptlen, l);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int crypto_ccm_check_iv(const u8 *iv)
|
|
|
|
{
|
|
|
|
/* 2 <= L <= 8, so 1 <= L' <= 7. */
|
|
|
|
if (iv[0] < 1 || iv[0] > 7)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ccm_format_packet(struct aead_request *req,
|
|
|
|
struct chcr_aead_ctx *aeadctx,
|
|
|
|
unsigned int sub_type,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
if (sub_type == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309) {
|
|
|
|
reqctx->iv[0] = 3;
|
|
|
|
memcpy(reqctx->iv + 1, &aeadctx->salt[0], 3);
|
|
|
|
memcpy(reqctx->iv + 4, req->iv, 8);
|
|
|
|
memset(reqctx->iv + 12, 0, 4);
|
|
|
|
*((unsigned short *)(reqctx->scratch_pad + 16)) =
|
|
|
|
htons(req->assoclen - 8);
|
|
|
|
} else {
|
|
|
|
memcpy(reqctx->iv, req->iv, 16);
|
|
|
|
*((unsigned short *)(reqctx->scratch_pad + 16)) =
|
|
|
|
htons(req->assoclen);
|
|
|
|
}
|
|
|
|
generate_b0(req, aeadctx, op_type);
|
|
|
|
/* zero the ctr value */
|
|
|
|
memset(reqctx->iv + 15 - reqctx->iv[0], 0, reqctx->iv[0] + 1);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void fill_sec_cpl_for_aead(struct cpl_tx_sec_pdu *sec_cpl,
|
|
|
|
unsigned int dst_size,
|
|
|
|
struct aead_request *req,
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned short op_type)
|
2016-11-29 20:30:43 +07:00
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CCM;
|
|
|
|
unsigned int mac_mode = CHCR_SCMD_AUTH_MODE_CBCMAC;
|
2017-10-08 15:07:23 +07:00
|
|
|
unsigned int c_id = a_ctx(tfm)->dev->rx_channel_id;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int ccm_xtra;
|
|
|
|
unsigned char tag_offset = 0, auth_offset = 0;
|
|
|
|
unsigned int assoclen;
|
|
|
|
|
|
|
|
if (get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309)
|
|
|
|
assoclen = req->assoclen - 8;
|
|
|
|
else
|
|
|
|
assoclen = req->assoclen;
|
|
|
|
ccm_xtra = CCM_B0_SIZE +
|
|
|
|
((assoclen) ? CCM_AAD_FIELD_SIZE : 0);
|
|
|
|
|
|
|
|
auth_offset = req->cryptlen ?
|
2017-10-08 15:07:23 +07:00
|
|
|
(assoclen + IV + 1 + ccm_xtra) : 0;
|
2016-11-29 20:30:43 +07:00
|
|
|
if (op_type == CHCR_DECRYPT_OP) {
|
|
|
|
if (crypto_aead_authsize(tfm) != req->cryptlen)
|
|
|
|
tag_offset = crypto_aead_authsize(tfm);
|
|
|
|
else
|
|
|
|
auth_offset = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
sec_cpl->op_ivinsrtofst = FILL_SEC_CPL_OP_IVINSR(c_id,
|
2017-10-08 15:07:23 +07:00
|
|
|
2, assoclen + 1 + ccm_xtra);
|
2016-11-29 20:30:43 +07:00
|
|
|
sec_cpl->pldlen =
|
2017-10-08 15:07:23 +07:00
|
|
|
htonl(assoclen + IV + req->cryptlen + ccm_xtra);
|
2016-11-29 20:30:43 +07:00
|
|
|
/* For CCM there wil be b0 always. So AAD start will be 1 always */
|
|
|
|
sec_cpl->aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
|
|
|
|
1, assoclen + ccm_xtra, assoclen
|
2017-10-08 15:07:23 +07:00
|
|
|
+ IV + 1 + ccm_xtra, 0);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
sec_cpl->cipherstop_lo_authinsert = FILL_SEC_CPL_AUTHINSERT(0,
|
|
|
|
auth_offset, tag_offset,
|
|
|
|
(op_type == CHCR_ENCRYPT_OP) ? 0 :
|
|
|
|
crypto_aead_authsize(tfm));
|
|
|
|
sec_cpl->seqno_numivs = FILL_SEC_CPL_SCMD0_SEQNO(op_type,
|
|
|
|
(op_type == CHCR_ENCRYPT_OP) ? 0 : 1,
|
2017-04-10 19:53:59 +07:00
|
|
|
cipher_mode, mac_mode,
|
2017-10-08 15:07:23 +07:00
|
|
|
aeadctx->hmac_ctrl, IV >> 1);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
sec_cpl->ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 1, 0,
|
2017-10-08 15:07:23 +07:00
|
|
|
0, dst_size);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
int aead_ccm_validate_input(unsigned short op_type,
|
|
|
|
struct aead_request *req,
|
|
|
|
struct chcr_aead_ctx *aeadctx,
|
|
|
|
unsigned int sub_type)
|
|
|
|
{
|
|
|
|
if (sub_type != CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309) {
|
|
|
|
if (crypto_ccm_check_iv(req->iv)) {
|
|
|
|
pr_err("CCM: IV check fails\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (req->assoclen != 16 && req->assoclen != 20) {
|
|
|
|
pr_err("RFC4309: Invalid AAD length %d\n",
|
|
|
|
req->assoclen);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct sk_buff *create_aead_ccm_wr(struct aead_request *req,
|
|
|
|
unsigned short qid,
|
|
|
|
int size,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct sk_buff *skb = NULL;
|
|
|
|
struct chcr_wr *chcr_req;
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ulptx_sgl *ulptx;
|
|
|
|
unsigned int transhdr_len;
|
|
|
|
unsigned int dst_size = 0, kctx_len, dnents, temp;
|
|
|
|
unsigned int sub_type, assoclen = req->assoclen;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
2017-10-08 15:07:23 +07:00
|
|
|
int error = -EINVAL;
|
2016-11-29 20:30:43 +07:00
|
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
|
|
|
|
GFP_ATOMIC;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct adapter *adap = padap(a_ctx(tfm)->dev);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->b0_dma = 0;
|
|
|
|
sub_type = get_aead_subtype(tfm);
|
|
|
|
if (sub_type == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309)
|
|
|
|
assoclen -= 8;
|
|
|
|
dst_size = assoclen + req->cryptlen + (op_type ? -authsize :
|
2017-06-15 14:13:46 +07:00
|
|
|
authsize);
|
2017-10-08 15:07:23 +07:00
|
|
|
error = chcr_aead_common_init(req, op_type);
|
|
|
|
if (error)
|
|
|
|
return ERR_PTR(error);
|
2017-04-10 19:54:01 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
|
|
|
|
reqctx->b0_len = CCM_B0_SIZE + (assoclen ? CCM_AAD_FIELD_SIZE : 0);
|
2017-06-15 14:13:41 +07:00
|
|
|
error = aead_ccm_validate_input(op_type, req, aeadctx, sub_type);
|
|
|
|
if (error)
|
2016-11-29 20:30:43 +07:00
|
|
|
goto err;
|
2017-10-08 15:07:23 +07:00
|
|
|
if (dst_size) {
|
|
|
|
dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
|
|
|
|
dnents += sg_nents_xlen(req->dst, req->cryptlen
|
|
|
|
+ (op_type ? -authsize : authsize),
|
|
|
|
CHCR_DST_SG_SIZE, req->assoclen);
|
|
|
|
dnents += MIN_CCM_SG; // For IV and B0
|
|
|
|
} else {
|
|
|
|
dnents = 0;
|
|
|
|
}
|
|
|
|
dst_size = get_space_for_phys_dsgl(dnents);
|
2016-11-29 20:30:43 +07:00
|
|
|
kctx_len = ((DIV_ROUND_UP(aeadctx->enckey_len, 16)) << 4) * 2;
|
|
|
|
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dst_size);
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->imm = (transhdr_len + assoclen + IV + req->cryptlen +
|
|
|
|
reqctx->b0_len) <= SGE_MAX_WR_LEN;
|
|
|
|
temp = reqctx->imm ? (DIV_ROUND_UP((assoclen + IV + req->cryptlen +
|
|
|
|
reqctx->b0_len), 16) * 16) :
|
|
|
|
(sgl_len(reqctx->src_nents + reqctx->aad_nents +
|
|
|
|
MIN_CCM_SG) * 8);
|
|
|
|
transhdr_len += temp;
|
|
|
|
transhdr_len = DIV_ROUND_UP(transhdr_len, 16) * 16;
|
|
|
|
|
|
|
|
if (chcr_aead_need_fallback(req, dnents, T6_MAX_AAD_SIZE -
|
|
|
|
reqctx->b0_len, transhdr_len, op_type)) {
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.fallback);
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req,
|
|
|
|
op_type);
|
2017-04-10 19:54:01 +07:00
|
|
|
return ERR_PTR(chcr_aead_fallback(req, op_type));
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
skb = alloc_skb(SGE_MAX_WR_LEN, flags);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-06-15 14:13:41 +07:00
|
|
|
if (!skb) {
|
|
|
|
error = -ENOMEM;
|
2016-11-29 20:30:43 +07:00
|
|
|
goto err;
|
2017-06-15 14:13:41 +07:00
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_req = (struct chcr_wr *) __skb_put_zero(skb, transhdr_len);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
fill_sec_cpl_for_aead(&chcr_req->sec_cpl, dst_size, req, op_type);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
chcr_req->key_ctx.ctx_hdr = aeadctx->key_ctx_hdr;
|
|
|
|
memcpy(chcr_req->key_ctx.key, aeadctx->key, aeadctx->enckey_len);
|
|
|
|
memcpy(chcr_req->key_ctx.key + (DIV_ROUND_UP(aeadctx->enckey_len, 16) *
|
|
|
|
16), aeadctx->key, aeadctx->enckey_len);
|
|
|
|
|
|
|
|
phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)(chcr_req + 1) + kctx_len);
|
2017-10-08 15:07:23 +07:00
|
|
|
ulptx = (struct ulptx_sgl *)((u8 *)(phys_cpl + 1) + dst_size);
|
2017-06-15 14:13:41 +07:00
|
|
|
error = ccm_format_packet(req, aeadctx, sub_type, op_type);
|
|
|
|
if (error)
|
2016-11-29 20:30:43 +07:00
|
|
|
goto dstmap_fail;
|
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->b0_dma = dma_map_single(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
&reqctx->scratch_pad, reqctx->b0_len,
|
|
|
|
DMA_BIDIRECTIONAL);
|
|
|
|
if (dma_mapping_error(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev,
|
|
|
|
reqctx->b0_dma)) {
|
|
|
|
error = -ENOMEM;
|
2016-11-29 20:30:43 +07:00
|
|
|
goto dstmap_fail;
|
2017-10-08 15:07:23 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
chcr_add_aead_dst_ent(req, phys_cpl, assoclen, op_type, qid);
|
|
|
|
chcr_add_aead_src_ent(req, ulptx, assoclen, op_type);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.aead_rqst);
|
2017-10-08 15:07:23 +07:00
|
|
|
temp = sizeof(struct cpl_rx_phys_dsgl) + dst_size +
|
|
|
|
kctx_len + (reqctx->imm ? (assoclen + IV + req->cryptlen +
|
|
|
|
reqctx->b0_len) : 0);
|
|
|
|
create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, 0,
|
|
|
|
transhdr_len, temp, 0);
|
2016-11-29 20:30:43 +07:00
|
|
|
reqctx->skb = skb;
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->op = op_type;
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
return skb;
|
|
|
|
dstmap_fail:
|
|
|
|
kfree_skb(skb);
|
|
|
|
err:
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req, op_type);
|
2017-06-15 14:13:41 +07:00
|
|
|
return ERR_PTR(error);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct sk_buff *create_gcm_wr(struct aead_request *req,
|
|
|
|
unsigned short qid,
|
|
|
|
int size,
|
|
|
|
unsigned short op_type)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
struct sk_buff *skb = NULL;
|
|
|
|
struct chcr_wr *chcr_req;
|
|
|
|
struct cpl_rx_phys_dsgl *phys_cpl;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct ulptx_sgl *ulptx;
|
|
|
|
unsigned int transhdr_len, dnents = 0;
|
|
|
|
unsigned int dst_size = 0, temp = 0, kctx_len, assoclen = req->assoclen;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int authsize = crypto_aead_authsize(tfm);
|
2017-10-08 15:07:23 +07:00
|
|
|
int error = -EINVAL;
|
2016-11-29 20:30:43 +07:00
|
|
|
gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
|
|
|
|
GFP_ATOMIC;
|
2017-10-08 15:07:23 +07:00
|
|
|
struct adapter *adap = padap(a_ctx(tfm)->dev);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
if (get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106)
|
|
|
|
assoclen = req->assoclen - 8;
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->b0_dma = 0;
|
|
|
|
dst_size = assoclen + req->cryptlen + (op_type ? -authsize : authsize);
|
|
|
|
error = chcr_aead_common_init(req, op_type);
|
2017-06-15 14:13:41 +07:00
|
|
|
if (error)
|
|
|
|
return ERR_PTR(error);
|
2017-10-08 15:07:23 +07:00
|
|
|
if (dst_size) {
|
|
|
|
dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
|
|
|
|
dnents += sg_nents_xlen(req->dst,
|
|
|
|
req->cryptlen + (op_type ? -authsize : authsize),
|
|
|
|
CHCR_DST_SG_SIZE, req->assoclen);
|
|
|
|
dnents += MIN_GCM_SG; // For IV
|
|
|
|
} else {
|
|
|
|
dnents = 0;
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
dst_size = get_space_for_phys_dsgl(dnents);
|
2016-11-29 20:30:43 +07:00
|
|
|
kctx_len = ((DIV_ROUND_UP(aeadctx->enckey_len, 16)) << 4) +
|
|
|
|
AEAD_H_SIZE;
|
|
|
|
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dst_size);
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->imm = (transhdr_len + assoclen + IV + req->cryptlen) <=
|
|
|
|
SGE_MAX_WR_LEN;
|
|
|
|
temp = reqctx->imm ? (DIV_ROUND_UP((assoclen + IV +
|
|
|
|
req->cryptlen), 16) * 16) : (sgl_len(reqctx->src_nents +
|
|
|
|
reqctx->aad_nents + MIN_GCM_SG) * 8);
|
|
|
|
transhdr_len += temp;
|
|
|
|
transhdr_len = DIV_ROUND_UP(transhdr_len, 16) * 16;
|
|
|
|
if (chcr_aead_need_fallback(req, dnents, T6_MAX_AAD_SIZE,
|
|
|
|
transhdr_len, op_type)) {
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.fallback);
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req,
|
|
|
|
op_type);
|
2017-04-10 19:54:01 +07:00
|
|
|
return ERR_PTR(chcr_aead_fallback(req, op_type));
|
|
|
|
}
|
2017-10-08 15:07:23 +07:00
|
|
|
skb = alloc_skb(SGE_MAX_WR_LEN, flags);
|
2017-06-15 14:13:41 +07:00
|
|
|
if (!skb) {
|
|
|
|
error = -ENOMEM;
|
2016-11-29 20:30:43 +07:00
|
|
|
goto err;
|
2017-06-15 14:13:41 +07:00
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
|
net: introduce __skb_put_[zero, data, u8]
follow Johannes Berg, semantic patch file as below,
@@
identifier p, p2;
expression len;
expression skb;
type t, t2;
@@
(
-p = __skb_put(skb, len);
+p = __skb_put_zero(skb, len);
|
-p = (t)__skb_put(skb, len);
+p = __skb_put_zero(skb, len);
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, len);
|
-memset(p, 0, len);
)
@@
identifier p;
expression len;
expression skb;
type t;
@@
(
-t p = __skb_put(skb, len);
+t p = __skb_put_zero(skb, len);
)
... when != p
(
-memset(p, 0, len);
)
@@
type t, t2;
identifier p, p2;
expression skb;
@@
t *p;
...
(
-p = __skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
|
-p = (t *)__skb_put(skb, sizeof(t));
+p = __skb_put_zero(skb, sizeof(t));
)
... when != p
(
p2 = (t2)p;
-memset(p2, 0, sizeof(*p));
|
-memset(p, 0, sizeof(*p));
)
@@
expression skb, len;
@@
-memset(__skb_put(skb, len), 0, len);
+__skb_put_zero(skb, len);
@@
expression skb, len, data;
@@
-memcpy(__skb_put(skb, len), data, len);
+__skb_put_data(skb, data, len);
@@
expression SKB, C, S;
typedef u8;
identifier fn = {__skb_put};
fresh identifier fn2 = fn ## "_u8";
@@
- *(u8 *)fn(SKB, S) = C;
+ fn2(SKB, C);
Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-18 21:48:17 +07:00
|
|
|
chcr_req = __skb_put_zero(skb, transhdr_len);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
//Offset of tag from end
|
|
|
|
temp = (op_type == CHCR_ENCRYPT_OP) ? 0 : authsize;
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.op_ivinsrtofst = FILL_SEC_CPL_OP_IVINSR(
|
2017-10-08 15:07:23 +07:00
|
|
|
a_ctx(tfm)->dev->rx_channel_id, 2,
|
|
|
|
(assoclen + 1));
|
2017-04-10 19:54:01 +07:00
|
|
|
chcr_req->sec_cpl.pldlen =
|
2017-10-08 15:07:23 +07:00
|
|
|
htonl(assoclen + IV + req->cryptlen);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
|
2017-06-15 14:13:42 +07:00
|
|
|
assoclen ? 1 : 0, assoclen,
|
2017-10-08 15:07:23 +07:00
|
|
|
assoclen + IV + 1, 0);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.cipherstop_lo_authinsert =
|
2017-10-08 15:07:23 +07:00
|
|
|
FILL_SEC_CPL_AUTHINSERT(0, assoclen + IV + 1,
|
|
|
|
temp, temp);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.seqno_numivs =
|
|
|
|
FILL_SEC_CPL_SCMD0_SEQNO(op_type, (op_type ==
|
|
|
|
CHCR_ENCRYPT_OP) ? 1 : 0,
|
|
|
|
CHCR_SCMD_CIPHER_MODE_AES_GCM,
|
2017-04-10 19:53:59 +07:00
|
|
|
CHCR_SCMD_AUTH_MODE_GHASH,
|
2017-10-08 15:07:23 +07:00
|
|
|
aeadctx->hmac_ctrl, IV >> 1);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->sec_cpl.ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 1,
|
2017-10-08 15:07:23 +07:00
|
|
|
0, 0, dst_size);
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_req->key_ctx.ctx_hdr = aeadctx->key_ctx_hdr;
|
|
|
|
memcpy(chcr_req->key_ctx.key, aeadctx->key, aeadctx->enckey_len);
|
|
|
|
memcpy(chcr_req->key_ctx.key + (DIV_ROUND_UP(aeadctx->enckey_len, 16) *
|
|
|
|
16), GCM_CTX(aeadctx)->ghash_h, AEAD_H_SIZE);
|
|
|
|
|
|
|
|
/* prepare a 16 byte iv */
|
|
|
|
/* S A L T | IV | 0x00000001 */
|
|
|
|
if (get_aead_subtype(tfm) ==
|
|
|
|
CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106) {
|
|
|
|
memcpy(reqctx->iv, aeadctx->salt, 4);
|
2017-08-22 15:08:15 +07:00
|
|
|
memcpy(reqctx->iv + 4, req->iv, GCM_RFC4106_IV_SIZE);
|
2016-11-29 20:30:43 +07:00
|
|
|
} else {
|
2017-08-22 15:08:15 +07:00
|
|
|
memcpy(reqctx->iv, req->iv, GCM_AES_IV_SIZE);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
*((unsigned int *)(reqctx->iv + 12)) = htonl(0x01);
|
|
|
|
|
|
|
|
phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)(chcr_req + 1) + kctx_len);
|
2017-10-08 15:07:23 +07:00
|
|
|
ulptx = (struct ulptx_sgl *)((u8 *)(phys_cpl + 1) + dst_size);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_add_aead_dst_ent(req, phys_cpl, assoclen, op_type, qid);
|
|
|
|
chcr_add_aead_src_ent(req, ulptx, assoclen, op_type);
|
2017-06-15 14:13:44 +07:00
|
|
|
atomic_inc(&adap->chcr_stats.aead_rqst);
|
2017-10-08 15:07:23 +07:00
|
|
|
temp = sizeof(struct cpl_rx_phys_dsgl) + dst_size +
|
|
|
|
kctx_len + (reqctx->imm ? (assoclen + IV + req->cryptlen) : 0);
|
|
|
|
create_wreq(a_ctx(tfm), chcr_req, &req->base, reqctx->imm, size,
|
|
|
|
transhdr_len, temp, reqctx->verify);
|
2016-11-29 20:30:43 +07:00
|
|
|
reqctx->skb = skb;
|
2017-10-08 15:07:23 +07:00
|
|
|
reqctx->op = op_type;
|
2016-11-29 20:30:43 +07:00
|
|
|
return skb;
|
|
|
|
|
|
|
|
err:
|
2017-10-08 15:07:23 +07:00
|
|
|
chcr_aead_dma_unmap(&ULD_CTX(a_ctx(tfm))->lldi.pdev->dev, req, op_type);
|
2017-06-15 14:13:41 +07:00
|
|
|
return ERR_PTR(error);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int chcr_aead_cra_init(struct crypto_aead *tfm)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2017-04-10 19:54:01 +07:00
|
|
|
struct aead_alg *alg = crypto_aead_alg(tfm);
|
|
|
|
|
|
|
|
aeadctx->sw_cipher = crypto_alloc_aead(alg->base.cra_name, 0,
|
2017-06-15 14:13:41 +07:00
|
|
|
CRYPTO_ALG_NEED_FALLBACK |
|
|
|
|
CRYPTO_ALG_ASYNC);
|
2017-04-10 19:54:01 +07:00
|
|
|
if (IS_ERR(aeadctx->sw_cipher))
|
|
|
|
return PTR_ERR(aeadctx->sw_cipher);
|
|
|
|
crypto_aead_set_reqsize(tfm, max(sizeof(struct chcr_aead_reqctx),
|
|
|
|
sizeof(struct aead_request) +
|
|
|
|
crypto_aead_reqsize(aeadctx->sw_cipher)));
|
2017-10-08 15:07:23 +07:00
|
|
|
return chcr_device_init(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void chcr_aead_cra_exit(struct crypto_aead *tfm)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2017-04-10 19:54:01 +07:00
|
|
|
|
|
|
|
crypto_free_aead(aeadctx->sw_cipher);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_authenc_null_setauthsize(struct crypto_aead *tfm,
|
|
|
|
unsigned int authsize)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NOP;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
2017-04-10 19:54:01 +07:00
|
|
|
return crypto_aead_setauthsize(aeadctx->sw_cipher, authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
static int chcr_authenc_setauthsize(struct crypto_aead *tfm,
|
|
|
|
unsigned int authsize)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
u32 maxauth = crypto_aead_maxauthsize(tfm);
|
|
|
|
|
|
|
|
/*SHA1 authsize in ipsec is 12 instead of 10 i.e maxauthsize / 2 is not
|
|
|
|
* true for sha1. authsize == 12 condition should be before
|
|
|
|
* authsize == (maxauth >> 1)
|
|
|
|
*/
|
|
|
|
if (authsize == ICV_4) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL1;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == ICV_6) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == ICV_10) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == ICV_12) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == ICV_14) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL3;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == (maxauth >> 1)) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_DIV2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else if (authsize == maxauth) {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
} else {
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_SW;
|
|
|
|
}
|
2017-04-10 19:54:01 +07:00
|
|
|
return crypto_aead_setauthsize(aeadctx->sw_cipher, authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int chcr_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
switch (authsize) {
|
|
|
|
case ICV_4:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL1;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_8:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_DIV2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_12:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_14:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL3;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_16:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_13:
|
|
|
|
case ICV_15:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_SW;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *) tfm,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-04-10 19:54:01 +07:00
|
|
|
return crypto_aead_setauthsize(aeadctx->sw_cipher, authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_4106_4309_setauthsize(struct crypto_aead *tfm,
|
|
|
|
unsigned int authsize)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
switch (authsize) {
|
|
|
|
case ICV_8:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_DIV2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_12:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_16:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *)tfm,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-04-10 19:54:01 +07:00
|
|
|
return crypto_aead_setauthsize(aeadctx->sw_cipher, authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_ccm_setauthsize(struct crypto_aead *tfm,
|
|
|
|
unsigned int authsize)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
switch (authsize) {
|
|
|
|
case ICV_4:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL1;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_6:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_8:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_DIV2;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_10:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_12:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_14:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_PL3;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
case ICV_16:
|
|
|
|
aeadctx->hmac_ctrl = CHCR_SCMD_HMAC_CTRL_NO_TRUNC;
|
|
|
|
aeadctx->mayverify = VERIFY_HW;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *)tfm,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-04-10 19:54:01 +07:00
|
|
|
return crypto_aead_setauthsize(aeadctx->sw_cipher, authsize);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
static int chcr_ccm_common_setkey(struct crypto_aead *aead,
|
2016-11-29 20:30:43 +07:00
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(aead));
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned char ck_size, mk_size;
|
|
|
|
int key_ctx_size = 0;
|
|
|
|
|
|
|
|
key_ctx_size = sizeof(struct _key_ctx) +
|
|
|
|
((DIV_ROUND_UP(keylen, 16)) << 4) * 2;
|
|
|
|
if (keylen == AES_KEYSIZE_128) {
|
|
|
|
mk_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
} else if (keylen == AES_KEYSIZE_192) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
|
|
|
|
mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_192;
|
|
|
|
} else if (keylen == AES_KEYSIZE_256) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
|
|
|
|
mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256;
|
|
|
|
} else {
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *)aead,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
aeadctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, mk_size, 0, 0,
|
|
|
|
key_ctx_size >> 4);
|
2017-04-10 19:54:01 +07:00
|
|
|
memcpy(aeadctx->key, key, keylen);
|
|
|
|
aeadctx->enckey_len = keylen;
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
static int chcr_aead_ccm_setkey(struct crypto_aead *aead,
|
|
|
|
const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(aead));
|
2017-04-10 19:54:01 +07:00
|
|
|
int error;
|
|
|
|
|
|
|
|
crypto_aead_clear_flags(aeadctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_aead_set_flags(aeadctx->sw_cipher, crypto_aead_get_flags(aead) &
|
|
|
|
CRYPTO_TFM_REQ_MASK);
|
|
|
|
error = crypto_aead_setkey(aeadctx->sw_cipher, key, keylen);
|
|
|
|
crypto_aead_clear_flags(aead, CRYPTO_TFM_RES_MASK);
|
|
|
|
crypto_aead_set_flags(aead, crypto_aead_get_flags(aeadctx->sw_cipher) &
|
|
|
|
CRYPTO_TFM_RES_MASK);
|
|
|
|
if (error)
|
|
|
|
return error;
|
|
|
|
return chcr_ccm_common_setkey(aead, key, keylen);
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
static int chcr_aead_rfc4309_setkey(struct crypto_aead *aead, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(aead));
|
2017-06-15 14:13:40 +07:00
|
|
|
int error;
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
if (keylen < 3) {
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *)aead,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-06-15 14:13:40 +07:00
|
|
|
crypto_aead_clear_flags(aeadctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_aead_set_flags(aeadctx->sw_cipher, crypto_aead_get_flags(aead) &
|
|
|
|
CRYPTO_TFM_REQ_MASK);
|
|
|
|
error = crypto_aead_setkey(aeadctx->sw_cipher, key, keylen);
|
|
|
|
crypto_aead_clear_flags(aead, CRYPTO_TFM_RES_MASK);
|
|
|
|
crypto_aead_set_flags(aead, crypto_aead_get_flags(aeadctx->sw_cipher) &
|
|
|
|
CRYPTO_TFM_RES_MASK);
|
|
|
|
if (error)
|
|
|
|
return error;
|
2016-11-29 20:30:43 +07:00
|
|
|
keylen -= 3;
|
|
|
|
memcpy(aeadctx->salt, key + keylen, 3);
|
2017-04-10 19:54:01 +07:00
|
|
|
return chcr_ccm_common_setkey(aead, key, keylen);
|
2016-11-29 20:30:43 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_gcm_setkey(struct crypto_aead *aead, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(aead));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_gcm_ctx *gctx = GCM_CTX(aeadctx);
|
2017-01-27 17:39:08 +07:00
|
|
|
struct crypto_cipher *cipher;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int ck_size;
|
|
|
|
int ret = 0, key_ctx_size = 0;
|
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
crypto_aead_clear_flags(aeadctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_aead_set_flags(aeadctx->sw_cipher, crypto_aead_get_flags(aead)
|
|
|
|
& CRYPTO_TFM_REQ_MASK);
|
|
|
|
ret = crypto_aead_setkey(aeadctx->sw_cipher, key, keylen);
|
|
|
|
crypto_aead_clear_flags(aead, CRYPTO_TFM_RES_MASK);
|
|
|
|
crypto_aead_set_flags(aead, crypto_aead_get_flags(aeadctx->sw_cipher) &
|
|
|
|
CRYPTO_TFM_RES_MASK);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
2017-01-27 17:39:06 +07:00
|
|
|
if (get_aead_subtype(aead) == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106 &&
|
|
|
|
keylen > 3) {
|
2016-11-29 20:30:43 +07:00
|
|
|
keylen -= 4; /* nonce/salt is present in the last 4 bytes */
|
|
|
|
memcpy(aeadctx->salt, key + keylen, 4);
|
|
|
|
}
|
|
|
|
if (keylen == AES_KEYSIZE_128) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
} else if (keylen == AES_KEYSIZE_192) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
|
|
|
|
} else if (keylen == AES_KEYSIZE_256) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
|
|
|
|
} else {
|
|
|
|
crypto_tfm_set_flags((struct crypto_tfm *)aead,
|
|
|
|
CRYPTO_TFM_RES_BAD_KEY_LEN);
|
2017-04-10 19:54:01 +07:00
|
|
|
pr_err("GCM: Invalid key length %d\n", keylen);
|
2016-11-29 20:30:43 +07:00
|
|
|
ret = -EINVAL;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(aeadctx->key, key, keylen);
|
|
|
|
aeadctx->enckey_len = keylen;
|
|
|
|
key_ctx_size = sizeof(struct _key_ctx) +
|
|
|
|
((DIV_ROUND_UP(keylen, 16)) << 4) +
|
|
|
|
AEAD_H_SIZE;
|
|
|
|
aeadctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size,
|
|
|
|
CHCR_KEYCTX_MAC_KEY_SIZE_128,
|
|
|
|
0, 0,
|
|
|
|
key_ctx_size >> 4);
|
2017-01-27 17:39:08 +07:00
|
|
|
/* Calculate the H = CIPH(K, 0 repeated 16 times).
|
|
|
|
* It will go in key context
|
2016-11-29 20:30:43 +07:00
|
|
|
*/
|
2017-01-27 17:39:08 +07:00
|
|
|
cipher = crypto_alloc_cipher("aes-generic", 0, 0);
|
|
|
|
if (IS_ERR(cipher)) {
|
2016-11-29 20:30:43 +07:00
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto out;
|
|
|
|
}
|
2017-01-27 17:39:08 +07:00
|
|
|
|
|
|
|
ret = crypto_cipher_setkey(cipher, key, keylen);
|
2016-11-29 20:30:43 +07:00
|
|
|
if (ret) {
|
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
goto out1;
|
|
|
|
}
|
|
|
|
memset(gctx->ghash_h, 0, AEAD_H_SIZE);
|
2017-01-27 17:39:08 +07:00
|
|
|
crypto_cipher_encrypt_one(cipher, gctx->ghash_h, gctx->ghash_h);
|
2016-11-29 20:30:43 +07:00
|
|
|
|
|
|
|
out1:
|
2017-01-27 17:39:08 +07:00
|
|
|
crypto_free_cipher(cipher);
|
2016-11-29 20:30:43 +07:00
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_authenc_setkey(struct crypto_aead *authenc, const u8 *key,
|
|
|
|
unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(authenc));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_authenc_ctx *actx = AUTHENC_CTX(aeadctx);
|
|
|
|
/* it contains auth and cipher key both*/
|
|
|
|
struct crypto_authenc_keys keys;
|
2018-01-11 18:15:51 +07:00
|
|
|
unsigned int bs, subtype;
|
2016-11-29 20:30:43 +07:00
|
|
|
unsigned int max_authsize = crypto_aead_alg(authenc)->maxauthsize;
|
|
|
|
int err = 0, i, key_ctx_len = 0;
|
|
|
|
unsigned char ck_size = 0;
|
|
|
|
unsigned char pad[CHCR_HASH_MAX_BLOCK_SIZE_128] = { 0 };
|
2017-04-14 01:25:15 +07:00
|
|
|
struct crypto_shash *base_hash = ERR_PTR(-EINVAL);
|
2016-11-29 20:30:43 +07:00
|
|
|
struct algo_param param;
|
|
|
|
int align;
|
|
|
|
u8 *o_ptr = NULL;
|
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
crypto_aead_clear_flags(aeadctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_aead_set_flags(aeadctx->sw_cipher, crypto_aead_get_flags(authenc)
|
|
|
|
& CRYPTO_TFM_REQ_MASK);
|
|
|
|
err = crypto_aead_setkey(aeadctx->sw_cipher, key, keylen);
|
|
|
|
crypto_aead_clear_flags(authenc, CRYPTO_TFM_RES_MASK);
|
|
|
|
crypto_aead_set_flags(authenc, crypto_aead_get_flags(aeadctx->sw_cipher)
|
|
|
|
& CRYPTO_TFM_RES_MASK);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) {
|
|
|
|
crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (get_alg_config(¶m, max_authsize)) {
|
|
|
|
pr_err("chcr : Unsupported digest size\n");
|
|
|
|
goto out;
|
|
|
|
}
|
2018-01-11 18:15:51 +07:00
|
|
|
subtype = get_aead_subtype(authenc);
|
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
|
|
|
|
if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
|
|
|
|
goto out;
|
|
|
|
memcpy(aeadctx->nonce, keys.enckey + (keys.enckeylen
|
|
|
|
- CTR_RFC3686_NONCE_SIZE), CTR_RFC3686_NONCE_SIZE);
|
|
|
|
keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
if (keys.enckeylen == AES_KEYSIZE_128) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
} else if (keys.enckeylen == AES_KEYSIZE_192) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
|
|
|
|
} else if (keys.enckeylen == AES_KEYSIZE_256) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
|
|
|
|
} else {
|
|
|
|
pr_err("chcr : Unsupported cipher key\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy only encryption key. We use authkey to generate h(ipad) and
|
|
|
|
* h(opad) so authkey is not needed again. authkeylen size have the
|
|
|
|
* size of the hash digest size.
|
|
|
|
*/
|
|
|
|
memcpy(aeadctx->key, keys.enckey, keys.enckeylen);
|
|
|
|
aeadctx->enckey_len = keys.enckeylen;
|
2018-01-11 18:15:51 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CBC_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CBC_NULL) {
|
2016-11-29 20:30:43 +07:00
|
|
|
|
2018-01-11 18:15:51 +07:00
|
|
|
get_aes_decrypt_key(actx->dec_rrkey, aeadctx->key,
|
|
|
|
aeadctx->enckey_len << 3);
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
base_hash = chcr_alloc_shash(max_authsize);
|
|
|
|
if (IS_ERR(base_hash)) {
|
|
|
|
pr_err("chcr : Base driver cannot be loaded\n");
|
2017-04-10 19:54:01 +07:00
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
return -EINVAL;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
{
|
|
|
|
SHASH_DESC_ON_STACK(shash, base_hash);
|
|
|
|
shash->tfm = base_hash;
|
|
|
|
shash->flags = crypto_shash_get_flags(base_hash);
|
|
|
|
bs = crypto_shash_blocksize(base_hash);
|
|
|
|
align = KEYCTX_ALIGN_PAD(max_authsize);
|
|
|
|
o_ptr = actx->h_iopad + param.result_size + align;
|
|
|
|
|
|
|
|
if (keys.authkeylen > bs) {
|
|
|
|
err = crypto_shash_digest(shash, keys.authkey,
|
|
|
|
keys.authkeylen,
|
|
|
|
o_ptr);
|
|
|
|
if (err) {
|
|
|
|
pr_err("chcr : Base driver cannot be loaded\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
keys.authkeylen = max_authsize;
|
|
|
|
} else
|
|
|
|
memcpy(o_ptr, keys.authkey, keys.authkeylen);
|
|
|
|
|
|
|
|
/* Compute the ipad-digest*/
|
|
|
|
memset(pad + keys.authkeylen, 0, bs - keys.authkeylen);
|
|
|
|
memcpy(pad, o_ptr, keys.authkeylen);
|
|
|
|
for (i = 0; i < bs >> 2; i++)
|
|
|
|
*((unsigned int *)pad + i) ^= IPAD_DATA;
|
|
|
|
|
|
|
|
if (chcr_compute_partial_hash(shash, pad, actx->h_iopad,
|
|
|
|
max_authsize))
|
|
|
|
goto out;
|
|
|
|
/* Compute the opad-digest */
|
|
|
|
memset(pad + keys.authkeylen, 0, bs - keys.authkeylen);
|
|
|
|
memcpy(pad, o_ptr, keys.authkeylen);
|
|
|
|
for (i = 0; i < bs >> 2; i++)
|
|
|
|
*((unsigned int *)pad + i) ^= OPAD_DATA;
|
|
|
|
|
|
|
|
if (chcr_compute_partial_hash(shash, pad, o_ptr, max_authsize))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
/* convert the ipad and opad digest to network order */
|
|
|
|
chcr_change_order(actx->h_iopad, param.result_size);
|
|
|
|
chcr_change_order(o_ptr, param.result_size);
|
|
|
|
key_ctx_len = sizeof(struct _key_ctx) +
|
|
|
|
((DIV_ROUND_UP(keys.enckeylen, 16)) << 4) +
|
|
|
|
(param.result_size + align) * 2;
|
|
|
|
aeadctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, param.mk_size,
|
|
|
|
0, 1, key_ctx_len >> 4);
|
|
|
|
actx->auth_mode = param.auth_mode;
|
|
|
|
chcr_free_shash(base_hash);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
aeadctx->enckey_len = 0;
|
2017-04-14 01:25:15 +07:00
|
|
|
if (!IS_ERR(base_hash))
|
2016-11-29 20:30:43 +07:00
|
|
|
chcr_free_shash(base_hash);
|
|
|
|
return -EINVAL;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
static int chcr_aead_digest_null_setkey(struct crypto_aead *authenc,
|
|
|
|
const u8 *key, unsigned int keylen)
|
|
|
|
{
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(authenc));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_authenc_ctx *actx = AUTHENC_CTX(aeadctx);
|
|
|
|
struct crypto_authenc_keys keys;
|
2017-04-10 19:54:01 +07:00
|
|
|
int err;
|
2016-11-29 20:30:43 +07:00
|
|
|
/* it contains auth and cipher key both*/
|
2018-01-11 18:15:51 +07:00
|
|
|
unsigned int subtype;
|
2016-11-29 20:30:43 +07:00
|
|
|
int key_ctx_len = 0;
|
|
|
|
unsigned char ck_size = 0;
|
|
|
|
|
2017-04-10 19:54:01 +07:00
|
|
|
crypto_aead_clear_flags(aeadctx->sw_cipher, CRYPTO_TFM_REQ_MASK);
|
|
|
|
crypto_aead_set_flags(aeadctx->sw_cipher, crypto_aead_get_flags(authenc)
|
|
|
|
& CRYPTO_TFM_REQ_MASK);
|
|
|
|
err = crypto_aead_setkey(aeadctx->sw_cipher, key, keylen);
|
|
|
|
crypto_aead_clear_flags(authenc, CRYPTO_TFM_RES_MASK);
|
|
|
|
crypto_aead_set_flags(authenc, crypto_aead_get_flags(aeadctx->sw_cipher)
|
|
|
|
& CRYPTO_TFM_RES_MASK);
|
|
|
|
if (err)
|
|
|
|
goto out;
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) {
|
|
|
|
crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
|
|
|
|
goto out;
|
|
|
|
}
|
2018-01-11 18:15:51 +07:00
|
|
|
subtype = get_aead_subtype(authenc);
|
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
|
|
|
|
if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
|
|
|
|
goto out;
|
|
|
|
memcpy(aeadctx->nonce, keys.enckey + (keys.enckeylen
|
|
|
|
- CTR_RFC3686_NONCE_SIZE), CTR_RFC3686_NONCE_SIZE);
|
|
|
|
keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
if (keys.enckeylen == AES_KEYSIZE_128) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128;
|
|
|
|
} else if (keys.enckeylen == AES_KEYSIZE_192) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192;
|
|
|
|
} else if (keys.enckeylen == AES_KEYSIZE_256) {
|
|
|
|
ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256;
|
|
|
|
} else {
|
2018-01-11 18:15:51 +07:00
|
|
|
pr_err("chcr : Unsupported cipher key %d\n", keys.enckeylen);
|
2016-11-29 20:30:43 +07:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
memcpy(aeadctx->key, keys.enckey, keys.enckeylen);
|
|
|
|
aeadctx->enckey_len = keys.enckeylen;
|
2018-01-11 18:15:51 +07:00
|
|
|
if (subtype == CRYPTO_ALG_SUB_TYPE_CBC_SHA ||
|
|
|
|
subtype == CRYPTO_ALG_SUB_TYPE_CBC_NULL) {
|
|
|
|
get_aes_decrypt_key(actx->dec_rrkey, aeadctx->key,
|
|
|
|
aeadctx->enckey_len << 3);
|
|
|
|
}
|
2016-11-29 20:30:43 +07:00
|
|
|
key_ctx_len = sizeof(struct _key_ctx)
|
|
|
|
+ ((DIV_ROUND_UP(keys.enckeylen, 16)) << 4);
|
|
|
|
|
|
|
|
aeadctx->key_ctx_hdr = FILL_KEY_CTX_HDR(ck_size, CHCR_KEYCTX_NO_KEY, 0,
|
|
|
|
0, key_ctx_len >> 4);
|
|
|
|
actx->auth_mode = CHCR_SCMD_AUTH_MODE_NOP;
|
|
|
|
return 0;
|
|
|
|
out:
|
|
|
|
aeadctx->enckey_len = 0;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2017-11-16 18:27:08 +07:00
|
|
|
|
|
|
|
static int chcr_aead_op(struct aead_request *req,
|
|
|
|
unsigned short op_type,
|
|
|
|
int size,
|
|
|
|
create_wr_t create_wr_fn)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
struct uld_ctx *u_ctx;
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
|
|
|
if (!a_ctx(tfm)->dev) {
|
|
|
|
pr_err("chcr : %s : No crypto device.\n", __func__);
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
|
|
|
u_ctx = ULD_CTX(a_ctx(tfm));
|
|
|
|
if (cxgb4_is_crypto_q_full(u_ctx->lldi.ports[0],
|
|
|
|
a_ctx(tfm)->tx_qidx)) {
|
|
|
|
if (!(req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Form a WR from req */
|
|
|
|
skb = create_wr_fn(req, u_ctx->lldi.rxq_ids[a_ctx(tfm)->rx_qidx], size,
|
|
|
|
op_type);
|
|
|
|
|
|
|
|
if (IS_ERR(skb) || !skb)
|
|
|
|
return PTR_ERR(skb);
|
|
|
|
|
|
|
|
skb->dev = u_ctx->lldi.ports[0];
|
|
|
|
set_wr_txq(skb, CPL_PRIORITY_DATA, a_ctx(tfm)->tx_qidx);
|
|
|
|
chcr_send_wr(skb);
|
|
|
|
return -EINPROGRESS;
|
|
|
|
}
|
|
|
|
|
2016-11-29 20:30:43 +07:00
|
|
|
static int chcr_aead_encrypt(struct aead_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
|
|
|
|
reqctx->verify = VERIFY_HW;
|
|
|
|
|
|
|
|
switch (get_aead_subtype(tfm)) {
|
2018-01-11 18:15:51 +07:00
|
|
|
case CRYPTO_ALG_SUB_TYPE_CTR_SHA:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CBC_SHA:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CBC_NULL:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CTR_NULL:
|
2016-11-29 20:30:43 +07:00
|
|
|
return chcr_aead_op(req, CHCR_ENCRYPT_OP, 0,
|
|
|
|
create_authenc_wr);
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_AEAD_CCM:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309:
|
|
|
|
return chcr_aead_op(req, CHCR_ENCRYPT_OP, 0,
|
|
|
|
create_aead_ccm_wr);
|
|
|
|
default:
|
|
|
|
return chcr_aead_op(req, CHCR_ENCRYPT_OP, 0,
|
|
|
|
create_gcm_wr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int chcr_aead_decrypt(struct aead_request *req)
|
|
|
|
{
|
|
|
|
struct crypto_aead *tfm = crypto_aead_reqtfm(req);
|
2017-10-08 15:07:23 +07:00
|
|
|
struct chcr_aead_ctx *aeadctx = AEAD_CTX(a_ctx(tfm));
|
2016-11-29 20:30:43 +07:00
|
|
|
struct chcr_aead_reqctx *reqctx = aead_request_ctx(req);
|
|
|
|
int size;
|
|
|
|
|
|
|
|
if (aeadctx->mayverify == VERIFY_SW) {
|
|
|
|
size = crypto_aead_maxauthsize(tfm);
|
|
|
|
reqctx->verify = VERIFY_SW;
|
|
|
|
} else {
|
|
|
|
size = 0;
|
|
|
|
reqctx->verify = VERIFY_HW;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (get_aead_subtype(tfm)) {
|
2018-01-11 18:15:51 +07:00
|
|
|
case CRYPTO_ALG_SUB_TYPE_CBC_SHA:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CTR_SHA:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CBC_NULL:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_CTR_NULL:
|
2016-11-29 20:30:43 +07:00
|
|
|
return chcr_aead_op(req, CHCR_DECRYPT_OP, size,
|
|
|
|
create_authenc_wr);
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_AEAD_CCM:
|
|
|
|
case CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309:
|
|
|
|
return chcr_aead_op(req, CHCR_DECRYPT_OP, size,
|
|
|
|
create_aead_ccm_wr);
|
|
|
|
default:
|
|
|
|
return chcr_aead_op(req, CHCR_DECRYPT_OP, size,
|
|
|
|
create_gcm_wr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
static struct chcr_alg_template driver_algs[] = {
|
|
|
|
/* AES-CBC */
|
|
|
|
{
|
2017-06-15 14:13:43 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_SUB_TYPE_CBC,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.crypto = {
|
|
|
|
.cra_name = "cbc(aes)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "cbc-aes-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_init = chcr_cra_init,
|
2017-06-15 14:13:43 +07:00
|
|
|
.cra_exit = chcr_cra_exit,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_u.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.setkey = chcr_aes_cbc_setkey,
|
|
|
|
.encrypt = chcr_aes_encrypt,
|
|
|
|
.decrypt = chcr_aes_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2017-06-15 14:13:43 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_SUB_TYPE_XTS,
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.crypto = {
|
|
|
|
.cra_name = "xts(aes)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "xts-aes-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
|
|
.cra_init = chcr_cra_init,
|
|
|
|
.cra_exit = NULL,
|
2017-06-15 14:13:43 +07:00
|
|
|
.cra_u .ablkcipher = {
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.min_keysize = 2 * AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = 2 * AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.setkey = chcr_aes_xts_setkey,
|
|
|
|
.encrypt = chcr_aes_encrypt,
|
|
|
|
.decrypt = chcr_aes_decrypt,
|
|
|
|
}
|
|
|
|
}
|
2017-06-15 14:13:43 +07:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_SUB_TYPE_CTR,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.crypto = {
|
|
|
|
.cra_name = "ctr(aes)",
|
|
|
|
.cra_driver_name = "ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_init = chcr_cra_init,
|
|
|
|
.cra_exit = chcr_cra_exit,
|
|
|
|
.cra_u.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.setkey = chcr_aes_ctr_setkey,
|
|
|
|
.encrypt = chcr_aes_encrypt,
|
|
|
|
.decrypt = chcr_aes_decrypt,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
|
|
CRYPTO_ALG_SUB_TYPE_CTR_RFC3686,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.crypto = {
|
|
|
|
.cra_name = "rfc3686(ctr(aes))",
|
|
|
|
.cra_driver_name = "rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_init = chcr_rfc3686_init,
|
|
|
|
.cra_exit = chcr_cra_exit,
|
|
|
|
.cra_u.ablkcipher = {
|
|
|
|
.min_keysize = AES_MIN_KEY_SIZE +
|
|
|
|
CTR_RFC3686_NONCE_SIZE,
|
|
|
|
.max_keysize = AES_MAX_KEY_SIZE +
|
|
|
|
CTR_RFC3686_NONCE_SIZE,
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.setkey = chcr_aes_rfc3686_setkey,
|
|
|
|
.encrypt = chcr_aes_encrypt,
|
|
|
|
.decrypt = chcr_aes_decrypt,
|
|
|
|
.geniv = "seqiv",
|
|
|
|
}
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
}
|
|
|
|
},
|
|
|
|
/* SHA */
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha1",
|
|
|
|
.cra_driver_name = "sha1-chcr",
|
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha256",
|
|
|
|
.cra_driver_name = "sha256-chcr",
|
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha224",
|
|
|
|
.cra_driver_name = "sha224-chcr",
|
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA384_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha384",
|
|
|
|
.cra_driver_name = "sha384-chcr",
|
|
|
|
.cra_blocksize = SHA384_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA512_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "sha512",
|
|
|
|
.cra_driver_name = "sha512-chcr",
|
|
|
|
.cra_blocksize = SHA512_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
/* HMAC */
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_HMAC,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA1_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha1)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "hmac-sha1-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = SHA1_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_HMAC,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA224_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha224)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "hmac-sha224-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = SHA224_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_HMAC,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA256_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha256)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "hmac-sha256-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = SHA256_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_HMAC,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA384_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha384)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "hmac-sha384-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = SHA384_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_HMAC,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.hash = {
|
|
|
|
.halg.digestsize = SHA512_DIGEST_SIZE,
|
|
|
|
.halg.base = {
|
|
|
|
.cra_name = "hmac(sha512)",
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_driver_name = "hmac-sha512-chcr",
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
.cra_blocksize = SHA512_BLOCK_SIZE,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
},
|
2016-11-29 20:30:43 +07:00
|
|
|
/* Add AEAD Algorithms */
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_AEAD_GCM,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "gcm(aes)",
|
|
|
|
.cra_driver_name = "gcm-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_gcm_ctx),
|
|
|
|
},
|
2017-08-22 15:08:15 +07:00
|
|
|
.ivsize = GCM_AES_IV_SIZE,
|
2016-11-29 20:30:43 +07:00
|
|
|
.maxauthsize = GHASH_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_gcm_setkey,
|
|
|
|
.setauthsize = chcr_gcm_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_AEAD_RFC4106,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "rfc4106(gcm(aes))",
|
|
|
|
.cra_driver_name = "rfc4106-gcm-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY + 1,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_gcm_ctx),
|
|
|
|
|
|
|
|
},
|
2017-08-22 15:08:15 +07:00
|
|
|
.ivsize = GCM_RFC4106_IV_SIZE,
|
2016-11-29 20:30:43 +07:00
|
|
|
.maxauthsize = GHASH_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_gcm_setkey,
|
|
|
|
.setauthsize = chcr_4106_4309_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_AEAD_CCM,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "ccm(aes)",
|
|
|
|
.cra_driver_name = "ccm-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = GHASH_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_aead_ccm_setkey,
|
|
|
|
.setauthsize = chcr_ccm_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "rfc4309(ccm(aes))",
|
|
|
|
.cra_driver_name = "rfc4309-ccm-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY + 1,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = 8,
|
|
|
|
.maxauthsize = GHASH_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_aead_rfc4309_setkey,
|
|
|
|
.setauthsize = chcr_4106_4309_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_SHA,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha1),cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha1-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_SHA,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
|
|
|
|
.cra_name = "authenc(hmac(sha256),cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha256-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA256_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_SHA,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha224),cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha224-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA224_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_SHA,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha384),cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha384-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA384_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_SHA,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha512),cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha512-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = SHA512_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
2018-01-11 18:15:51 +07:00
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CBC_NULL,
|
2016-11-29 20:30:43 +07:00
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(digest_null,cbc(aes))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-digest_null-cbc-aes-chcr",
|
|
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
2017-04-10 19:53:58 +07:00
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
2016-11-29 20:30:43 +07:00
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
|
|
.maxauthsize = 0,
|
|
|
|
.setkey = chcr_aead_digest_null_setkey,
|
|
|
|
.setauthsize = chcr_authenc_null_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
2018-01-11 18:15:51 +07:00
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_SHA,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha1-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = SHA1_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_SHA,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
|
|
|
|
.cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha256-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = SHA256_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_SHA,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha224-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = SHA224_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_SHA,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha384),rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha384-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = SHA384_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_SHA,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(hmac(sha512),rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-hmac-sha512-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = SHA512_DIGEST_SIZE,
|
|
|
|
.setkey = chcr_authenc_setkey,
|
|
|
|
.setauthsize = chcr_authenc_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.type = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_SUB_TYPE_CTR_NULL,
|
|
|
|
.is_registered = 0,
|
|
|
|
.alg.aead = {
|
|
|
|
.base = {
|
|
|
|
.cra_name = "authenc(digest_null,rfc3686(ctr(aes)))",
|
|
|
|
.cra_driver_name =
|
|
|
|
"authenc-digest_null-rfc3686-ctr-aes-chcr",
|
|
|
|
.cra_blocksize = 1,
|
|
|
|
.cra_priority = CHCR_AEAD_PRIORITY,
|
|
|
|
.cra_ctxsize = sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct chcr_aead_ctx) +
|
|
|
|
sizeof(struct chcr_authenc_ctx),
|
|
|
|
|
|
|
|
},
|
|
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
|
|
.maxauthsize = 0,
|
|
|
|
.setkey = chcr_aead_digest_null_setkey,
|
|
|
|
.setauthsize = chcr_authenc_null_setauthsize,
|
|
|
|
}
|
|
|
|
},
|
|
|
|
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* chcr_unregister_alg - Deregister crypto algorithms with
|
|
|
|
* kernel framework.
|
|
|
|
*/
|
|
|
|
static int chcr_unregister_alg(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
|
|
|
|
switch (driver_algs[i].type & CRYPTO_ALG_TYPE_MASK) {
|
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
|
|
|
if (driver_algs[i].is_registered)
|
|
|
|
crypto_unregister_alg(
|
|
|
|
&driver_algs[i].alg.crypto);
|
|
|
|
break;
|
2016-11-29 20:30:43 +07:00
|
|
|
case CRYPTO_ALG_TYPE_AEAD:
|
|
|
|
if (driver_algs[i].is_registered)
|
|
|
|
crypto_unregister_aead(
|
|
|
|
&driver_algs[i].alg.aead);
|
|
|
|
break;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
if (driver_algs[i].is_registered)
|
|
|
|
crypto_unregister_ahash(
|
|
|
|
&driver_algs[i].alg.hash);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
driver_algs[i].is_registered = 0;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define SZ_AHASH_CTX sizeof(struct chcr_context)
|
|
|
|
#define SZ_AHASH_H_CTX (sizeof(struct chcr_context) + sizeof(struct hmac_ctx))
|
|
|
|
#define SZ_AHASH_REQ_CTX sizeof(struct chcr_ahash_req_ctx)
|
|
|
|
#define AHASH_CRA_FLAGS (CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_ASYNC)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* chcr_register_alg - Register crypto algorithms with kernel framework.
|
|
|
|
*/
|
|
|
|
static int chcr_register_alg(void)
|
|
|
|
{
|
|
|
|
struct crypto_alg ai;
|
|
|
|
struct ahash_alg *a_hash;
|
|
|
|
int err = 0, i;
|
|
|
|
char *name = NULL;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
|
|
|
|
if (driver_algs[i].is_registered)
|
|
|
|
continue;
|
|
|
|
switch (driver_algs[i].type & CRYPTO_ALG_TYPE_MASK) {
|
|
|
|
case CRYPTO_ALG_TYPE_ABLKCIPHER:
|
2017-06-15 14:13:43 +07:00
|
|
|
driver_algs[i].alg.crypto.cra_priority =
|
|
|
|
CHCR_CRA_PRIORITY;
|
|
|
|
driver_algs[i].alg.crypto.cra_module = THIS_MODULE;
|
|
|
|
driver_algs[i].alg.crypto.cra_flags =
|
|
|
|
CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK;
|
|
|
|
driver_algs[i].alg.crypto.cra_ctxsize =
|
|
|
|
sizeof(struct chcr_context) +
|
|
|
|
sizeof(struct ablk_ctx);
|
|
|
|
driver_algs[i].alg.crypto.cra_alignmask = 0;
|
|
|
|
driver_algs[i].alg.crypto.cra_type =
|
|
|
|
&crypto_ablkcipher_type;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
err = crypto_register_alg(&driver_algs[i].alg.crypto);
|
|
|
|
name = driver_algs[i].alg.crypto.cra_driver_name;
|
|
|
|
break;
|
2016-11-29 20:30:43 +07:00
|
|
|
case CRYPTO_ALG_TYPE_AEAD:
|
|
|
|
driver_algs[i].alg.aead.base.cra_flags =
|
2017-04-10 19:54:01 +07:00
|
|
|
CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC |
|
|
|
|
CRYPTO_ALG_NEED_FALLBACK;
|
2016-11-29 20:30:43 +07:00
|
|
|
driver_algs[i].alg.aead.encrypt = chcr_aead_encrypt;
|
|
|
|
driver_algs[i].alg.aead.decrypt = chcr_aead_decrypt;
|
|
|
|
driver_algs[i].alg.aead.init = chcr_aead_cra_init;
|
|
|
|
driver_algs[i].alg.aead.exit = chcr_aead_cra_exit;
|
|
|
|
driver_algs[i].alg.aead.base.cra_module = THIS_MODULE;
|
|
|
|
err = crypto_register_aead(&driver_algs[i].alg.aead);
|
|
|
|
name = driver_algs[i].alg.aead.base.cra_driver_name;
|
|
|
|
break;
|
chcr: Support for Chelsio's Crypto Hardware
The Chelsio's Crypto Hardware can perform the following operations:
SHA1, SHA224, SHA256, SHA384 and SHA512, HMAC(SHA1), HMAC(SHA224),
HMAC(SHA256), HMAC(SHA384), HAMC(SHA512), AES-128-CBC, AES-192-CBC,
AES-256-CBC, AES-128-XTS, AES-256-XTS
This patch implements the driver for above mentioned features. This
driver is an Upper Layer Driver which is attached to Chelsio's LLD
(cxgb4) and uses the queue allocated by the LLD for sending the crypto
requests to the Hardware and receiving the responses from it.
The crypto operations can be performed by Chelsio's hardware from the
userspace applications and/or from within the kernel space using the
kernel's crypto API.
The above mentioned crypto features have been tested using kernel's
tests mentioned in testmgr.h. They also have been tested from user
space using libkcapi and Openssl.
Signed-off-by: Atul Gupta <atul.gupta@chelsio.com>
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-08-17 14:03:05 +07:00
|
|
|
case CRYPTO_ALG_TYPE_AHASH:
|
|
|
|
a_hash = &driver_algs[i].alg.hash;
|
|
|
|
a_hash->update = chcr_ahash_update;
|
|
|
|
a_hash->final = chcr_ahash_final;
|
|
|
|
a_hash->finup = chcr_ahash_finup;
|
|
|
|
a_hash->digest = chcr_ahash_digest;
|
|
|
|
a_hash->export = chcr_ahash_export;
|
|
|
|
a_hash->import = chcr_ahash_import;
|
|
|
|
a_hash->halg.statesize = SZ_AHASH_REQ_CTX;
|
|
|
|
a_hash->halg.base.cra_priority = CHCR_CRA_PRIORITY;
|
|
|
|
a_hash->halg.base.cra_module = THIS_MODULE;
|
|
|
|
a_hash->halg.base.cra_flags = AHASH_CRA_FLAGS;
|
|
|
|
a_hash->halg.base.cra_alignmask = 0;
|
|
|
|
a_hash->halg.base.cra_exit = NULL;
|
|
|
|
a_hash->halg.base.cra_type = &crypto_ahash_type;
|
|
|
|
|
|
|
|
if (driver_algs[i].type == CRYPTO_ALG_TYPE_HMAC) {
|
|
|
|
a_hash->halg.base.cra_init = chcr_hmac_cra_init;
|
|
|
|
a_hash->halg.base.cra_exit = chcr_hmac_cra_exit;
|
|
|
|
a_hash->init = chcr_hmac_init;
|
|
|
|
a_hash->setkey = chcr_ahash_setkey;
|
|
|
|
a_hash->halg.base.cra_ctxsize = SZ_AHASH_H_CTX;
|
|
|
|
} else {
|
|
|
|
a_hash->init = chcr_sha_init;
|
|
|
|
a_hash->halg.base.cra_ctxsize = SZ_AHASH_CTX;
|
|
|
|
a_hash->halg.base.cra_init = chcr_sha_cra_init;
|
|
|
|
}
|
|
|
|
err = crypto_register_ahash(&driver_algs[i].alg.hash);
|
|
|
|
ai = driver_algs[i].alg.hash.halg.base;
|
|
|
|
name = ai.cra_driver_name;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (err) {
|
|
|
|
pr_err("chcr : %s : Algorithm registration failed\n",
|
|
|
|
name);
|
|
|
|
goto register_err;
|
|
|
|
} else {
|
|
|
|
driver_algs[i].is_registered = 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
register_err:
|
|
|
|
chcr_unregister_alg();
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* start_crypto - Register the crypto algorithms.
|
|
|
|
* This should called once when the first device comesup. After this
|
|
|
|
* kernel will start calling driver APIs for crypto operations.
|
|
|
|
*/
|
|
|
|
int start_crypto(void)
|
|
|
|
{
|
|
|
|
return chcr_register_alg();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* stop_crypto - Deregister all the crypto algorithms with kernel.
|
|
|
|
* This should be called once when the last device goes down. After this
|
|
|
|
* kernel will not call the driver API for crypto operations.
|
|
|
|
*/
|
|
|
|
int stop_crypto(void)
|
|
|
|
{
|
|
|
|
chcr_unregister_alg();
|
|
|
|
return 0;
|
|
|
|
}
|