2014-02-07 14:24:56 +07:00
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/*
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* Copyright 2013 Gateworks Corporation
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2014-09-09 13:07:28 +07:00
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#include <dt-bindings/gpio/gpio.h>
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2014-02-07 14:24:56 +07:00
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/ {
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/* these are used by bootloader for disabling nodes */
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aliases {
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led0 = &led0;
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led1 = &led1;
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nand = &gpmi;
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usb0 = &usbh1;
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usb1 = &usbotg;
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};
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chosen {
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bootargs = "console=ttymxc1,115200";
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};
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leds {
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compatible = "gpio-leds";
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2014-09-09 13:07:30 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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2014-02-07 14:24:56 +07:00
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led0: user1 {
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label = "user1";
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
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2014-02-07 14:24:56 +07:00
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default-state = "on";
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linux,default-trigger = "heartbeat";
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};
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led1: user2 {
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label = "user2";
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
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2014-02-07 14:24:56 +07:00
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default-state = "off";
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};
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};
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2018-01-24 20:22:14 +07:00
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memory@10000000 {
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2018-12-06 01:10:03 +07:00
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device_type = "memory";
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2014-02-07 14:24:56 +07:00
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reg = <0x10000000 0x20000000>;
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};
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pps {
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compatible = "pps-gpio";
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2014-09-09 13:07:30 +07:00
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pps>;
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2014-09-09 13:07:28 +07:00
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gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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2014-02-07 14:24:56 +07:00
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status = "okay";
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};
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2016-11-17 02:40:45 +07:00
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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2014-02-07 14:24:56 +07:00
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2016-11-17 02:40:45 +07:00
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reg_5p0v: regulator-5p0v {
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compatible = "regulator-fixed";
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regulator-name = "5P0V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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2014-02-07 14:24:56 +07:00
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2016-11-17 02:40:45 +07:00
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reg_usb_otg_vbus: regulator-usb-otg-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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2014-02-07 14:24:56 +07:00
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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2015-12-11 20:22:04 +07:00
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phy-mode = "rgmii-id";
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2014-09-09 13:07:28 +07:00
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phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
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2014-02-07 14:24:56 +07:00
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status = "okay";
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};
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand>;
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status = "okay";
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};
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2014-04-23 14:47:51 +07:00
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&hdmi {
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ddc-i2c-bus = <&i2c3>;
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status = "okay";
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};
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2014-02-07 14:24:56 +07:00
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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eeprom1: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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eeprom2: eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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eeprom3: eeprom@52 {
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compatible = "atmel,24c02";
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reg = <0x52>;
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pagesize = <16>;
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};
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eeprom4: eeprom@53 {
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compatible = "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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};
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gpio: pca9555@23 {
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compatible = "nxp,pca9555";
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reg = <0x23>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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rtc: ds1672@68 {
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compatible = "dallas,ds1672";
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reg = <0x68>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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2016-11-17 02:40:45 +07:00
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ltc3676: pmic@3c {
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compatible = "lltc,ltc3676";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
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regulators {
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/* VDD_SOC (1+R1/R2 = 1.635) */
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reg_vdd_soc: sw1 {
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regulator-name = "vddsoc";
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regulator-min-microvolt = <674400>;
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regulator-max-microvolt = <1308000>;
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lltc,fb-voltage-divider = <127000 200000>;
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regulator-ramp-delay = <7000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
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reg_1p8v: sw2 {
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regulator-name = "vdd1p8";
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regulator-min-microvolt = <1033310>;
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regulator-max-microvolt = <2004000>;
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lltc,fb-voltage-divider = <301000 200000>;
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regulator-ramp-delay = <7000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_ARM (1+R1/R2 = 1.635) */
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reg_vdd_arm: sw3 {
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regulator-name = "vddarm";
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regulator-min-microvolt = <674400>;
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regulator-max-microvolt = <1308000>;
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lltc,fb-voltage-divider = <127000 200000>;
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regulator-ramp-delay = <7000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_DDR (1+R1/R2 = 2.105) */
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reg_vdd_ddr: sw4 {
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regulator-name = "vddddr";
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regulator-min-microvolt = <868310>;
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regulator-max-microvolt = <1684000>;
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lltc,fb-voltage-divider = <221000 200000>;
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regulator-ramp-delay = <7000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
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reg_2p5v: ldo2 {
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regulator-name = "vdd2p5";
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regulator-min-microvolt = <2490375>;
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regulator-max-microvolt = <2490375>;
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lltc,fb-voltage-divider = <487000 200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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/* VDD_HIGH (1+R1/R2 = 4.17) */
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reg_3p0v: ldo4 {
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regulator-name = "vdd3p0";
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regulator-min-microvolt = <3023250>;
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regulator-max-microvolt = <3023250>;
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lltc,fb-voltage-divider = <634000 200000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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2014-02-07 14:24:56 +07:00
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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2017-06-19 22:00:10 +07:00
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adv7180: camera@20 {
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compatible = "adi,adv7180";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adv7180>;
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reg = <0x20>;
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powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio5>;
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
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port {
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adv7180_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <8>;
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};
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};
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};
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};
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&ipu1_csi0_from_ipu1_csi0_mux {
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bus-width = <8>;
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};
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&ipu1_csi0_mux_from_parallel_sensor {
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remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
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bus-width = <8>;
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};
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&ipu1_csi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_csi0>;
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2014-02-07 14:24:56 +07:00
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};
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2014-09-09 13:07:30 +07:00
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&pcie {
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2014-02-07 14:24:56 +07:00
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pinctrl-names = "default";
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2014-09-09 13:07:30 +07:00
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pinctrl-0 = <&pinctrl_pcie>;
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reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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2014-02-07 14:24:56 +07:00
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2015-11-20 03:02:03 +07:00
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
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status = "disabled";
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};
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&pwm3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
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status = "disabled";
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};
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&pwm4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
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status = "disabled";
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};
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2014-09-09 13:07:30 +07:00
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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2014-02-07 14:24:56 +07:00
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2014-09-09 13:07:30 +07:00
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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status = "okay";
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};
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|
|
&usbotg {
|
|
|
|
|
vbus-supply = <®_usb_otg_vbus>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
|
|
|
disable-over-current;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usbh1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-29 20:31:03 +07:00
|
|
|
&wdog1 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
|
|
|
fsl,ext-reset-output;
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-09 13:07:30 +07:00
|
|
|
&iomuxc {
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_adv7180: adv7180grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
2017-06-19 22:00:10 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_enet: enetgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
|
|
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
|
|
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
|
|
|
|
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-09-09 13:07:30 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
|
|
|
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
|
|
|
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
|
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_ipu1_csi0: ipu1csi0grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
|
|
|
|
|
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
2017-06-19 22:00:10 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pcie: pciegrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-09-09 13:07:30 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pmic: pmicgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
|
|
|
|
|
>;
|
|
|
|
|
};
|
2016-11-17 02:40:45 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pps: ppsgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-09-09 13:07:30 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pwm2: pwm2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2015-11-20 03:02:03 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pwm3: pwm3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2015-11-20 03:02:03 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_pwm4: pwm4grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2015-11-20 03:02:03 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_uart2: uart2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_uart3: uart3grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_uart5: uart5grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
|
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
2014-02-07 14:24:56 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
|
|
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
|
|
|
|
|
>;
|
|
|
|
|
};
|
2016-06-29 20:31:03 +07:00
|
|
|
|
2017-09-19 03:11:01 +07:00
|
|
|
pinctrl_wdog: wdoggrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
|
|
|
|
|
>;
|
2014-02-07 14:24:56 +07:00
|
|
|
};
|
|
|
|
|
};
|
