2014-06-18 19:53:49 +07:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright IBM Corp. 2007
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* Authors: Hollis Blanchard <hollisb@us.ibm.com>
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*/
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#include <linux/jiffies.h>
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#include <linux/hrtimer.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm_host.h>
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#include <linux/clockchips.h>
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#include <asm/reg.h>
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#include <asm/time.h>
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#include <asm/byteorder.h>
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#include <asm/kvm_ppc.h>
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#include <asm/disassemble.h>
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#include <asm/ppc-opcode.h>
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#include "timing.h"
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#include "trace.h"
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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#ifdef CONFIG_PPC_FPU
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static bool kvmppc_check_fp_disabled(struct kvm_vcpu *vcpu)
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{
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if (!(kvmppc_get_msr(vcpu) & MSR_FP)) {
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kvmppc_core_queue_fpunavail(vcpu);
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return true;
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}
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return false;
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}
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#endif /* CONFIG_PPC_FPU */
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#ifdef CONFIG_VSX
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static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)
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{
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if (!(kvmppc_get_msr(vcpu) & MSR_VSX)) {
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kvmppc_core_queue_vsx_unavail(vcpu);
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return true;
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}
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return false;
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}
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#endif /* CONFIG_VSX */
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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/*
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* XXX to do:
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* lfiwax, lfiwzx
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* vector loads and stores
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2014-06-18 19:53:49 +07:00
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*
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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* Instructions that trap when used on cache-inhibited mappings
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* are not emulated here: multiple and string instructions,
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* lq/stq, and the load-reserve/store-conditional instructions.
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2014-06-18 19:53:49 +07:00
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*/
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int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
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{
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struct kvm_run *run = vcpu->run;
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u32 inst;
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int ra, rs, rt;
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enum emulation_result emulated;
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int advance = 1;
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/* this default type might be overwritten by subcategories */
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kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
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2014-09-10 19:37:29 +07:00
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emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
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2014-06-18 19:53:49 +07:00
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if (emulated != EMULATE_DONE)
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return emulated;
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ra = get_ra(inst);
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rs = get_rs(inst);
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rt = get_rt(inst);
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KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
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/*
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* if mmio_vsx_tx_sx_enabled == 0, copy data between
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* VSR[0..31] and memory
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* if mmio_vsx_tx_sx_enabled == 1, copy data between
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* VSR[32..63] and memory
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*/
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vcpu->arch.mmio_vsx_tx_sx_enabled = get_tx_or_sx(inst);
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vcpu->arch.mmio_vsx_copy_nums = 0;
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vcpu->arch.mmio_vsx_offset = 0;
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vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_NONE;
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vcpu->arch.mmio_sp64_extend = 0;
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vcpu->arch.mmio_sign_extend = 0;
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2014-06-18 19:53:49 +07:00
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switch (get_op(inst)) {
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case 31:
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switch (get_xop(inst)) {
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case OP_31_XOP_LWZX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
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break;
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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case OP_31_XOP_LWZUX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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break;
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2014-06-18 19:53:49 +07:00
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case OP_31_XOP_LBZX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
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break;
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case OP_31_XOP_LBZUX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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break;
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2017-03-17 15:31:38 +07:00
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case OP_31_XOP_STDX:
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emulated = kvmppc_handle_store(run, vcpu,
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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kvmppc_get_gpr(vcpu, rs), 8, 1);
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break;
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case OP_31_XOP_STDUX:
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emulated = kvmppc_handle_store(run, vcpu,
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kvmppc_get_gpr(vcpu, rs), 8, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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2017-03-17 15:31:38 +07:00
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break;
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2014-06-18 19:53:49 +07:00
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case OP_31_XOP_STWX:
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emulated = kvmppc_handle_store(run, vcpu,
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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kvmppc_get_gpr(vcpu, rs), 4, 1);
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break;
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case OP_31_XOP_STWUX:
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emulated = kvmppc_handle_store(run, vcpu,
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kvmppc_get_gpr(vcpu, rs), 4, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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2014-06-18 19:53:49 +07:00
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break;
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case OP_31_XOP_STBX:
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emulated = kvmppc_handle_store(run, vcpu,
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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kvmppc_get_gpr(vcpu, rs), 1, 1);
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2014-06-18 19:53:49 +07:00
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break;
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case OP_31_XOP_STBUX:
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emulated = kvmppc_handle_store(run, vcpu,
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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kvmppc_get_gpr(vcpu, rs), 1, 1);
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2014-06-18 19:53:49 +07:00
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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break;
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case OP_31_XOP_LHAX:
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emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
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break;
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KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
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case OP_31_XOP_LHAUX:
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emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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break;
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2014-06-18 19:53:49 +07:00
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case OP_31_XOP_LHZX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
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break;
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case OP_31_XOP_LHZUX:
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emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
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kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
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break;
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case OP_31_XOP_STHX:
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emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 2, 1);
|
2014-06-18 19:53:49 +07:00
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break;
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case OP_31_XOP_STHUX:
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emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 2, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_DCBST:
|
|
|
|
case OP_31_XOP_DCBF:
|
|
|
|
case OP_31_XOP_DCBI:
|
|
|
|
/* Do nothing. The guest is performing dcbi because
|
|
|
|
* hardware DMA is not snooped by the dcache, but
|
|
|
|
* emulated DMA either goes through the dcache as
|
|
|
|
* normal writes, or the host kernel has handled dcache
|
|
|
|
* coherence. */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LWBRX:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STWBRX:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 4, 0);
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LHBRX:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STHBRX:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 2, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LDBRX:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STDBRX:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
kvmppc_get_gpr(vcpu, rs), 8, 0);
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
case OP_31_XOP_LDX:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LDUX:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LWAX:
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
case OP_31_XOP_LWAUX:
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
#ifdef CONFIG_PPC_FPU
|
|
|
|
case OP_31_XOP_LFSX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LFSUX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LFDX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LFDUX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
2017-03-23 07:55:16 +07:00
|
|
|
case OP_31_XOP_LFIWAX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LFIWZX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
case OP_31_XOP_STFSX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs), 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STFSUX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs), 4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STFDX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
VCPU_FPR(vcpu, rs), 8, 1);
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STFDUX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
VCPU_FPR(vcpu, rs), 8, 1);
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STFIWX:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
VCPU_FPR(vcpu, rs), 4, 1);
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
case OP_31_XOP_LXSDX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXSSPX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXSIWAX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 4, 1, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXSIWZX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXVD2X:
|
|
|
|
/*
|
|
|
|
* In this case, the official load/store process is like this:
|
|
|
|
* Step1, exit from vm by page fault isr, then kvm save vsr.
|
|
|
|
* Please see guest_exit_cont->store_fp_state->SAVE_32VSRS
|
|
|
|
* as reference.
|
|
|
|
*
|
|
|
|
* Step2, copy data between memory and VCPU
|
|
|
|
* Notice: for LXVD2X/STXVD2X/LXVW4X/STXVW4X, we use
|
|
|
|
* 2copies*8bytes or 4copies*4bytes
|
|
|
|
* to simulate one copy of 16bytes.
|
|
|
|
* Also there is an endian issue here, we should notice the
|
|
|
|
* layout of memory.
|
|
|
|
* Please see MARCO of LXVD2X_ROT/STXVD2X_ROT as more reference.
|
|
|
|
* If host is little-endian, kvm will call XXSWAPD for
|
|
|
|
* LXVD2X_ROT/STXVD2X_ROT.
|
|
|
|
* So, if host is little-endian,
|
|
|
|
* the postion of memeory should be swapped.
|
|
|
|
*
|
|
|
|
* Step3, return to guest, kvm reset register.
|
|
|
|
* Please see kvmppc_hv_entry->load_fp_state->REST_32VSRS
|
|
|
|
* as reference.
|
|
|
|
*/
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 2;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXVW4X:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 4;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 4, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_LXVDSX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type =
|
|
|
|
KVMPPC_VSX_COPY_DWORD_LOAD_DUMP;
|
|
|
|
emulated = kvmppc_handle_vsx_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_VSX|rt, 8, 1, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STXSDX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_store(run, vcpu,
|
|
|
|
rs, 8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STXSSPX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_vsx_store(run, vcpu,
|
|
|
|
rs, 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STXSIWX:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_offset = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 1;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
|
|
|
|
emulated = kvmppc_handle_vsx_store(run, vcpu,
|
|
|
|
rs, 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STXVD2X:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 2;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_DWORD;
|
|
|
|
emulated = kvmppc_handle_vsx_store(run, vcpu,
|
|
|
|
rs, 8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_31_XOP_STXVW4X:
|
|
|
|
if (kvmppc_check_vsx_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_vsx_copy_nums = 4;
|
|
|
|
vcpu->arch.mmio_vsx_copy_type = KVMPPC_VSX_COPY_WORD;
|
|
|
|
emulated = kvmppc_handle_vsx_store(run, vcpu,
|
|
|
|
rs, 4, 1);
|
|
|
|
break;
|
|
|
|
#endif /* CONFIG_VSX */
|
2014-06-18 19:53:49 +07:00
|
|
|
default:
|
|
|
|
emulated = EMULATE_FAIL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LWZ:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
#ifdef CONFIG_PPC_FPU
|
|
|
|
case OP_STFS:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs),
|
|
|
|
4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STFSU:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs),
|
|
|
|
4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STFD:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs),
|
|
|
|
8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STFDU:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
VCPU_FPR(vcpu, rs),
|
|
|
|
8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2014-06-18 19:53:49 +07:00
|
|
|
case OP_LD:
|
|
|
|
rt = get_rt(inst);
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
switch (inst & 3) {
|
|
|
|
case 0: /* ld */
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
|
|
|
|
break;
|
|
|
|
case 1: /* ldu */
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
case 2: /* lwa */
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu, rt, 4, 1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
emulated = EMULATE_FAIL;
|
|
|
|
}
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LWZU:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LBZ:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LBZU:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STW:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
kvmppc_get_gpr(vcpu, rs),
|
|
|
|
4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STD:
|
|
|
|
rs = get_rs(inst);
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
switch (inst & 3) {
|
|
|
|
case 0: /* std */
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
kvmppc_get_gpr(vcpu, rs), 8, 1);
|
|
|
|
break;
|
|
|
|
case 1: /* stdu */
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
|
|
|
kvmppc_get_gpr(vcpu, rs), 8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
emulated = EMULATE_FAIL;
|
|
|
|
}
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STWU:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 4, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STB:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 1, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STBU:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 1, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHZ:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHZU:
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHA:
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LHAU:
|
|
|
|
emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STH:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 2, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_STHU:
|
|
|
|
emulated = kvmppc_handle_store(run, vcpu,
|
KVM: PPC: Emulation for more integer loads and stores
This adds emulation for the following integer loads and stores,
thus enabling them to be used in a guest for accessing emulated
MMIO locations.
- lhaux
- lwaux
- lwzux
- ldu
- lwa
- stdux
- stwux
- stdu
- ldbrx
- stdbrx
Previously, most of these would cause an emulation failure exit to
userspace, though ldu and lwa got treated incorrectly as ld, and
stdu got treated incorrectly as std.
This also tidies up some of the formatting and updates the comment
listing instructions that still need to be implemented.
With this, all integer loads and stores that are defined in the Power
ISA v2.07 are emulated, except for those that are permitted to trap
when used on cache-inhibited or write-through mappings (and which do
in fact trap on POWER8), that is, lmw/stmw, lswi/stswi, lswx/stswx,
lq/stq, and l[bhwdq]arx/st[bhwdq]cx.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-03-21 11:43:47 +07:00
|
|
|
kvmppc_get_gpr(vcpu, rs), 2, 1);
|
2014-06-18 19:53:49 +07:00
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
KVM: PPC: Book3S: Add MMIO emulation for FP and VSX instructions
This patch provides the MMIO load/store emulation for instructions
of 'double & vector unsigned char & vector signed char & vector
unsigned short & vector signed short & vector unsigned int & vector
signed int & vector double '.
The instructions that this adds emulation for are:
- ldx, ldux, lwax,
- lfs, lfsx, lfsu, lfsux, lfd, lfdx, lfdu, lfdux,
- stfs, stfsx, stfsu, stfsux, stfd, stfdx, stfdu, stfdux, stfiwx,
- lxsdx, lxsspx, lxsiwax, lxsiwzx, lxvd2x, lxvw4x, lxvdsx,
- stxsdx, stxsspx, stxsiwx, stxvd2x, stxvw4x
[paulus@ozlabs.org - some cleanups, fixes and rework, make it
compile for Book E, fix build when PR KVM is built in]
Signed-off-by: Bin Lu <lblulb@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2017-02-21 20:12:36 +07:00
|
|
|
#ifdef CONFIG_PPC_FPU
|
|
|
|
case OP_LFS:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LFSU:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
vcpu->arch.mmio_sp64_extend = 1;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 4, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LFD:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 8, 1);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case OP_LFDU:
|
|
|
|
if (kvmppc_check_fp_disabled(vcpu))
|
|
|
|
return EMULATE_DONE;
|
|
|
|
emulated = kvmppc_handle_load(run, vcpu,
|
|
|
|
KVM_MMIO_REG_FPR|rt, 8, 1);
|
|
|
|
kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
|
2014-06-18 19:53:49 +07:00
|
|
|
default:
|
|
|
|
emulated = EMULATE_FAIL;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (emulated == EMULATE_FAIL) {
|
|
|
|
advance = 0;
|
|
|
|
kvmppc_core_queue_program(vcpu, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
|
|
|
|
|
|
|
|
/* Advance past emulated instruction. */
|
|
|
|
if (advance)
|
|
|
|
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
|
|
|
|
|
|
|
|
return emulated;
|
|
|
|
}
|