2006-09-27 21:27:33 +07:00
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/*
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* linux/arch/arm/mm/mmu.c
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*
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* Copyright (C) 1995-2005 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2006-09-27 21:38:34 +07:00
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#include <linux/module.h>
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2006-09-27 21:27:33 +07:00
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/nodemask.h>
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2010-07-09 22:27:52 +07:00
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#include <linux/memblock.h>
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2010-09-13 22:01:24 +07:00
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#include <linux/fs.h>
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2011-08-25 11:35:59 +07:00
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#include <linux/vmalloc.h>
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2012-06-24 18:46:26 +07:00
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#include <linux/sizes.h>
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2006-09-27 21:27:33 +07:00
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2012-03-29 00:30:01 +07:00
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#include <asm/cp15.h>
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2008-08-11 00:08:10 +07:00
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#include <asm/cputype.h>
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2008-12-01 18:53:07 +07:00
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#include <asm/sections.h>
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2008-11-04 12:48:42 +07:00
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#include <asm/cachetype.h>
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2014-04-05 04:27:49 +07:00
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#include <asm/fixmap.h>
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2013-10-24 14:12:39 +07:00
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#include <asm/sections.h>
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2006-09-27 21:27:33 +07:00
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#include <asm/setup.h>
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2009-09-28 02:55:43 +07:00
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#include <asm/smp_plat.h>
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2006-09-27 21:27:33 +07:00
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#include <asm/tlb.h>
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2008-09-16 03:44:55 +07:00
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#include <asm/highmem.h>
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2012-03-29 00:30:01 +07:00
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#include <asm/system_info.h>
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2010-09-13 22:03:21 +07:00
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#include <asm/traps.h>
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2013-07-31 23:44:46 +07:00
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#include <asm/procinfo.h>
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#include <asm/memory.h>
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2006-09-27 21:27:33 +07:00
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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2012-03-01 07:10:58 +07:00
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#include <asm/mach/pci.h>
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2014-04-18 15:43:32 +07:00
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#include <asm/fixmap.h>
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2006-09-27 21:27:33 +07:00
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#include "mm.h"
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2013-04-05 09:16:51 +07:00
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#include "tcm.h"
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2006-09-27 21:27:33 +07:00
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/*
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* empty_zero_page is a special page that is used for
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* zero-initialized data and COW.
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*/
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struct page *empty_zero_page;
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2008-04-29 19:11:12 +07:00
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EXPORT_SYMBOL(empty_zero_page);
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2006-09-27 21:27:33 +07:00
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/*
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* The pmd table for the upper-most set of pages.
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*/
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pmd_t *top_pmd;
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2014-11-29 08:33:30 +07:00
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pmdval_t user_pmd_table = _PAGE_USER_TABLE;
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2006-09-27 21:38:34 +07:00
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#define CPOLICY_UNCACHED 0
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#define CPOLICY_BUFFERED 1
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#define CPOLICY_WRITETHROUGH 2
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#define CPOLICY_WRITEBACK 3
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#define CPOLICY_WRITEALLOC 4
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static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
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static unsigned int ecc_mask __initdata = 0;
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2007-02-11 19:45:13 +07:00
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pgprot_t pgprot_user;
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2006-09-27 21:38:34 +07:00
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pgprot_t pgprot_kernel;
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2013-01-21 06:28:04 +07:00
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pgprot_t pgprot_hyp_device;
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pgprot_t pgprot_s2;
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pgprot_t pgprot_s2_device;
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2006-09-27 21:38:34 +07:00
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2007-02-11 19:45:13 +07:00
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EXPORT_SYMBOL(pgprot_user);
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2006-09-27 21:38:34 +07:00
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EXPORT_SYMBOL(pgprot_kernel);
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struct cachepolicy {
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const char policy[16];
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unsigned int cr_mask;
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2011-09-05 23:51:56 +07:00
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pmdval_t pmd;
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2010-11-16 07:22:09 +07:00
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pteval_t pte;
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2013-01-21 06:28:04 +07:00
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pteval_t pte_s2;
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2006-09-27 21:38:34 +07:00
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};
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2013-01-21 06:28:04 +07:00
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#ifdef CONFIG_ARM_LPAE
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#define s2_policy(policy) policy
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#else
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#define s2_policy(policy) 0
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#endif
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2006-09-27 21:38:34 +07:00
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static struct cachepolicy cache_policies[] __initdata = {
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{
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.policy = "uncached",
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.cr_mask = CR_W|CR_C,
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.pmd = PMD_SECT_UNCACHED,
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2008-09-07 02:04:59 +07:00
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.pte = L_PTE_MT_UNCACHED,
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2013-01-21 06:28:04 +07:00
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.pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
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2006-09-27 21:38:34 +07:00
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}, {
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.policy = "buffered",
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.cr_mask = CR_C,
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.pmd = PMD_SECT_BUFFERED,
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2008-09-07 02:04:59 +07:00
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.pte = L_PTE_MT_BUFFERABLE,
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2013-01-21 06:28:04 +07:00
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.pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
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2006-09-27 21:38:34 +07:00
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}, {
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.policy = "writethrough",
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.cr_mask = 0,
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.pmd = PMD_SECT_WT,
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2008-09-07 02:04:59 +07:00
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.pte = L_PTE_MT_WRITETHROUGH,
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2013-01-21 06:28:04 +07:00
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.pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
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2006-09-27 21:38:34 +07:00
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}, {
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.policy = "writeback",
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.cr_mask = 0,
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.pmd = PMD_SECT_WB,
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2008-09-07 02:04:59 +07:00
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.pte = L_PTE_MT_WRITEBACK,
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2013-01-21 06:28:04 +07:00
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.pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
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2006-09-27 21:38:34 +07:00
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}, {
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.policy = "writealloc",
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.cr_mask = 0,
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.pmd = PMD_SECT_WBWA,
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2008-09-07 02:04:59 +07:00
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.pte = L_PTE_MT_WRITEALLOC,
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2013-01-21 06:28:04 +07:00
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.pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
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2006-09-27 21:38:34 +07:00
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}
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};
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2012-01-16 16:34:31 +07:00
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#ifdef CONFIG_CPU_CP15
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2014-06-02 15:29:37 +07:00
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static unsigned long initial_pmd_value __initdata = 0;
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2006-09-27 21:38:34 +07:00
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/*
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2014-05-28 02:34:28 +07:00
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* Initialise the cache_policy variable with the initial state specified
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* via the "pmd" value. This is used to ensure that on ARMv6 and later,
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* the C code sets the page tables up with the same policy as the head
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* assembly code, which avoids an illegal state where the TLBs can get
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* confused. See comments in early_cachepolicy() for more information.
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2006-09-27 21:38:34 +07:00
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*/
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2014-05-28 02:34:28 +07:00
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void __init init_default_cache_policy(unsigned long pmd)
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2006-09-27 21:38:34 +07:00
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{
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int i;
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2014-06-02 15:29:37 +07:00
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initial_pmd_value = pmd;
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2014-05-28 02:34:28 +07:00
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pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
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if (cache_policies[i].pmd == pmd) {
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cachepolicy = i;
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break;
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}
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if (i == ARRAY_SIZE(cache_policies))
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pr_err("ERROR: could not find cache policy\n");
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}
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/*
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* These are useful for identifying cache coherency problems by allowing
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* the cache or the cache and writebuffer to be turned off. (Note: the
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* write buffer should not be on and the cache off).
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*/
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static int __init early_cachepolicy(char *p)
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{
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int i, selected = -1;
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2006-09-27 21:38:34 +07:00
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for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
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int len = strlen(cache_policies[i].policy);
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2010-01-12 05:17:34 +07:00
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if (memcmp(p, cache_policies[i].policy, len) == 0) {
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2014-05-28 02:34:28 +07:00
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selected = i;
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2006-09-27 21:38:34 +07:00
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break;
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}
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}
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2014-05-28 02:34:28 +07:00
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if (selected == -1)
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pr_err("ERROR: unknown or unsupported cache policy\n");
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2009-11-02 00:44:24 +07:00
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/*
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* This restriction is partly to do with the way we boot; it is
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* unpredictable to have memory mapped using two different sets of
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* memory attributes (shared, type, and cache attribs). We can not
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* change these attributes once the initial assembly has setup the
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* page tables.
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*/
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2014-05-28 02:34:28 +07:00
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if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
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pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
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cache_policies[cachepolicy].policy);
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return 0;
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}
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if (selected != cachepolicy) {
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unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
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cachepolicy = selected;
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flush_cache_all();
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set_cr(cr);
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2007-07-20 17:42:24 +07:00
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}
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2010-01-12 05:17:34 +07:00
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return 0;
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2006-09-27 21:38:34 +07:00
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}
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2010-01-12 05:17:34 +07:00
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early_param("cachepolicy", early_cachepolicy);
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2006-09-27 21:38:34 +07:00
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2010-01-12 05:17:34 +07:00
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static int __init early_nocache(char *__unused)
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2006-09-27 21:38:34 +07:00
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{
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char *p = "buffered";
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2014-10-28 18:26:42 +07:00
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pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
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2010-01-12 05:17:34 +07:00
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early_cachepolicy(p);
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return 0;
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2006-09-27 21:38:34 +07:00
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}
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2010-01-12 05:17:34 +07:00
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early_param("nocache", early_nocache);
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2006-09-27 21:38:34 +07:00
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2010-01-12 05:17:34 +07:00
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static int __init early_nowrite(char *__unused)
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2006-09-27 21:38:34 +07:00
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{
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char *p = "uncached";
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2014-10-28 18:26:42 +07:00
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pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
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2010-01-12 05:17:34 +07:00
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early_cachepolicy(p);
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return 0;
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2006-09-27 21:38:34 +07:00
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}
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2010-01-12 05:17:34 +07:00
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early_param("nowb", early_nowrite);
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2006-09-27 21:38:34 +07:00
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2011-11-23 00:30:29 +07:00
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#ifndef CONFIG_ARM_LPAE
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2010-01-12 05:17:34 +07:00
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static int __init early_ecc(char *p)
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2006-09-27 21:38:34 +07:00
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{
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2010-01-12 05:17:34 +07:00
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if (memcmp(p, "on", 2) == 0)
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2006-09-27 21:38:34 +07:00
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ecc_mask = PMD_PROTECTION;
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2010-01-12 05:17:34 +07:00
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else if (memcmp(p, "off", 3) == 0)
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2006-09-27 21:38:34 +07:00
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ecc_mask = 0;
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2010-01-12 05:17:34 +07:00
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return 0;
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2006-09-27 21:38:34 +07:00
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}
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2010-01-12 05:17:34 +07:00
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early_param("ecc", early_ecc);
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2011-11-23 00:30:29 +07:00
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#endif
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2006-09-27 21:38:34 +07:00
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2012-01-16 16:34:31 +07:00
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#else /* ifdef CONFIG_CPU_CP15 */
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static int __init early_cachepolicy(char *p)
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{
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2014-09-17 02:41:43 +07:00
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pr_warn("cachepolicy kernel parameter not supported without cp15\n");
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2012-01-16 16:34:31 +07:00
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}
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early_param("cachepolicy", early_cachepolicy);
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static int __init noalign_setup(char *__unused)
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{
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2014-09-17 02:41:43 +07:00
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pr_warn("noalign kernel parameter not supported without cp15\n");
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2012-01-16 16:34:31 +07:00
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}
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__setup("noalign", noalign_setup);
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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2010-11-16 15:40:36 +07:00
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
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2014-02-03 04:21:31 +07:00
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#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
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2007-05-06 02:28:16 +07:00
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2007-04-21 16:47:29 +07:00
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static struct mem_type mem_types[] = {
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2007-05-06 02:28:16 +07:00
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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2008-09-07 02:04:59 +07:00
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
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L_PTE_SHARED,
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2014-02-03 04:21:31 +07:00
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.prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
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s2_policy(L_PTE_S2_MT_DEV_SHARED) |
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L_PTE_SHARED,
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2007-05-06 02:28:16 +07:00
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.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
|
2007-05-06 02:28:16 +07:00
|
|
|
.domain = DOMAIN_IO,
|
|
|
|
},
|
|
|
|
[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
|
2008-09-07 02:04:59 +07:00
|
|
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
|
2007-05-06 02:28:16 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
.prot_sect = PROT_SECT_DEVICE,
|
2007-05-06 02:28:16 +07:00
|
|
|
.domain = DOMAIN_IO,
|
|
|
|
},
|
|
|
|
[MT_DEVICE_CACHED] = { /* ioremap_cached */
|
2008-09-07 02:04:59 +07:00
|
|
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
|
2007-05-06 02:28:16 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
|
|
|
|
.domain = DOMAIN_IO,
|
2012-03-01 07:10:58 +07:00
|
|
|
},
|
[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 19:17:11 +07:00
|
|
|
[MT_DEVICE_WC] = { /* ioremap_wc */
|
2008-09-07 02:04:59 +07:00
|
|
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
|
2007-05-06 02:28:16 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
.prot_sect = PROT_SECT_DEVICE,
|
2007-05-06 02:28:16 +07:00
|
|
|
.domain = DOMAIN_IO,
|
2006-09-27 21:38:34 +07:00
|
|
|
},
|
2008-11-09 18:18:36 +07:00
|
|
|
[MT_UNCACHED] = {
|
|
|
|
.prot_pte = PROT_PTE_DEVICE,
|
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
|
|
|
.domain = DOMAIN_IO,
|
|
|
|
},
|
2006-09-27 21:38:34 +07:00
|
|
|
[MT_CACHECLEAN] = {
|
2007-05-06 02:03:35 +07:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
2006-09-27 21:38:34 +07:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2006-09-27 21:38:34 +07:00
|
|
|
[MT_MINICLEAN] = {
|
2007-05-06 02:03:35 +07:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
|
2006-09-27 21:38:34 +07:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
2006-09-27 21:38:34 +07:00
|
|
|
[MT_LOW_VECTORS] = {
|
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 15:40:36 +07:00
|
|
|
L_PTE_RDONLY,
|
2006-09-27 21:38:34 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.domain = DOMAIN_USER,
|
|
|
|
},
|
|
|
|
[MT_HIGH_VECTORS] = {
|
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 15:40:36 +07:00
|
|
|
L_PTE_USER | L_PTE_RDONLY,
|
2006-09-27 21:38:34 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.domain = DOMAIN_USER,
|
|
|
|
},
|
2013-10-24 16:26:40 +07:00
|
|
|
[MT_MEMORY_RWX] = {
|
2010-11-16 15:40:36 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
|
2010-09-24 13:18:22 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
2007-05-06 02:03:35 +07:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
2006-09-27 21:38:34 +07:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2013-10-24 14:12:39 +07:00
|
|
|
[MT_MEMORY_RW] = {
|
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
|
|
|
L_PTE_XN,
|
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2006-09-27 21:38:34 +07:00
|
|
|
[MT_ROM] = {
|
2007-05-06 02:03:35 +07:00
|
|
|
.prot_sect = PMD_TYPE_SECT,
|
2006-09-27 21:38:34 +07:00
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2013-10-24 16:26:40 +07:00
|
|
|
[MT_MEMORY_RWX_NONCACHED] = {
|
2010-09-24 13:18:22 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 15:40:36 +07:00
|
|
|
L_PTE_MT_BUFFERABLE,
|
2010-09-24 13:18:22 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 02:11:43 +07:00
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2013-10-24 16:26:40 +07:00
|
|
|
[MT_MEMORY_RW_DTCM] = {
|
2010-10-18 15:03:03 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2010-11-16 15:40:36 +07:00
|
|
|
L_PTE_XN,
|
2010-10-18 15:03:03 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
|
|
|
|
.domain = DOMAIN_KERNEL,
|
2010-07-13 03:50:59 +07:00
|
|
|
},
|
2013-10-24 16:26:40 +07:00
|
|
|
[MT_MEMORY_RWX_ITCM] = {
|
2010-11-16 15:40:36 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
|
2010-07-13 03:50:59 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
2010-10-18 15:03:03 +07:00
|
|
|
.domain = DOMAIN_KERNEL,
|
2010-07-13 03:50:59 +07:00
|
|
|
},
|
2013-10-24 16:26:40 +07:00
|
|
|
[MT_MEMORY_RW_SO] = {
|
2011-06-29 02:42:56 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
2013-01-17 13:18:04 +07:00
|
|
|
L_PTE_MT_UNCACHED | L_PTE_XN,
|
2011-06-29 02:42:56 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
|
|
|
|
PMD_SECT_UNCACHED | PMD_SECT_XN,
|
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2011-12-29 19:09:51 +07:00
|
|
|
[MT_MEMORY_DMA_READY] = {
|
2013-11-25 19:01:03 +07:00
|
|
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
|
|
|
L_PTE_XN,
|
2011-12-29 19:09:51 +07:00
|
|
|
.prot_l1 = PMD_TYPE_TABLE,
|
|
|
|
.domain = DOMAIN_KERNEL,
|
|
|
|
},
|
2006-09-27 21:38:34 +07:00
|
|
|
};
|
|
|
|
|
2007-04-21 16:47:29 +07:00
|
|
|
const struct mem_type *get_mem_type(unsigned int type)
|
|
|
|
{
|
|
|
|
return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
|
|
|
|
}
|
2009-01-29 02:32:08 +07:00
|
|
|
EXPORT_SYMBOL(get_mem_type);
|
2007-04-21 16:47:29 +07:00
|
|
|
|
2014-04-05 04:27:49 +07:00
|
|
|
/*
|
|
|
|
* To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range().
|
|
|
|
* As a result, this can only be called with preemption disabled, as under
|
|
|
|
* stop_machine().
|
|
|
|
*/
|
|
|
|
void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
|
|
|
|
{
|
|
|
|
unsigned long vaddr = __fix_to_virt(idx);
|
|
|
|
pte_t *pte = pte_offset_kernel(pmd_off_k(vaddr), vaddr);
|
|
|
|
|
|
|
|
/* Make sure fixmap region does not exceed available allocation. */
|
|
|
|
BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
|
|
|
|
FIXADDR_END);
|
|
|
|
BUG_ON(idx >= __end_of_fixed_addresses);
|
|
|
|
|
|
|
|
if (pgprot_val(prot))
|
|
|
|
set_pte_at(NULL, vaddr, pte,
|
|
|
|
pfn_pte(phys >> PAGE_SHIFT, prot));
|
|
|
|
else
|
|
|
|
pte_clear(NULL, vaddr, pte);
|
|
|
|
local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
|
|
|
|
}
|
|
|
|
|
2006-09-27 21:38:34 +07:00
|
|
|
/*
|
|
|
|
* Adjust the PMD section entries according to the CPU in use.
|
|
|
|
*/
|
|
|
|
static void __init build_mem_type_table(void)
|
|
|
|
{
|
|
|
|
struct cachepolicy *cp;
|
|
|
|
unsigned int cr = get_cr();
|
2011-09-05 23:51:56 +07:00
|
|
|
pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
|
2013-01-21 06:28:04 +07:00
|
|
|
pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
|
2006-09-27 21:38:34 +07:00
|
|
|
int cpu_arch = cpu_architecture();
|
|
|
|
int i;
|
|
|
|
|
2007-07-20 17:42:24 +07:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv6) {
|
2006-09-27 21:38:34 +07:00
|
|
|
#if defined(CONFIG_CPU_DCACHE_DISABLE)
|
2007-07-20 17:42:24 +07:00
|
|
|
if (cachepolicy > CPOLICY_BUFFERED)
|
|
|
|
cachepolicy = CPOLICY_BUFFERED;
|
2006-09-27 21:38:34 +07:00
|
|
|
#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
|
2007-07-20 17:42:24 +07:00
|
|
|
if (cachepolicy > CPOLICY_WRITETHROUGH)
|
|
|
|
cachepolicy = CPOLICY_WRITETHROUGH;
|
2006-09-27 21:38:34 +07:00
|
|
|
#endif
|
2007-07-20 17:42:24 +07:00
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv5) {
|
|
|
|
if (cachepolicy >= CPOLICY_WRITEALLOC)
|
|
|
|
cachepolicy = CPOLICY_WRITEBACK;
|
|
|
|
ecc_mask = 0;
|
|
|
|
}
|
2014-05-28 02:34:28 +07:00
|
|
|
|
2014-06-02 15:29:37 +07:00
|
|
|
if (is_smp()) {
|
|
|
|
if (cachepolicy != CPOLICY_WRITEALLOC) {
|
|
|
|
pr_warn("Forcing write-allocate cache policy for SMP\n");
|
|
|
|
cachepolicy = CPOLICY_WRITEALLOC;
|
|
|
|
}
|
|
|
|
if (!(initial_pmd_value & PMD_SECT_S)) {
|
|
|
|
pr_warn("Forcing shared mappings for SMP\n");
|
|
|
|
initial_pmd_value |= PMD_SECT_S;
|
|
|
|
}
|
2014-05-28 02:34:28 +07:00
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
|
[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 19:17:11 +07:00
|
|
|
/*
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
* Strip out features not present on earlier architectures.
|
|
|
|
* Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those
|
|
|
|
* without extended page tables don't have the 'Shared' bit.
|
[ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().
We use different page table attributes depending on which CPU we
are running on:
- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
possible mapping types (CB=00/01/10/11). We can't use any of the
cached memory types (CB=10/11), since that breaks coherency with
peripheral devices. Both CB=00 and CB=01 are suitable for _wc, and
CB=01 (Uncached/Buffered) allows the hardware more freedom than
CB=00, so we'll use that.
(The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
but isn't allowed to merge them, but there is no other mapping type
we can use that allows the hardware to delay and merge stores, so
we'll go with CB=01.)
- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
difference that on these platforms, CB=01 actually _does_ allow
merging stores. (If you want noncoalescing bufferable behavior
on Xscale v1/v2, you need to use XCB=101.)
- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
in ARMv6 parlance).
The ARMv6 ARM explicitly says that any accesses to Normal memory can
be merged, which makes Normal memory more suitable for _wc mappings
than Device or Strongly Ordered memory, as the latter two mapping
types are guaranteed to maintain transaction number, size and order.
We use the Uncached variety of Normal mappings for the same reason
that we can't use C=1 mappings on ARMv5.
The xsc3 Architecture Specification documents TEXCB=00100 as being
Uncacheable and allowing coalescing of writes, which is also just
what we need.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 19:17:11 +07:00
|
|
|
*/
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
if (cpu_arch < CPU_ARCH_ARMv5)
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
|
|
|
|
mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
|
|
|
|
if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++)
|
|
|
|
mem_types[i].prot_sect &= ~PMD_SECT_S;
|
2006-09-27 21:38:34 +07:00
|
|
|
|
|
|
|
/*
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
* ARMv5 and lower, bit 4 must be set for page tables (was: cache
|
|
|
|
* "update-able on write" bit on ARM610). However, Xscale and
|
|
|
|
* Xscale3 require this bit to be cleared.
|
2006-09-27 21:38:34 +07:00
|
|
|
*/
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
if (cpu_is_xscale() || cpu_is_xsc3()) {
|
2007-05-06 02:03:35 +07:00
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
2006-09-27 21:38:34 +07:00
|
|
|
mem_types[i].prot_sect &= ~PMD_BIT4;
|
2007-05-06 02:03:35 +07:00
|
|
|
mem_types[i].prot_l1 &= ~PMD_BIT4;
|
|
|
|
}
|
|
|
|
} else if (cpu_arch < CPU_ARCH_ARMv6) {
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
2006-09-27 21:38:34 +07:00
|
|
|
if (mem_types[i].prot_l1)
|
|
|
|
mem_types[i].prot_l1 |= PMD_BIT4;
|
2007-05-06 02:03:35 +07:00
|
|
|
if (mem_types[i].prot_sect)
|
|
|
|
mem_types[i].prot_sect |= PMD_BIT4;
|
|
|
|
}
|
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
/*
|
|
|
|
* Mark the device areas according to the CPU/architecture.
|
|
|
|
*/
|
|
|
|
if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
|
|
|
|
if (!cpu_is_xsc3()) {
|
|
|
|
/*
|
|
|
|
* Mark device regions on ARMv6+ as execute-never
|
|
|
|
* to prevent speculative instruction fetches.
|
|
|
|
*/
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
|
2013-10-24 14:12:39 +07:00
|
|
|
|
|
|
|
/* Also setup NX memory mapping */
|
|
|
|
mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
|
[ARM] mm: fix page table initialization
As a result of the ptebits changes, we ended up marking device mappings
as normal memory on ARMv7 CPUs, resulting in undesirable behaviour with
serial ports and the like. While reviewing the section mapping table
entries, other errors in the memory type settings for devices were
detected and confirmed to prevent Xscale3 platforms booting.
Tested on:
OMAP34xx (ARMv7),
OMAP24xx (ARMv6),
OMAP16xx (ARM926T, ARMv5),
PXA311 (Xscale3),
PXA272 (Xscale),
PXA255 (Xscale),
IXP42x (Xscale),
S3C2410 (ARM920T, ARMv4T),
ARM720T (ARMv4T)
StrongARM-110 (ARMv4)
Acked-by: Tony Lindgren <tony@atomide.com>
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Mike Rapoport <mike@compulab.co.il>
Tested-by: Ben Dooks <ben-linux@fluff.org>
Tested-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-11-04 17:52:28 +07:00
|
|
|
}
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
|
|
|
|
/*
|
|
|
|
* For ARMv7 with TEX remapping,
|
|
|
|
* - shared device is SXCB=1100
|
|
|
|
* - nonshared device is SXCB=0100
|
|
|
|
* - write combine device mem is SXCB=0001
|
|
|
|
* (Uncached Normal memory)
|
|
|
|
*/
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
|
|
} else if (cpu_is_xsc3()) {
|
|
|
|
/*
|
|
|
|
* For Xscale3,
|
|
|
|
* - shared device is TEXCB=00101
|
|
|
|
* - nonshared device is TEXCB=01000
|
|
|
|
* - write combine device mem is TEXCB=00100
|
|
|
|
* (Inner/Outer Uncacheable in xsc3 parlance)
|
|
|
|
*/
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* For ARMv6 and ARMv7 without TEX remapping,
|
|
|
|
* - shared device is TEXCB=00001
|
|
|
|
* - nonshared device is TEXCB=01000
|
|
|
|
* - write combine device mem is TEXCB=00100
|
|
|
|
* (Uncached Normal in ARMv6 parlance).
|
|
|
|
*/
|
|
|
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
|
|
|
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* On others, write combining is "Uncached/Buffered"
|
|
|
|
*/
|
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now deal with the memory-type mappings
|
|
|
|
*/
|
2006-09-27 21:38:34 +07:00
|
|
|
cp = &cache_policies[cachepolicy];
|
2008-09-07 02:04:59 +07:00
|
|
|
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
|
2013-01-21 06:28:04 +07:00
|
|
|
s2_pgprot = cp->pte_s2;
|
2014-02-03 04:21:31 +07:00
|
|
|
hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
|
|
|
|
s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
|
2008-09-07 02:04:59 +07:00
|
|
|
|
2014-11-29 08:33:30 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2014-02-08 01:12:27 +07:00
|
|
|
/*
|
|
|
|
* We don't use domains on ARMv6 (since this causes problems with
|
|
|
|
* v6/v7 kernels), so we must use a separate memory type for user
|
|
|
|
* r/o, kernel r/w to map the vectors page.
|
|
|
|
*/
|
|
|
|
if (cpu_arch == CPU_ARCH_ARMv6)
|
|
|
|
vecs_pgprot |= L_PTE_MT_VECTORS;
|
2014-11-29 08:33:30 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check is it with support for the PXN bit
|
|
|
|
* in the Short-descriptor translation table format descriptors.
|
|
|
|
*/
|
|
|
|
if (cpu_arch == CPU_ARCH_ARMv7 &&
|
|
|
|
(read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) == 4) {
|
|
|
|
user_pmd_table |= PMD_PXNTABLE;
|
|
|
|
}
|
2014-02-08 01:12:27 +07:00
|
|
|
#endif
|
2008-09-07 02:04:59 +07:00
|
|
|
|
2006-09-27 21:38:34 +07:00
|
|
|
/*
|
|
|
|
* ARMv6 and above have extended page tables.
|
|
|
|
*/
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2006-09-27 21:38:34 +07:00
|
|
|
/*
|
|
|
|
* Mark cache clean areas and XIP ROM read only
|
|
|
|
* from SVC mode and no access from userspace.
|
|
|
|
*/
|
|
|
|
mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
|
|
mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2014-06-02 15:29:37 +07:00
|
|
|
/*
|
|
|
|
* If the initial page tables were created with the S bit
|
|
|
|
* set, then we need to do the same here for the same
|
|
|
|
* reasons given in early_cachepolicy().
|
|
|
|
*/
|
|
|
|
if (initial_pmd_value & PMD_SECT_S) {
|
2010-09-04 16:47:48 +07:00
|
|
|
user_pgprot |= L_PTE_SHARED;
|
|
|
|
kern_pgprot |= L_PTE_SHARED;
|
|
|
|
vecs_pgprot |= L_PTE_SHARED;
|
2013-01-21 06:28:04 +07:00
|
|
|
s2_pgprot |= L_PTE_SHARED;
|
2010-09-04 16:47:48 +07:00
|
|
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
|
|
|
|
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
|
|
|
|
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
|
|
|
|
mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
|
2013-10-24 14:12:39 +07:00
|
|
|
mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
|
|
|
|
mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
|
2011-12-29 19:09:51 +07:00
|
|
|
mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
|
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
|
2010-09-04 16:47:48 +07:00
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 02:11:43 +07:00
|
|
|
/*
|
|
|
|
* Non-cacheable Normal - intended for memory areas that must
|
|
|
|
* not cause dirty cache line writebacks when used
|
|
|
|
*/
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv6) {
|
|
|
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
|
|
|
|
/* Non-cacheable Normal is XCB = 001 */
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 02:11:43 +07:00
|
|
|
PMD_SECT_BUFFERED;
|
|
|
|
} else {
|
|
|
|
/* For both ARMv6 and non-TEX-remapping ARMv7 */
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 02:11:43 +07:00
|
|
|
PMD_SECT_TEX(1);
|
|
|
|
}
|
|
|
|
} else {
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
|
[ARM] 5422/1: ARM: MMU: add a Non-cacheable Normal executable memory type
This patch adds a Non-cacheable Normal ARM executable memory type,
MT_MEMORY_NONCACHED.
On OMAP3, this is used for rapid dynamic voltage/frequency scaling in
the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the
VDD2 voltage domain, and its clock frequency must change along with
voltage. The SDRC clock change code cannot run from SDRAM itself,
since SDRAM accesses are paused during the clock change. So the
current implementation of the DVFS code executes from OMAP on-chip
SRAM, aka "OCM RAM."
If the OCM RAM pages are marked as Cacheable, the ARM cache controller
will attempt to flush dirty cache lines to the SDRC, so it can fill
those lines with OCM RAM instruction code. The problem is that the
SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU
subsystem to hang.
TI's original solution to this problem was to mark the OCM RAM
sections as Strongly Ordered memory, thus preventing caching. This is
overkill: since the memory is marked as non-bufferable, OCM RAM writes
become needlessly slow. The idea of "Strongly Ordered SRAM" is also
conceptually disturbing. Previous LAKML list discussion is here:
http://www.spinics.net/lists/arm-kernel/msg54312.html
This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future
patch.
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-03-13 02:11:43 +07:00
|
|
|
}
|
|
|
|
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifdef CONFIG_ARM_LPAE
|
|
|
|
/*
|
|
|
|
* Do not generate access flag faults for the kernel mappings.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
|
|
|
mem_types[i].prot_pte |= PTE_EXT_AF;
|
2012-05-15 21:01:16 +07:00
|
|
|
if (mem_types[i].prot_sect)
|
|
|
|
mem_types[i].prot_sect |= PMD_SECT_AF;
|
2011-11-23 00:30:29 +07:00
|
|
|
}
|
|
|
|
kern_pgprot |= PTE_EXT_AF;
|
|
|
|
vecs_pgprot |= PTE_EXT_AF;
|
2014-11-29 08:33:30 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set PXN for user mappings
|
|
|
|
*/
|
|
|
|
user_pgprot |= PTE_EXT_PXN;
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
|
|
|
|
2006-09-27 21:38:34 +07:00
|
|
|
for (i = 0; i < 16; i++) {
|
2012-09-19 01:18:35 +07:00
|
|
|
pteval_t v = pgprot_val(protection_map[i]);
|
2008-09-07 02:04:59 +07:00
|
|
|
protection_map[i] = __pgprot(v | user_pgprot);
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2008-09-07 02:04:59 +07:00
|
|
|
mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
|
|
|
|
mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2007-02-11 19:45:13 +07:00
|
|
|
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
|
2006-09-27 21:38:34 +07:00
|
|
|
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
|
2010-11-16 15:40:36 +07:00
|
|
|
L_PTE_DIRTY | kern_pgprot);
|
2013-01-21 06:28:04 +07:00
|
|
|
pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
|
|
|
|
pgprot_s2_device = __pgprot(s2_device_pgprot);
|
|
|
|
pgprot_hyp_device = __pgprot(hyp_device_pgprot);
|
2006-09-27 21:38:34 +07:00
|
|
|
|
|
|
|
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
|
|
|
|
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
|
|
|
|
mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
|
2013-10-24 14:12:39 +07:00
|
|
|
mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
|
|
|
|
mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
|
2011-12-29 19:09:51 +07:00
|
|
|
mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
|
2013-10-24 16:26:40 +07:00
|
|
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
|
2006-09-27 21:38:34 +07:00
|
|
|
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
|
|
|
|
|
|
|
switch (cp->pmd) {
|
|
|
|
case PMD_SECT_WT:
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
|
|
|
|
break;
|
|
|
|
case PMD_SECT_WB:
|
|
|
|
case PMD_SECT_WBWA:
|
|
|
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
|
|
|
|
break;
|
|
|
|
}
|
2013-11-07 18:49:53 +07:00
|
|
|
pr_info("Memory policy: %sData cache %s\n",
|
|
|
|
ecc_mask ? "ECC enabled, " : "", cp->policy);
|
2007-04-21 15:59:44 +07:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
|
|
|
|
struct mem_type *t = &mem_types[i];
|
|
|
|
if (t->prot_l1)
|
|
|
|
t->prot_l1 |= PMD_DOMAIN(t->domain);
|
|
|
|
if (t->prot_sect)
|
|
|
|
t->prot_sect |= PMD_DOMAIN(t->domain);
|
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2010-09-13 22:01:24 +07:00
|
|
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
|
|
|
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|
|
|
unsigned long size, pgprot_t vma_prot)
|
|
|
|
{
|
|
|
|
if (!pfn_valid(pfn))
|
|
|
|
return pgprot_noncached(vma_prot);
|
|
|
|
else if (file->f_flags & O_SYNC)
|
|
|
|
return pgprot_writecombine(vma_prot);
|
|
|
|
return vma_prot;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(phys_mem_access_prot);
|
|
|
|
#endif
|
|
|
|
|
2006-09-27 21:38:34 +07:00
|
|
|
#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
|
|
|
|
|
2011-08-25 11:35:59 +07:00
|
|
|
static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
|
2010-03-26 00:02:59 +07:00
|
|
|
{
|
2011-08-25 11:35:59 +07:00
|
|
|
void *ptr = __va(memblock_alloc(sz, align));
|
2010-07-09 22:27:52 +07:00
|
|
|
memset(ptr, 0, sz);
|
|
|
|
return ptr;
|
2010-03-26 00:02:59 +07:00
|
|
|
}
|
|
|
|
|
2011-08-25 11:35:59 +07:00
|
|
|
static void __init *early_alloc(unsigned long sz)
|
|
|
|
{
|
|
|
|
return early_alloc_aligned(sz, sz);
|
|
|
|
}
|
|
|
|
|
2010-07-02 00:33:29 +07:00
|
|
|
static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
|
2006-09-27 21:38:34 +07:00
|
|
|
{
|
2007-04-21 16:21:28 +07:00
|
|
|
if (pmd_none(*pmd)) {
|
2011-02-14 18:58:04 +07:00
|
|
|
pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
|
2010-11-16 07:16:01 +07:00
|
|
|
__pmd_populate(pmd, __pa(pte), prot);
|
2007-04-21 16:21:28 +07:00
|
|
|
}
|
2010-07-02 00:33:29 +07:00
|
|
|
BUG_ON(pmd_bad(*pmd));
|
|
|
|
return pte_offset_kernel(pmd, addr);
|
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2010-07-02 00:33:29 +07:00
|
|
|
static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
|
|
|
|
unsigned long end, unsigned long pfn,
|
|
|
|
const struct mem_type *type)
|
|
|
|
{
|
|
|
|
pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
|
2007-04-21 16:21:28 +07:00
|
|
|
do {
|
2008-09-07 03:15:56 +07:00
|
|
|
set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
|
2007-04-21 16:21:28 +07:00
|
|
|
pfn++;
|
|
|
|
} while (pte++, addr += PAGE_SIZE, addr != end);
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2013-06-07 18:15:45 +07:00
|
|
|
static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
|
2013-03-18 18:24:04 +07:00
|
|
|
unsigned long end, phys_addr_t phys,
|
|
|
|
const struct mem_type *type)
|
2006-09-27 21:38:34 +07:00
|
|
|
{
|
2013-06-07 18:15:45 +07:00
|
|
|
pmd_t *p = pmd;
|
|
|
|
|
2013-03-18 18:24:04 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2007-04-21 16:21:28 +07:00
|
|
|
/*
|
2013-03-18 18:24:04 +07:00
|
|
|
* In classic MMU format, puds and pmds are folded in to
|
|
|
|
* the pgds. pmd_offset gives the PGD entry. PGDs refer to a
|
|
|
|
* group of L1 entries making up one logical pointer to
|
|
|
|
* an L2 table (2MB), where as PMDs refer to the individual
|
|
|
|
* L1 entries (1MB). Hence increment to get the correct
|
|
|
|
* offset for odd 1MB sections.
|
|
|
|
* (See arch/arm/include/asm/pgtable-2level.h)
|
2007-04-21 16:21:28 +07:00
|
|
|
*/
|
2013-03-18 18:24:04 +07:00
|
|
|
if (addr & SECTION_SIZE)
|
|
|
|
pmd++;
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
2013-03-18 18:24:04 +07:00
|
|
|
do {
|
|
|
|
*pmd = __pmd(phys | type->prot_sect);
|
|
|
|
phys += SECTION_SIZE;
|
|
|
|
} while (pmd++, addr += SECTION_SIZE, addr != end);
|
2007-04-21 16:21:28 +07:00
|
|
|
|
2013-06-07 18:15:45 +07:00
|
|
|
flush_pmd_entry(p);
|
2013-03-18 18:24:04 +07:00
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2013-03-18 18:24:04 +07:00
|
|
|
static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
|
|
|
|
unsigned long end, phys_addr_t phys,
|
|
|
|
const struct mem_type *type)
|
|
|
|
{
|
|
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
|
|
|
unsigned long next;
|
|
|
|
|
|
|
|
do {
|
2007-04-21 16:21:28 +07:00
|
|
|
/*
|
2013-03-18 18:24:04 +07:00
|
|
|
* With LPAE, we must loop over to map
|
|
|
|
* all the pmds for the given range.
|
2007-04-21 16:21:28 +07:00
|
|
|
*/
|
2013-03-18 18:24:04 +07:00
|
|
|
next = pmd_addr_end(addr, end);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Try a section mapping - addr, next and phys must all be
|
|
|
|
* aligned to a section boundary.
|
|
|
|
*/
|
|
|
|
if (type->prot_sect &&
|
|
|
|
((addr | next | phys) & ~SECTION_MASK) == 0) {
|
2013-06-07 18:15:45 +07:00
|
|
|
__map_init_section(pmd, addr, next, phys, type);
|
2013-03-18 18:24:04 +07:00
|
|
|
} else {
|
|
|
|
alloc_init_pte(pmd, addr, next,
|
|
|
|
__phys_to_pfn(phys), type);
|
|
|
|
}
|
|
|
|
|
|
|
|
phys += next - addr;
|
|
|
|
|
|
|
|
} while (pmd++, addr = next, addr != end);
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2012-04-27 07:40:10 +07:00
|
|
|
static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
|
2012-07-11 01:41:17 +07:00
|
|
|
unsigned long end, phys_addr_t phys,
|
|
|
|
const struct mem_type *type)
|
2010-11-21 23:27:49 +07:00
|
|
|
{
|
|
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
|
|
unsigned long next;
|
|
|
|
|
|
|
|
do {
|
|
|
|
next = pud_addr_end(addr, end);
|
2013-03-18 18:24:04 +07:00
|
|
|
alloc_init_pmd(pud, addr, next, phys, type);
|
2010-11-21 23:27:49 +07:00
|
|
|
phys += next - addr;
|
|
|
|
} while (pud++, addr = next, addr != end);
|
|
|
|
}
|
|
|
|
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2007-04-21 16:16:48 +07:00
|
|
|
static void __init create_36bit_mapping(struct map_desc *md,
|
|
|
|
const struct mem_type *type)
|
|
|
|
{
|
2010-11-16 07:16:01 +07:00
|
|
|
unsigned long addr, length, end;
|
|
|
|
phys_addr_t phys;
|
2007-04-21 16:16:48 +07:00
|
|
|
pgd_t *pgd;
|
|
|
|
|
|
|
|
addr = md->virtual;
|
2011-02-15 18:42:57 +07:00
|
|
|
phys = __pfn_to_phys(md->pfn);
|
2007-04-21 16:16:48 +07:00
|
|
|
length = PAGE_ALIGN(md->length);
|
|
|
|
|
|
|
|
if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
|
2011-02-15 20:31:37 +07:00
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 16:16:48 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* N.B. ARMv6 supersections are only defined to work with domain 0.
|
|
|
|
* Since domain assignments can in fact be arbitrary, the
|
|
|
|
* 'domain == 0' check below is required to insure that ARMv6
|
|
|
|
* supersections are only allocated for domain 0 regardless
|
|
|
|
* of the actual domain assignments in use.
|
|
|
|
*/
|
|
|
|
if (type->domain) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
|
2011-02-15 20:31:37 +07:00
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 16:16:48 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
|
2011-02-15 20:31:37 +07:00
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), addr);
|
2007-04-21 16:16:48 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Shift bits [35:32] of address into bits [23:20] of PMD
|
|
|
|
* (See ARMv6 spec).
|
|
|
|
*/
|
|
|
|
phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
|
|
|
|
|
|
|
|
pgd = pgd_offset_k(addr);
|
|
|
|
end = addr + length;
|
|
|
|
do {
|
2010-11-21 23:27:49 +07:00
|
|
|
pud_t *pud = pud_offset(pgd, addr);
|
|
|
|
pmd_t *pmd = pmd_offset(pud, addr);
|
2007-04-21 16:16:48 +07:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
|
|
|
|
|
|
|
|
addr += SUPERSECTION_SIZE;
|
|
|
|
phys += SUPERSECTION_SIZE;
|
|
|
|
pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
|
|
|
|
} while (addr != end);
|
|
|
|
}
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif /* !CONFIG_ARM_LPAE */
|
2007-04-21 16:16:48 +07:00
|
|
|
|
2006-09-27 21:38:34 +07:00
|
|
|
/*
|
|
|
|
* Create the page directory entries and any necessary
|
|
|
|
* page tables for the mapping specified by `md'. We
|
|
|
|
* are able to cope here with varying sizes and address
|
|
|
|
* offsets, and we take full advantage of sections and
|
|
|
|
* supersections.
|
|
|
|
*/
|
2010-03-26 01:56:05 +07:00
|
|
|
static void __init create_mapping(struct map_desc *md)
|
2006-09-27 21:38:34 +07:00
|
|
|
{
|
2011-02-15 18:42:57 +07:00
|
|
|
unsigned long addr, length, end;
|
|
|
|
phys_addr_t phys;
|
2007-04-21 16:05:32 +07:00
|
|
|
const struct mem_type *type;
|
2007-04-21 16:21:28 +07:00
|
|
|
pgd_t *pgd;
|
2006-09-27 21:38:34 +07:00
|
|
|
|
|
|
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
|
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
2006-09-27 21:38:34 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
|
2011-08-25 11:35:59 +07:00
|
|
|
md->virtual >= PAGE_OFFSET &&
|
|
|
|
(md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
|
|
|
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual);
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2007-04-21 16:05:32 +07:00
|
|
|
type = &mem_types[md->type];
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
2006-09-27 21:38:34 +07:00
|
|
|
/*
|
|
|
|
* Catch 36-bit addresses
|
|
|
|
*/
|
2007-04-21 16:16:48 +07:00
|
|
|
if (md->pfn >= 0x100000) {
|
|
|
|
create_36bit_mapping(md, type);
|
|
|
|
return;
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2007-07-05 03:16:33 +07:00
|
|
|
addr = md->virtual & PAGE_MASK;
|
2011-02-15 18:42:57 +07:00
|
|
|
phys = __pfn_to_phys(md->pfn);
|
2007-07-05 03:16:33 +07:00
|
|
|
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2007-04-21 16:21:28 +07:00
|
|
|
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
|
|
|
|
(long long)__pfn_to_phys(md->pfn), addr);
|
2006-09-27 21:38:34 +07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2007-04-21 16:21:28 +07:00
|
|
|
pgd = pgd_offset_k(addr);
|
|
|
|
end = addr + length;
|
|
|
|
do {
|
|
|
|
unsigned long next = pgd_addr_end(addr, end);
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2010-11-21 23:27:49 +07:00
|
|
|
alloc_init_pud(pgd, addr, next, phys, type);
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2007-04-21 16:21:28 +07:00
|
|
|
phys += next - addr;
|
|
|
|
addr = next;
|
|
|
|
} while (pgd++, addr != end);
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create the architecture specific mappings
|
|
|
|
*/
|
|
|
|
void __init iotable_init(struct map_desc *io_desc, int nr)
|
|
|
|
{
|
2011-08-25 11:35:59 +07:00
|
|
|
struct map_desc *md;
|
|
|
|
struct vm_struct *vm;
|
2013-02-09 12:28:06 +07:00
|
|
|
struct static_vm *svm;
|
2011-08-25 11:35:59 +07:00
|
|
|
|
|
|
|
if (!nr)
|
|
|
|
return;
|
2006-09-27 21:38:34 +07:00
|
|
|
|
2013-02-09 12:28:06 +07:00
|
|
|
svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
|
2011-08-25 11:35:59 +07:00
|
|
|
|
|
|
|
for (md = io_desc; nr; md++, nr--) {
|
|
|
|
create_mapping(md);
|
2013-02-09 12:28:06 +07:00
|
|
|
|
|
|
|
vm = &svm->vm;
|
2011-08-25 11:35:59 +07:00
|
|
|
vm->addr = (void *)(md->virtual & PAGE_MASK);
|
|
|
|
vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
|
2012-03-01 07:10:58 +07:00
|
|
|
vm->phys_addr = __pfn_to_phys(md->pfn);
|
|
|
|
vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
|
2011-09-16 12:14:23 +07:00
|
|
|
vm->flags |= VM_ARM_MTYPE(md->type);
|
2011-08-25 11:35:59 +07:00
|
|
|
vm->caller = iotable_init;
|
2013-02-09 12:28:06 +07:00
|
|
|
add_static_vm_early(svm++);
|
2011-08-25 11:35:59 +07:00
|
|
|
}
|
2006-09-27 21:38:34 +07:00
|
|
|
}
|
|
|
|
|
2012-03-01 07:10:58 +07:00
|
|
|
void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
|
|
|
|
void *caller)
|
|
|
|
{
|
|
|
|
struct vm_struct *vm;
|
2013-02-09 12:28:06 +07:00
|
|
|
struct static_vm *svm;
|
|
|
|
|
|
|
|
svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
|
2012-03-01 07:10:58 +07:00
|
|
|
|
2013-02-09 12:28:06 +07:00
|
|
|
vm = &svm->vm;
|
2012-03-01 07:10:58 +07:00
|
|
|
vm->addr = (void *)addr;
|
|
|
|
vm->size = size;
|
2012-09-04 20:01:37 +07:00
|
|
|
vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
|
2012-03-01 07:10:58 +07:00
|
|
|
vm->caller = caller;
|
2013-02-09 12:28:06 +07:00
|
|
|
add_static_vm_early(svm);
|
2012-03-01 07:10:58 +07:00
|
|
|
}
|
|
|
|
|
2012-06-27 23:28:57 +07:00
|
|
|
#ifndef CONFIG_ARM_LPAE
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Linux PMD is made of two consecutive section entries covering 2MB
|
|
|
|
* (see definition in include/asm/pgtable-2level.h). However a call to
|
|
|
|
* create_mapping() may optimize static mappings by using individual
|
|
|
|
* 1MB section mappings. This leaves the actual PMD potentially half
|
|
|
|
* initialized if the top or bottom section entry isn't used, leaving it
|
|
|
|
* open to problems if a subsequent ioremap() or vmalloc() tries to use
|
|
|
|
* the virtual space left free by that unused section entry.
|
|
|
|
*
|
|
|
|
* Let's avoid the issue by inserting dummy vm entries covering the unused
|
|
|
|
* PMD halves once the static mappings are in place.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void __init pmd_empty_section_gap(unsigned long addr)
|
|
|
|
{
|
2012-03-01 07:10:58 +07:00
|
|
|
vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
|
2012-06-27 23:28:57 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init fill_pmd_gaps(void)
|
|
|
|
{
|
2013-02-09 12:28:06 +07:00
|
|
|
struct static_vm *svm;
|
2012-06-27 23:28:57 +07:00
|
|
|
struct vm_struct *vm;
|
|
|
|
unsigned long addr, next = 0;
|
|
|
|
pmd_t *pmd;
|
|
|
|
|
2013-02-09 12:28:06 +07:00
|
|
|
list_for_each_entry(svm, &static_vmlist, list) {
|
|
|
|
vm = &svm->vm;
|
2012-06-27 23:28:57 +07:00
|
|
|
addr = (unsigned long)vm->addr;
|
|
|
|
if (addr < next)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if this vm starts on an odd section boundary.
|
|
|
|
* If so and the first section entry for this PMD is free
|
|
|
|
* then we block the corresponding virtual address.
|
|
|
|
*/
|
|
|
|
if ((addr & ~PMD_MASK) == SECTION_SIZE) {
|
|
|
|
pmd = pmd_off_k(addr);
|
|
|
|
if (pmd_none(*pmd))
|
|
|
|
pmd_empty_section_gap(addr & PMD_MASK);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Then check if this vm ends on an odd section boundary.
|
|
|
|
* If so and the second section entry for this PMD is empty
|
|
|
|
* then we block the corresponding virtual address.
|
|
|
|
*/
|
|
|
|
addr += vm->size;
|
|
|
|
if ((addr & ~PMD_MASK) == SECTION_SIZE) {
|
|
|
|
pmd = pmd_off_k(addr) + 1;
|
|
|
|
if (pmd_none(*pmd))
|
|
|
|
pmd_empty_section_gap(addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* no need to look at any vm entry until we hit the next PMD */
|
|
|
|
next = (addr + PMD_SIZE - 1) & PMD_MASK;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
#define fill_pmd_gaps() do { } while (0)
|
|
|
|
#endif
|
|
|
|
|
2012-03-01 07:10:58 +07:00
|
|
|
#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
|
|
|
|
static void __init pci_reserve_io(void)
|
|
|
|
{
|
2013-02-09 12:28:06 +07:00
|
|
|
struct static_vm *svm;
|
2012-03-01 07:10:58 +07:00
|
|
|
|
2013-02-09 12:28:06 +07:00
|
|
|
svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
|
|
|
|
if (svm)
|
|
|
|
return;
|
2012-03-01 07:10:58 +07:00
|
|
|
|
|
|
|
vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define pci_reserve_io() do { } while (0)
|
|
|
|
#endif
|
|
|
|
|
ARM: implement debug_ll_io_init()
When using DEBUG_LL, the UART's (or other HW's) registers are mapped
into early page tables based on the results of assembly macro addruart.
Later, when the page tables are replaced, the same virtual address must
remain valid. Historically, this has been ensured by using defines from
<mach/iomap.h> in both the implementation of addruart, and the machine's
.map_io() function. However, with the move to single zImage, we wish to
remove <mach/iomap.h>. To enable this, the macro addruart may be used
when constructing the late page tables too; addruart is exposed as a
C function debug_ll_addr(), and used to set up the required mapping in
debug_ll_io_init(), which may called on an opt-in basis from a machine's
.map_io() function.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[swarren: Mask map.virtual with PAGE_MASK. Checked for NULL results from
debug_ll_addr (e.g. when selected UART isn't valid). Fixed compile when
either !CONFIG_DEBUG_LL or CONFIG_DEBUG_SEMIHOSTING.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2012-10-23 00:42:54 +07:00
|
|
|
#ifdef CONFIG_DEBUG_LL
|
|
|
|
void __init debug_ll_io_init(void)
|
|
|
|
{
|
|
|
|
struct map_desc map;
|
|
|
|
|
|
|
|
debug_ll_addr(&map.pfn, &map.virtual);
|
|
|
|
if (!map.pfn || !map.virtual)
|
|
|
|
return;
|
|
|
|
map.pfn = __phys_to_pfn(map.pfn);
|
|
|
|
map.virtual &= PAGE_MASK;
|
|
|
|
map.length = PAGE_SIZE;
|
|
|
|
map.type = MT_DEVICE;
|
2013-07-06 06:25:51 +07:00
|
|
|
iotable_init(&map, 1);
|
ARM: implement debug_ll_io_init()
When using DEBUG_LL, the UART's (or other HW's) registers are mapped
into early page tables based on the results of assembly macro addruart.
Later, when the page tables are replaced, the same virtual address must
remain valid. Historically, this has been ensured by using defines from
<mach/iomap.h> in both the implementation of addruart, and the machine's
.map_io() function. However, with the move to single zImage, we wish to
remove <mach/iomap.h>. To enable this, the macro addruart may be used
when constructing the late page tables too; addruart is exposed as a
C function debug_ll_addr(), and used to set up the required mapping in
debug_ll_io_init(), which may called on an opt-in basis from a machine's
.map_io() function.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[swarren: Mask map.virtual with PAGE_MASK. Checked for NULL results from
debug_ll_addr (e.g. when selected UART isn't valid). Fixed compile when
either !CONFIG_DEBUG_LL or CONFIG_DEBUG_SEMIHOSTING.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2012-10-23 00:42:54 +07:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-08-25 11:35:59 +07:00
|
|
|
static void * __initdata vmalloc_min =
|
|
|
|
(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
|
2008-10-01 01:31:44 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* vmalloc=size forces the vmalloc area to be exactly 'size'
|
|
|
|
* bytes. This can be used to increase (or decrease) the vmalloc
|
2011-08-25 11:35:59 +07:00
|
|
|
* area - the default is 240m.
|
2008-10-01 01:31:44 +07:00
|
|
|
*/
|
2010-01-12 05:17:34 +07:00
|
|
|
static int __init early_vmalloc(char *arg)
|
2008-10-01 01:31:44 +07:00
|
|
|
{
|
2010-05-22 22:20:14 +07:00
|
|
|
unsigned long vmalloc_reserve = memparse(arg, NULL);
|
2008-10-01 01:31:44 +07:00
|
|
|
|
|
|
|
if (vmalloc_reserve < SZ_16M) {
|
|
|
|
vmalloc_reserve = SZ_16M;
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_warn("vmalloc area too small, limiting to %luMB\n",
|
2008-10-01 01:31:44 +07:00
|
|
|
vmalloc_reserve >> 20);
|
|
|
|
}
|
2008-09-19 21:43:06 +07:00
|
|
|
|
|
|
|
if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
|
|
|
|
vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
|
2014-10-28 18:26:42 +07:00
|
|
|
pr_warn("vmalloc area is too big, limiting to %luMB\n",
|
2008-09-19 21:43:06 +07:00
|
|
|
vmalloc_reserve >> 20);
|
|
|
|
}
|
2010-05-22 22:20:14 +07:00
|
|
|
|
|
|
|
vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
|
2010-01-12 05:17:34 +07:00
|
|
|
return 0;
|
2008-10-01 01:31:44 +07:00
|
|
|
}
|
2010-01-12 05:17:34 +07:00
|
|
|
early_param("vmalloc", early_vmalloc);
|
2008-10-01 01:31:44 +07:00
|
|
|
|
2011-12-29 19:09:51 +07:00
|
|
|
phys_addr_t arm_lowmem_limit __initdata = 0;
|
2010-10-28 01:57:38 +07:00
|
|
|
|
2011-07-06 01:58:29 +07:00
|
|
|
void __init sanity_check_meminfo(void)
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 06:56:13 +07:00
|
|
|
{
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
phys_addr_t memblock_limit = 0;
|
2014-04-14 04:54:58 +07:00
|
|
|
int highmem = 0;
|
2012-07-20 23:01:23 +07:00
|
|
|
phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
|
2014-04-14 04:54:58 +07:00
|
|
|
struct memblock_region *reg;
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 06:56:13 +07:00
|
|
|
|
2014-04-14 04:54:58 +07:00
|
|
|
for_each_memblock(memory, reg) {
|
|
|
|
phys_addr_t block_start = reg->base;
|
|
|
|
phys_addr_t block_end = reg->base + reg->size;
|
|
|
|
phys_addr_t size_limit = reg->size;
|
2011-11-23 00:30:32 +07:00
|
|
|
|
2014-04-14 04:54:58 +07:00
|
|
|
if (reg->base >= vmalloc_limit)
|
ARM: Fix broken highmem support
Currently, highmem is selectable, and you can request an increased
vmalloc area. However, none of this has any effect on the memory
layout since a patch in the highmem series was accidentally dropped.
Moreover, even if you did want highmem, all memory would still be
registered as lowmem, possibly resulting in overflow of the available
virtual mapping space.
The highmem boundary is determined by the highest allowed beginning
of the vmalloc area, which depends on its configurable minimum size
(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on
this).
We should create mappings and initialize bootmem only for low memory,
while the zone allocator must still be told about highmem.
Currently, memory nodes which are completely located in high memory
are not supported. This is not a huge limitation since systems
relying on highmem support are unlikely to have discontiguous memory
with large holes.
[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3
and be available in Linux v2.6.30, however some git rebase screw-up
of mine dropped the first commit of the series, and that goofage
escaped testing somehow as well. -- Nico ]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
2009-08-15 18:36:00 +07:00
|
|
|
highmem = 1;
|
2012-07-21 00:16:41 +07:00
|
|
|
else
|
2014-04-14 04:54:58 +07:00
|
|
|
size_limit = vmalloc_limit - reg->base;
|
ARM: Fix broken highmem support
Currently, highmem is selectable, and you can request an increased
vmalloc area. However, none of this has any effect on the memory
layout since a patch in the highmem series was accidentally dropped.
Moreover, even if you did want highmem, all memory would still be
registered as lowmem, possibly resulting in overflow of the available
virtual mapping space.
The highmem boundary is determined by the highest allowed beginning
of the vmalloc area, which depends on its configurable minimum size
(see commit 60296c71f6c5063e3c1f1d2619ca0b60940162e7 for details on
this).
We should create mappings and initialize bootmem only for low memory,
while the zone allocator must still be told about highmem.
Currently, memory nodes which are completely located in high memory
are not supported. This is not a huge limitation since systems
relying on highmem support are unlikely to have discontiguous memory
with large holes.
[ A similar patch was meant to be merged before commit 5f0fbf9ecaf3
and be available in Linux v2.6.30, however some git rebase screw-up
of mine dropped the first commit of the series, and that goofage
escaped testing somehow as well. -- Nico ]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
2009-08-15 18:36:00 +07:00
|
|
|
|
|
|
|
|
2014-04-14 04:54:58 +07:00
|
|
|
if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
|
|
|
|
|
|
|
|
if (highmem) {
|
|
|
|
pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
|
2014-10-28 18:26:42 +07:00
|
|
|
&block_start, &block_end);
|
2014-04-14 04:54:58 +07:00
|
|
|
memblock_remove(reg->base, reg->size);
|
|
|
|
continue;
|
2008-09-02 22:44:21 +07:00
|
|
|
}
|
2011-11-23 00:30:32 +07:00
|
|
|
|
2014-04-14 04:54:58 +07:00
|
|
|
if (reg->size > size_limit) {
|
|
|
|
phys_addr_t overlap_size = reg->size - size_limit;
|
|
|
|
|
|
|
|
pr_notice("Truncating RAM at %pa-%pa to -%pa",
|
2014-10-28 18:26:42 +07:00
|
|
|
&block_start, &block_end, &vmalloc_limit);
|
2014-04-14 04:54:58 +07:00
|
|
|
memblock_remove(vmalloc_limit, overlap_size);
|
|
|
|
block_end = vmalloc_limit;
|
|
|
|
}
|
2008-09-02 22:44:21 +07:00
|
|
|
}
|
2011-05-19 19:22:48 +07:00
|
|
|
|
2014-04-14 04:54:58 +07:00
|
|
|
if (!highmem) {
|
|
|
|
if (block_end > arm_lowmem_limit) {
|
|
|
|
if (reg->size > size_limit)
|
|
|
|
arm_lowmem_limit = vmalloc_limit;
|
|
|
|
else
|
|
|
|
arm_lowmem_limit = block_end;
|
|
|
|
}
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
|
|
|
|
/*
|
2015-05-13 21:07:54 +07:00
|
|
|
* Find the first non-pmd-aligned page, and point
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
* memblock_limit at it. This relies on rounding the
|
2015-05-13 21:07:54 +07:00
|
|
|
* limit down to be pmd-aligned, which happens at the
|
|
|
|
* end of this function.
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
*
|
|
|
|
* With this algorithm, the start or end of almost any
|
2015-05-13 21:07:54 +07:00
|
|
|
* bank can be non-pmd-aligned. The only exception is
|
|
|
|
* that the start of the bank 0 must be section-
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
* aligned, since otherwise memory would need to be
|
|
|
|
* allocated when mapping the start of bank 0, which
|
|
|
|
* occurs before any free memory is mapped.
|
|
|
|
*/
|
|
|
|
if (!memblock_limit) {
|
2015-05-13 21:07:54 +07:00
|
|
|
if (!IS_ALIGNED(block_start, PMD_SIZE))
|
2014-04-14 04:54:58 +07:00
|
|
|
memblock_limit = block_start;
|
2015-05-13 21:07:54 +07:00
|
|
|
else if (!IS_ALIGNED(block_end, PMD_SIZE))
|
2014-04-14 04:54:58 +07:00
|
|
|
memblock_limit = arm_lowmem_limit;
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
}
|
2009-09-28 02:55:43 +07:00
|
|
|
|
|
|
|
}
|
|
|
|
}
|
2014-04-14 04:54:58 +07:00
|
|
|
|
2011-12-29 19:09:51 +07:00
|
|
|
high_memory = __va(arm_lowmem_limit - 1) + 1;
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
|
|
|
|
/*
|
2015-05-13 21:07:54 +07:00
|
|
|
* Round the memblock limit down to a pmd size. This
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
* helps to ensure that we will allocate memory from the
|
2015-05-13 21:07:54 +07:00
|
|
|
* last full pmd, which should be mapped.
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
*/
|
|
|
|
if (memblock_limit)
|
2015-05-13 21:07:54 +07:00
|
|
|
memblock_limit = round_down(memblock_limit, PMD_SIZE);
|
ARM: 7785/1: mm: restrict early_alloc to section-aligned memory
When map_lowmem() runs, and processes a memory bank whose start or end
is not section-aligned, memory must be allocated to store the 2nd-level
page tables. Those allocations are made by calling memblock_alloc().
At this point, the only memory that is free *and* mapped is memory which
has already been mapped by map_lowmem() itself. For this reason, we must
calculate the first point at which map_lowmem() will need to allocate
memory, and set the memblock allocation limit to a lower address, so that
memblock_alloc() is guaranteed to return memory that is already mapped.
This patch enhances sanity_check_meminfo() to calculate that memory
address, and pass it to memblock_set_current_limit(), rather than just
assuming the limit is arm_lowmem_limit.
The algorithm applied is:
* Default memblock_limit to arm_lowmem_limit in the absence of any other
limit; arm_lowmem_limit is the highest memory that is mapped by
map_lowmem().
* While walking the list of memblocks, if the start of a block is not
aligned, 2nd-level page tables will need to be allocated to map the
first few pages of the block. Hence, the memblock_limit must be before
the start of the block.
* Similarly, if the end of any block is not aligned, 2nd-level page
tables will need to be allocated to map the last few pages of the
block. Hence, the memblock_limit must point at the end of the block,
rounded down to section-alignment.
* The memory blocks are assumed to be sorted in address order, so the
first unaligned block start or end is used to set the limit.
With this algorithm, the start or end of almost any bank can be non-
section-aligned. The only exception is that the start of bank 0 must
be section-aligned, since otherwise memory would need to be allocated
when mapping the start of bank 0, which occurs before any free memory
is mapped.
[swarren, wrote commit description, rewrote calculation of memblock_limit]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-07-17 23:53:04 +07:00
|
|
|
if (!memblock_limit)
|
|
|
|
memblock_limit = arm_lowmem_limit;
|
|
|
|
|
|
|
|
memblock_set_current_limit(memblock_limit);
|
[ARM] prevent crashing when too much RAM installed
This patch will truncate and/or ignore memory banks if their kernel
direct mappings would (partially) overlap with the vmalloc area or
the mappings between the vmalloc area and the address space top, to
prevent crashing during early boot if there happens to be more RAM
installed than we are expecting.
Since the start of the vmalloc area is not at a fixed address (but
the vmalloc end address is, via the per-platform VMALLOC_END define),
a default area of 128M is reserved for vmalloc mappings, which can
be shrunk or enlarged by passing an appropriate vmalloc= command line
option as it is done on x86.
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe000000,
two 512M RAM banks and vmalloc=128M (the default), this patch gives:
Truncating RAM at 20000000-3fffffff to -35ffffff (vmalloc region overlap).
Memory: 512MB 352MB = 864MB total
On a board with a 3:1 user:kernel split, VMALLOC_END at 0xfe800000,
two 256M RAM banks and vmalloc=768M, this patch gives:
Truncating RAM at 00000000-0fffffff to -0e7fffff (vmalloc region overlap).
Ignoring RAM at 10000000-1fffffff (vmalloc region overlap).
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Tested-by: Riku Voipio <riku.voipio@iki.fi>
2008-08-05 06:56:13 +07:00
|
|
|
}
|
|
|
|
|
2008-10-07 00:24:40 +07:00
|
|
|
static inline void prepare_page_table(void)
|
2006-09-27 21:27:33 +07:00
|
|
|
{
|
|
|
|
unsigned long addr;
|
2010-10-28 01:57:38 +07:00
|
|
|
phys_addr_t end;
|
2006-09-27 21:27:33 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear out all the mappings below the kernel image.
|
|
|
|
*/
|
2011-08-23 20:07:23 +07:00
|
|
|
for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
|
2006-09-27 21:27:33 +07:00
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
|
|
/* The XIP kernel is mapped in the module area -- skip over it */
|
2011-08-23 20:07:23 +07:00
|
|
|
addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
|
2006-09-27 21:27:33 +07:00
|
|
|
#endif
|
2011-08-23 20:07:23 +07:00
|
|
|
for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
|
2006-09-27 21:27:33 +07:00
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
2010-10-28 01:57:38 +07:00
|
|
|
/*
|
|
|
|
* Find the end of the first block of lowmem.
|
|
|
|
*/
|
|
|
|
end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
|
2011-12-29 19:09:51 +07:00
|
|
|
if (end >= arm_lowmem_limit)
|
|
|
|
end = arm_lowmem_limit;
|
2010-10-28 01:57:38 +07:00
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
/*
|
|
|
|
* Clear out all the kernel space mappings, except for the first
|
2011-08-25 11:35:59 +07:00
|
|
|
* memory bank, up to the vmalloc region.
|
2006-09-27 21:27:33 +07:00
|
|
|
*/
|
2010-10-28 01:57:38 +07:00
|
|
|
for (addr = __phys_to_virt(end);
|
2011-08-25 11:35:59 +07:00
|
|
|
addr < VMALLOC_START; addr += PMD_SIZE)
|
2006-09-27 21:27:33 +07:00
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
}
|
|
|
|
|
2011-11-23 00:30:29 +07:00
|
|
|
#ifdef CONFIG_ARM_LPAE
|
|
|
|
/* the first page is reserved for pgd */
|
|
|
|
#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
|
|
|
|
PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
|
|
|
|
#else
|
2011-08-23 20:07:23 +07:00
|
|
|
#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
|
2011-11-23 00:30:29 +07:00
|
|
|
#endif
|
2011-08-23 20:07:23 +07:00
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
/*
|
2010-07-09 22:27:52 +07:00
|
|
|
* Reserve the special regions of memory
|
2006-09-27 21:27:33 +07:00
|
|
|
*/
|
2010-07-09 22:27:52 +07:00
|
|
|
void __init arm_mm_memblock_reserve(void)
|
2006-09-27 21:27:33 +07:00
|
|
|
{
|
|
|
|
/*
|
|
|
|
* Reserve the page tables. These are already in use,
|
|
|
|
* and can only be in node 0.
|
|
|
|
*/
|
2011-08-23 20:07:23 +07:00
|
|
|
memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
|
2006-09-27 21:27:33 +07:00
|
|
|
|
|
|
|
#ifdef CONFIG_SA1111
|
|
|
|
/*
|
|
|
|
* Because of the SA1111 DMA bug, we want to preserve our
|
|
|
|
* precious DMA-able memory...
|
|
|
|
*/
|
2010-07-09 22:27:52 +07:00
|
|
|
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
|
2006-09-27 21:27:33 +07:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
2011-08-25 11:35:59 +07:00
|
|
|
* Set up the device mappings. Since we clear out the page tables for all
|
|
|
|
* mappings above VMALLOC_START, we will remove any debug device mappings.
|
2006-09-27 21:27:33 +07:00
|
|
|
* This means you have to be careful how you debug this function, or any
|
|
|
|
* called function. This means you can't use any function or debugging
|
|
|
|
* method which may touch any device, otherwise the kernel _will_ crash.
|
|
|
|
*/
|
2013-07-26 20:55:59 +07:00
|
|
|
static void __init devicemaps_init(const struct machine_desc *mdesc)
|
2006-09-27 21:27:33 +07:00
|
|
|
{
|
|
|
|
struct map_desc map;
|
|
|
|
unsigned long addr;
|
2012-01-18 22:32:49 +07:00
|
|
|
void *vectors;
|
2006-09-27 21:27:33 +07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Allocate the vector page early.
|
|
|
|
*/
|
2013-07-04 17:40:32 +07:00
|
|
|
vectors = early_alloc(PAGE_SIZE * 2);
|
2012-01-18 22:32:49 +07:00
|
|
|
|
|
|
|
early_trap_init(vectors);
|
2006-09-27 21:27:33 +07:00
|
|
|
|
2011-08-25 11:35:59 +07:00
|
|
|
for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
|
2006-09-27 21:27:33 +07:00
|
|
|
pmd_clear(pmd_off_k(addr));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the kernel if it is XIP.
|
|
|
|
* It is always first in the modulearea.
|
|
|
|
*/
|
|
|
|
#ifdef CONFIG_XIP_KERNEL
|
|
|
|
map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
|
2008-11-07 00:11:07 +07:00
|
|
|
map.virtual = MODULES_VADDR;
|
2008-12-01 18:53:07 +07:00
|
|
|
map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
|
2006-09-27 21:27:33 +07:00
|
|
|
map.type = MT_ROM;
|
|
|
|
create_mapping(&map);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Map the cache flushing regions.
|
|
|
|
*/
|
|
|
|
#ifdef FLUSH_BASE
|
|
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
|
|
|
|
map.virtual = FLUSH_BASE;
|
|
|
|
map.length = SZ_1M;
|
|
|
|
map.type = MT_CACHECLEAN;
|
|
|
|
create_mapping(&map);
|
|
|
|
#endif
|
|
|
|
#ifdef FLUSH_BASE_MINICACHE
|
|
|
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
|
|
|
|
map.virtual = FLUSH_BASE_MINICACHE;
|
|
|
|
map.length = SZ_1M;
|
|
|
|
map.type = MT_MINICLEAN;
|
|
|
|
create_mapping(&map);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Create a mapping for the machine vectors at the high-vectors
|
|
|
|
* location (0xffff0000). If we aren't using high-vectors, also
|
|
|
|
* create a mapping at the low-vectors virtual address.
|
|
|
|
*/
|
2012-01-18 22:32:49 +07:00
|
|
|
map.pfn = __phys_to_pfn(virt_to_phys(vectors));
|
2006-09-27 21:27:33 +07:00
|
|
|
map.virtual = 0xffff0000;
|
|
|
|
map.length = PAGE_SIZE;
|
2013-08-01 03:58:56 +07:00
|
|
|
#ifdef CONFIG_KUSER_HELPERS
|
2006-09-27 21:27:33 +07:00
|
|
|
map.type = MT_HIGH_VECTORS;
|
2013-08-01 03:58:56 +07:00
|
|
|
#else
|
|
|
|
map.type = MT_LOW_VECTORS;
|
|
|
|
#endif
|
2006-09-27 21:27:33 +07:00
|
|
|
create_mapping(&map);
|
|
|
|
|
|
|
|
if (!vectors_high()) {
|
|
|
|
map.virtual = 0;
|
2013-07-04 17:40:32 +07:00
|
|
|
map.length = PAGE_SIZE * 2;
|
2006-09-27 21:27:33 +07:00
|
|
|
map.type = MT_LOW_VECTORS;
|
|
|
|
create_mapping(&map);
|
|
|
|
}
|
|
|
|
|
2013-07-04 17:40:32 +07:00
|
|
|
/* Now create a kernel read-only mapping */
|
|
|
|
map.pfn += 1;
|
|
|
|
map.virtual = 0xffff0000 + PAGE_SIZE;
|
|
|
|
map.length = PAGE_SIZE;
|
|
|
|
map.type = MT_LOW_VECTORS;
|
|
|
|
create_mapping(&map);
|
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
/*
|
|
|
|
* Ask the machine support to map in the statically mapped devices.
|
|
|
|
*/
|
|
|
|
if (mdesc->map_io)
|
|
|
|
mdesc->map_io();
|
2013-04-19 02:52:23 +07:00
|
|
|
else
|
|
|
|
debug_ll_io_init();
|
2012-06-27 23:28:57 +07:00
|
|
|
fill_pmd_gaps();
|
2006-09-27 21:27:33 +07:00
|
|
|
|
2012-03-01 07:10:58 +07:00
|
|
|
/* Reserve fixed i/o space in VMALLOC region */
|
|
|
|
pci_reserve_io();
|
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
/*
|
|
|
|
* Finally flush the caches and tlb to ensure that we're in a
|
|
|
|
* consistent state wrt the writebuffer. This also ensures that
|
|
|
|
* any write-allocated cache lines in the vector page are written
|
|
|
|
* back. After this point, we can start to touch devices again.
|
|
|
|
*/
|
|
|
|
local_flush_tlb_all();
|
|
|
|
flush_cache_all();
|
|
|
|
}
|
|
|
|
|
2008-09-16 03:44:55 +07:00
|
|
|
static void __init kmap_init(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_HIGHMEM
|
2010-07-02 00:33:29 +07:00
|
|
|
pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
|
|
|
|
PKMAP_BASE, _PAGE_KERNEL_TABLE);
|
2008-09-16 03:44:55 +07:00
|
|
|
#endif
|
2014-07-02 14:01:15 +07:00
|
|
|
|
|
|
|
early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
|
|
|
|
_PAGE_KERNEL_TABLE);
|
2008-09-16 03:44:55 +07:00
|
|
|
}
|
|
|
|
|
2010-03-26 01:56:05 +07:00
|
|
|
static void __init map_lowmem(void)
|
|
|
|
{
|
2010-10-28 01:57:38 +07:00
|
|
|
struct memblock_region *reg;
|
2014-12-24 01:36:55 +07:00
|
|
|
phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
|
|
|
|
phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
|
2010-03-26 01:56:05 +07:00
|
|
|
|
|
|
|
/* Map all the lowmem memory banks. */
|
2010-10-28 01:57:38 +07:00
|
|
|
for_each_memblock(memory, reg) {
|
|
|
|
phys_addr_t start = reg->base;
|
|
|
|
phys_addr_t end = start + reg->size;
|
|
|
|
struct map_desc map;
|
|
|
|
|
2011-12-29 19:09:51 +07:00
|
|
|
if (end > arm_lowmem_limit)
|
|
|
|
end = arm_lowmem_limit;
|
2010-10-28 01:57:38 +07:00
|
|
|
if (start >= end)
|
|
|
|
break;
|
|
|
|
|
2014-04-04 07:28:11 +07:00
|
|
|
if (end < kernel_x_start) {
|
2013-10-24 14:12:39 +07:00
|
|
|
map.pfn = __phys_to_pfn(start);
|
|
|
|
map.virtual = __phys_to_virt(start);
|
|
|
|
map.length = end - start;
|
|
|
|
map.type = MT_MEMORY_RWX;
|
2010-03-26 01:56:05 +07:00
|
|
|
|
2014-04-04 07:28:11 +07:00
|
|
|
create_mapping(&map);
|
|
|
|
} else if (start >= kernel_x_end) {
|
|
|
|
map.pfn = __phys_to_pfn(start);
|
|
|
|
map.virtual = __phys_to_virt(start);
|
|
|
|
map.length = end - start;
|
|
|
|
map.type = MT_MEMORY_RW;
|
|
|
|
|
2013-10-24 14:12:39 +07:00
|
|
|
create_mapping(&map);
|
|
|
|
} else {
|
|
|
|
/* This better cover the entire kernel */
|
|
|
|
if (start < kernel_x_start) {
|
|
|
|
map.pfn = __phys_to_pfn(start);
|
|
|
|
map.virtual = __phys_to_virt(start);
|
|
|
|
map.length = kernel_x_start - start;
|
|
|
|
map.type = MT_MEMORY_RW;
|
|
|
|
|
|
|
|
create_mapping(&map);
|
|
|
|
}
|
|
|
|
|
|
|
|
map.pfn = __phys_to_pfn(kernel_x_start);
|
|
|
|
map.virtual = __phys_to_virt(kernel_x_start);
|
|
|
|
map.length = kernel_x_end - kernel_x_start;
|
|
|
|
map.type = MT_MEMORY_RWX;
|
|
|
|
|
|
|
|
create_mapping(&map);
|
|
|
|
|
|
|
|
if (kernel_x_end < end) {
|
|
|
|
map.pfn = __phys_to_pfn(kernel_x_end);
|
|
|
|
map.virtual = __phys_to_virt(kernel_x_end);
|
|
|
|
map.length = end - kernel_x_end;
|
|
|
|
map.type = MT_MEMORY_RW;
|
|
|
|
|
|
|
|
create_mapping(&map);
|
|
|
|
}
|
|
|
|
}
|
2010-03-26 01:56:05 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-04-04 22:58:38 +07:00
|
|
|
#ifdef CONFIG_ARM_PV_FIXUP
|
|
|
|
extern unsigned long __atags_pointer;
|
|
|
|
typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
|
|
|
|
pgtables_remap lpae_pgtables_remap_asm;
|
|
|
|
|
2013-07-31 23:44:46 +07:00
|
|
|
/*
|
|
|
|
* early_paging_init() recreates boot time page table setup, allowing machines
|
|
|
|
* to switch over to a high (>4G) address space on LPAE systems
|
|
|
|
*/
|
2015-04-04 23:25:20 +07:00
|
|
|
void __init early_paging_init(const struct machine_desc *mdesc)
|
2013-07-31 23:44:46 +07:00
|
|
|
{
|
2015-04-04 22:58:38 +07:00
|
|
|
pgtables_remap *lpae_pgtables_remap;
|
|
|
|
unsigned long pa_pgd;
|
|
|
|
unsigned int cr, ttbcr;
|
2015-04-04 15:53:38 +07:00
|
|
|
long long offset;
|
2015-04-04 22:58:38 +07:00
|
|
|
void *boot_data;
|
2013-07-31 23:44:46 +07:00
|
|
|
|
2015-04-04 16:01:10 +07:00
|
|
|
if (!mdesc->pv_fixup)
|
2013-07-31 23:44:46 +07:00
|
|
|
return;
|
|
|
|
|
2015-04-04 16:01:10 +07:00
|
|
|
offset = mdesc->pv_fixup();
|
2015-04-04 15:53:38 +07:00
|
|
|
if (offset == 0)
|
|
|
|
return;
|
2013-07-31 23:44:46 +07:00
|
|
|
|
2015-04-04 22:58:38 +07:00
|
|
|
/*
|
|
|
|
* Get the address of the remap function in the 1:1 identity
|
|
|
|
* mapping setup by the early page table assembly code. We
|
|
|
|
* must get this prior to the pv update. The following barrier
|
|
|
|
* ensures that this is complete before we fixup any P:V offsets.
|
|
|
|
*/
|
|
|
|
lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
|
|
|
|
pa_pgd = __pa(swapper_pg_dir);
|
|
|
|
boot_data = __va(__atags_pointer);
|
|
|
|
barrier();
|
2013-07-31 23:44:46 +07:00
|
|
|
|
2015-04-04 16:25:28 +07:00
|
|
|
pr_info("Switching physical address space to 0x%08llx\n",
|
|
|
|
(u64)PHYS_OFFSET + offset);
|
2013-07-31 23:44:46 +07:00
|
|
|
|
2015-04-04 15:53:38 +07:00
|
|
|
/* Re-set the phys pfn offset, and the pv offset */
|
|
|
|
__pv_offset += offset;
|
|
|
|
__pv_phys_pfn_offset += PFN_DOWN(offset);
|
2013-07-31 23:44:46 +07:00
|
|
|
|
|
|
|
/* Run the patch stub to update the constants */
|
|
|
|
fixup_pv_table(&__pv_table_begin,
|
|
|
|
(&__pv_table_end - &__pv_table_begin) << 2);
|
|
|
|
|
|
|
|
/*
|
2015-04-04 22:58:38 +07:00
|
|
|
* We changing not only the virtual to physical mapping, but also
|
|
|
|
* the physical addresses used to access memory. We need to flush
|
|
|
|
* all levels of cache in the system with caching disabled to
|
|
|
|
* ensure that all data is written back, and nothing is prefetched
|
|
|
|
* into the caches. We also need to prevent the TLB walkers
|
|
|
|
* allocating into the caches too. Note that this is ARMv7 LPAE
|
|
|
|
* specific.
|
2014-07-29 15:27:13 +07:00
|
|
|
*/
|
2015-04-04 22:58:38 +07:00
|
|
|
cr = get_cr();
|
|
|
|
set_cr(cr & ~(CR_I | CR_C));
|
|
|
|
asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
|
|
|
|
asm volatile("mcr p15, 0, %0, c2, c0, 2"
|
|
|
|
: : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
|
2013-07-31 23:44:46 +07:00
|
|
|
flush_cache_all();
|
2014-07-29 15:27:13 +07:00
|
|
|
|
|
|
|
/*
|
2015-04-04 22:58:38 +07:00
|
|
|
* Fixup the page tables - this must be in the idmap region as
|
|
|
|
* we need to disable the MMU to do this safely, and hence it
|
|
|
|
* needs to be assembly. It's fairly simple, as we're using the
|
|
|
|
* temporary tables setup by the initial assembly code.
|
2014-07-29 15:27:13 +07:00
|
|
|
*/
|
2015-04-04 22:58:38 +07:00
|
|
|
lpae_pgtables_remap(offset, pa_pgd, boot_data);
|
2014-07-29 15:27:13 +07:00
|
|
|
|
2015-04-04 22:58:38 +07:00
|
|
|
/* Re-enable the caches and cacheable TLB walks */
|
|
|
|
asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
|
|
|
|
set_cr(cr);
|
2013-07-31 23:44:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
2015-04-04 23:25:20 +07:00
|
|
|
void __init early_paging_init(const struct machine_desc *mdesc)
|
2013-07-31 23:44:46 +07:00
|
|
|
{
|
2015-04-04 15:53:38 +07:00
|
|
|
long long offset;
|
|
|
|
|
2015-04-04 16:01:10 +07:00
|
|
|
if (!mdesc->pv_fixup)
|
2015-04-04 15:53:38 +07:00
|
|
|
return;
|
|
|
|
|
2015-04-04 16:01:10 +07:00
|
|
|
offset = mdesc->pv_fixup();
|
2015-04-04 15:53:38 +07:00
|
|
|
if (offset == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
pr_crit("Physical address space modification is only to support Keystone2.\n");
|
|
|
|
pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
|
|
|
|
pr_crit("feature. Your kernel may crash now, have a good day.\n");
|
|
|
|
add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
|
2013-07-31 23:44:46 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
/*
|
|
|
|
* paging_init() sets up the page tables, initialises the zone memory
|
|
|
|
* maps, and sets up the zero page, bad page and bad page tables.
|
|
|
|
*/
|
2013-07-26 20:55:59 +07:00
|
|
|
void __init paging_init(const struct machine_desc *mdesc)
|
2006-09-27 21:27:33 +07:00
|
|
|
{
|
|
|
|
void *zero_page;
|
|
|
|
|
|
|
|
build_mem_type_table();
|
2008-10-07 00:24:40 +07:00
|
|
|
prepare_page_table();
|
2010-03-26 01:56:05 +07:00
|
|
|
map_lowmem();
|
2011-12-29 19:09:51 +07:00
|
|
|
dma_contiguous_remap();
|
2006-09-27 21:27:33 +07:00
|
|
|
devicemaps_init(mdesc);
|
2008-09-16 03:44:55 +07:00
|
|
|
kmap_init();
|
2013-04-05 09:16:51 +07:00
|
|
|
tcm_init();
|
2006-09-27 21:27:33 +07:00
|
|
|
|
|
|
|
top_pmd = pmd_off_k(0xffff0000);
|
|
|
|
|
2010-03-26 00:02:59 +07:00
|
|
|
/* allocate the zero page. */
|
|
|
|
zero_page = early_alloc(PAGE_SIZE);
|
2010-07-09 22:27:52 +07:00
|
|
|
|
2010-05-23 01:47:18 +07:00
|
|
|
bootmem_init();
|
2010-07-09 22:27:52 +07:00
|
|
|
|
2006-09-27 21:27:33 +07:00
|
|
|
empty_zero_page = virt_to_page(zero_page);
|
2009-10-25 17:23:04 +07:00
|
|
|
__flush_dcache_page(NULL, empty_zero_page);
|
2006-09-27 21:27:33 +07:00
|
|
|
}
|