2006-11-09 20:51:17 +07:00
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/*
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2011-11-08 17:12:32 +07:00
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* Cadence MACB/GEM Ethernet Controller driver
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2006-11-09 20:51:17 +07:00
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*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2011-03-09 03:27:08 +07:00
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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2006-11-09 20:51:17 +07:00
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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2012-11-19 13:00:21 +07:00
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#include <linux/circ_buf.h>
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2006-11-09 20:51:17 +07:00
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#include <linux/slab.h>
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#include <linux/init.h>
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2013-12-11 07:07:21 +07:00
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#include <linux/io.h>
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2012-11-11 20:56:27 +07:00
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#include <linux/gpio.h>
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2011-06-06 17:43:46 +07:00
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#include <linux/interrupt.h>
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2006-11-09 20:51:17 +07:00
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/dma-mapping.h>
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2011-03-09 03:17:06 +07:00
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#include <linux/platform_data/macb.h>
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2006-11-09 20:51:17 +07:00
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#include <linux/platform_device.h>
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2007-07-13 00:07:24 +07:00
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#include <linux/phy.h>
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2011-12-21 04:13:07 +07:00
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#include <linux/of.h>
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2011-11-18 21:29:25 +07:00
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#include <linux/of_device.h>
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2013-08-22 22:57:28 +07:00
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#include <linux/of_mdio.h>
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2011-11-18 21:29:25 +07:00
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#include <linux/of_net.h>
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2006-11-09 20:51:17 +07:00
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#include "macb.h"
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2013-06-05 04:57:11 +07:00
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#define MACB_RX_BUFFER_SIZE 128
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#define RX_BUFFER_MULTIPLE 64 /* bytes */
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2012-10-31 13:04:55 +07:00
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#define RX_RING_SIZE 512 /* must be power of 2 */
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#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
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2006-11-09 20:51:17 +07:00
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2012-10-31 13:04:55 +07:00
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#define TX_RING_SIZE 128 /* must be power of 2 */
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#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
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2006-11-09 20:51:17 +07:00
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2012-11-19 13:00:21 +07:00
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/* level of occupied TX descriptors under which we wake up TX process */
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#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
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2006-11-09 20:51:17 +07:00
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#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
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| MACB_BIT(ISR_ROVR))
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2012-10-31 13:04:57 +07:00
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#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
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| MACB_BIT(ISR_RLE) \
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| MACB_BIT(TXERR))
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#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
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2014-07-24 18:50:59 +07:00
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#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
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#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
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2012-10-31 13:04:57 +07:00
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/*
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* Graceful stop timeouts in us. We should allow up to
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* 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
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*/
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#define MACB_HALT_TIMEOUT 1230
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2006-11-09 20:51:17 +07:00
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2012-10-31 13:04:55 +07:00
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/* Ring buffer accessors */
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static unsigned int macb_tx_ring_wrap(unsigned int index)
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{
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return index & (TX_RING_SIZE - 1);
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}
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
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unsigned int index)
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2012-10-31 13:04:55 +07:00
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{
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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return &queue->tx_ring[macb_tx_ring_wrap(index)];
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2012-10-31 13:04:55 +07:00
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}
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
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unsigned int index)
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2012-10-31 13:04:55 +07:00
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{
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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return &queue->tx_skb[macb_tx_ring_wrap(index)];
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2012-10-31 13:04:55 +07:00
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}
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
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2012-10-31 13:04:55 +07:00
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{
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dma_addr_t offset;
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offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
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net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
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return queue->tx_ring_dma + offset;
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2012-10-31 13:04:55 +07:00
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}
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static unsigned int macb_rx_ring_wrap(unsigned int index)
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{
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return index & (RX_RING_SIZE - 1);
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}
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static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
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{
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return &bp->rx_ring[macb_rx_ring_wrap(index)];
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}
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static void *macb_rx_buffer(struct macb *bp, unsigned int index)
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{
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2013-06-05 04:57:11 +07:00
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return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
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2012-10-31 13:04:55 +07:00
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}
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2015-03-07 13:23:32 +07:00
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static void macb_set_hwaddr(struct macb *bp)
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2006-11-09 20:51:17 +07:00
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{
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u32 bottom;
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u16 top;
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bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
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2011-11-08 17:12:32 +07:00
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macb_or_gem_writel(bp, SA1B, bottom);
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2006-11-09 20:51:17 +07:00
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top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
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2011-11-08 17:12:32 +07:00
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|
|
macb_or_gem_writel(bp, SA1T, top);
|
2012-11-11 20:56:28 +07:00
|
|
|
|
|
|
|
|
/* Clear unused address register sets */
|
|
|
|
|
macb_or_gem_writel(bp, SA2B, 0);
|
|
|
|
|
macb_or_gem_writel(bp, SA2T, 0);
|
|
|
|
|
macb_or_gem_writel(bp, SA3B, 0);
|
|
|
|
|
macb_or_gem_writel(bp, SA3T, 0);
|
|
|
|
|
macb_or_gem_writel(bp, SA4B, 0);
|
|
|
|
|
macb_or_gem_writel(bp, SA4T, 0);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static void macb_get_hwaddr(struct macb *bp)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2012-11-07 15:14:51 +07:00
|
|
|
struct macb_platform_data *pdata;
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 bottom;
|
|
|
|
|
u16 top;
|
|
|
|
|
u8 addr[6];
|
2012-11-07 15:14:50 +07:00
|
|
|
int i;
|
|
|
|
|
|
2013-08-30 12:12:21 +07:00
|
|
|
pdata = dev_get_platdata(&bp->pdev->dev);
|
2012-11-07 15:14:51 +07:00
|
|
|
|
2012-11-07 15:14:50 +07:00
|
|
|
/* Check all 4 address register for vaild address */
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
bottom = macb_or_gem_readl(bp, SA1B + i * 8);
|
|
|
|
|
top = macb_or_gem_readl(bp, SA1T + i * 8);
|
|
|
|
|
|
2012-11-07 15:14:51 +07:00
|
|
|
if (pdata && pdata->rev_eth_addr) {
|
|
|
|
|
addr[5] = bottom & 0xff;
|
|
|
|
|
addr[4] = (bottom >> 8) & 0xff;
|
|
|
|
|
addr[3] = (bottom >> 16) & 0xff;
|
|
|
|
|
addr[2] = (bottom >> 24) & 0xff;
|
|
|
|
|
addr[1] = top & 0xff;
|
|
|
|
|
addr[0] = (top & 0xff00) >> 8;
|
|
|
|
|
} else {
|
|
|
|
|
addr[0] = bottom & 0xff;
|
|
|
|
|
addr[1] = (bottom >> 8) & 0xff;
|
|
|
|
|
addr[2] = (bottom >> 16) & 0xff;
|
|
|
|
|
addr[3] = (bottom >> 24) & 0xff;
|
|
|
|
|
addr[4] = top & 0xff;
|
|
|
|
|
addr[5] = (top >> 8) & 0xff;
|
|
|
|
|
}
|
2012-11-07 15:14:50 +07:00
|
|
|
|
|
|
|
|
if (is_valid_ether_addr(addr)) {
|
|
|
|
|
memcpy(bp->dev->dev_addr, addr, sizeof(addr));
|
|
|
|
|
return;
|
|
|
|
|
}
|
2008-06-10 06:33:57 +07:00
|
|
|
}
|
2012-11-07 15:14:50 +07:00
|
|
|
|
|
|
|
|
netdev_info(bp->dev, "invalid hw address, using random\n");
|
|
|
|
|
eth_hw_addr_random(bp->dev);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2007-07-13 00:07:24 +07:00
|
|
|
struct macb *bp = bus->priv;
|
2006-11-09 20:51:17 +07:00
|
|
|
int value;
|
|
|
|
|
|
|
|
|
|
macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
|
|
|
|
|
| MACB_BF(RW, MACB_MAN_READ)
|
2007-07-13 00:07:24 +07:00
|
|
|
| MACB_BF(PHYA, mii_id)
|
|
|
|
|
| MACB_BF(REGA, regnum)
|
2006-11-09 20:51:17 +07:00
|
|
|
| MACB_BF(CODE, MACB_MAN_CODE)));
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* wait for end of transfer */
|
|
|
|
|
while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
|
|
|
|
|
cpu_relax();
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
|
|
|
|
|
|
|
|
|
|
return value;
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
|
|
|
|
|
u16 value)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2007-07-13 00:07:24 +07:00
|
|
|
struct macb *bp = bus->priv;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
|
|
|
|
|
| MACB_BF(RW, MACB_MAN_WRITE)
|
2007-07-13 00:07:24 +07:00
|
|
|
| MACB_BF(PHYA, mii_id)
|
|
|
|
|
| MACB_BF(REGA, regnum)
|
2006-11-09 20:51:17 +07:00
|
|
|
| MACB_BF(CODE, MACB_MAN_CODE)
|
2007-07-13 00:07:24 +07:00
|
|
|
| MACB_BF(DATA, value)));
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* wait for end of transfer */
|
|
|
|
|
while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
|
|
|
|
|
cpu_relax();
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-12-11 07:07:23 +07:00
|
|
|
/**
|
|
|
|
|
* macb_set_tx_clk() - Set a clock to a new frequency
|
|
|
|
|
* @clk Pointer to the clock to change
|
|
|
|
|
* @rate New frequency in Hz
|
|
|
|
|
* @dev Pointer to the struct net_device
|
|
|
|
|
*/
|
|
|
|
|
static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
long ferr, rate, rate_rounded;
|
|
|
|
|
|
2015-03-07 13:23:31 +07:00
|
|
|
if (!clk)
|
|
|
|
|
return;
|
|
|
|
|
|
2013-12-11 07:07:23 +07:00
|
|
|
switch (speed) {
|
|
|
|
|
case SPEED_10:
|
|
|
|
|
rate = 2500000;
|
|
|
|
|
break;
|
|
|
|
|
case SPEED_100:
|
|
|
|
|
rate = 25000000;
|
|
|
|
|
break;
|
|
|
|
|
case SPEED_1000:
|
|
|
|
|
rate = 125000000;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2013-12-11 11:57:57 +07:00
|
|
|
return;
|
2013-12-11 07:07:23 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
rate_rounded = clk_round_rate(clk, rate);
|
|
|
|
|
if (rate_rounded < 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* RGMII allows 50 ppm frequency error. Test and warn if this limit
|
|
|
|
|
* is not satisfied.
|
|
|
|
|
*/
|
|
|
|
|
ferr = abs(rate_rounded - rate);
|
|
|
|
|
ferr = DIV_ROUND_UP(ferr, rate / 100000);
|
|
|
|
|
if (ferr > 5)
|
|
|
|
|
netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
|
|
|
|
|
rate);
|
|
|
|
|
|
|
|
|
|
if (clk_set_rate(clk, rate_rounded))
|
|
|
|
|
netdev_err(dev, "adjusting tx_clk failed.\n");
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
static void macb_handle_link_change(struct net_device *dev)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2007-07-13 00:07:24 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
struct phy_device *phydev = bp->phy_dev;
|
|
|
|
|
unsigned long flags;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
int status_change = 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
spin_lock_irqsave(&bp->lock, flags);
|
|
|
|
|
|
|
|
|
|
if (phydev->link) {
|
|
|
|
|
if ((bp->speed != phydev->speed) ||
|
|
|
|
|
(bp->duplex != phydev->duplex)) {
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
reg = macb_readl(bp, NCFGR);
|
|
|
|
|
reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
|
2012-10-31 13:04:50 +07:00
|
|
|
if (macb_is_gem(bp))
|
|
|
|
|
reg &= ~GEM_BIT(GBE);
|
2007-07-13 00:07:24 +07:00
|
|
|
|
|
|
|
|
if (phydev->duplex)
|
|
|
|
|
reg |= MACB_BIT(FD);
|
2008-02-21 20:50:54 +07:00
|
|
|
if (phydev->speed == SPEED_100)
|
2007-07-13 00:07:24 +07:00
|
|
|
reg |= MACB_BIT(SPD);
|
2014-07-24 18:50:58 +07:00
|
|
|
if (phydev->speed == SPEED_1000 &&
|
|
|
|
|
bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
|
2012-10-31 13:04:50 +07:00
|
|
|
reg |= GEM_BIT(GBE);
|
2007-07-13 00:07:24 +07:00
|
|
|
|
2012-10-31 13:04:50 +07:00
|
|
|
macb_or_gem_writel(bp, NCFGR, reg);
|
2007-07-13 00:07:24 +07:00
|
|
|
|
|
|
|
|
bp->speed = phydev->speed;
|
|
|
|
|
bp->duplex = phydev->duplex;
|
|
|
|
|
status_change = 1;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
if (phydev->link != bp->link) {
|
2008-07-23 05:41:24 +07:00
|
|
|
if (!phydev->link) {
|
2007-07-13 00:07:24 +07:00
|
|
|
bp->speed = 0;
|
|
|
|
|
bp->duplex = -1;
|
|
|
|
|
}
|
|
|
|
|
bp->link = phydev->link;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
status_change = 1;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
|
|
|
|
|
2015-03-07 13:23:31 +07:00
|
|
|
macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
|
2013-12-11 07:07:23 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
if (status_change) {
|
2012-07-04 06:14:13 +07:00
|
|
|
if (phydev->link) {
|
|
|
|
|
netif_carrier_on(dev);
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_info(dev, "link up (%d/%s)\n",
|
|
|
|
|
phydev->speed,
|
|
|
|
|
phydev->duplex == DUPLEX_FULL ?
|
|
|
|
|
"Full" : "Half");
|
2012-07-04 06:14:13 +07:00
|
|
|
} else {
|
|
|
|
|
netif_carrier_off(dev);
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_info(dev, "link down\n");
|
2012-07-04 06:14:13 +07:00
|
|
|
}
|
2007-07-13 00:07:24 +07:00
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* based on au1000_eth. c*/
|
|
|
|
|
static int macb_mii_probe(struct net_device *dev)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2007-07-13 00:07:24 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
2012-11-11 20:56:27 +07:00
|
|
|
struct macb_platform_data *pdata;
|
2010-02-08 12:12:08 +07:00
|
|
|
struct phy_device *phydev;
|
2012-11-11 20:56:27 +07:00
|
|
|
int phy_irq;
|
2010-02-08 12:12:08 +07:00
|
|
|
int ret;
|
2007-07-13 00:07:24 +07:00
|
|
|
|
2010-02-08 12:12:08 +07:00
|
|
|
phydev = phy_find_first(bp->mii_bus);
|
2007-07-13 00:07:24 +07:00
|
|
|
if (!phydev) {
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_err(dev, "no PHY found\n");
|
2013-08-27 19:36:14 +07:00
|
|
|
return -ENXIO;
|
2007-07-13 00:07:24 +07:00
|
|
|
}
|
|
|
|
|
|
2012-11-11 20:56:27 +07:00
|
|
|
pdata = dev_get_platdata(&bp->pdev->dev);
|
|
|
|
|
if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
|
|
|
|
|
ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
|
|
|
|
|
if (!ret) {
|
|
|
|
|
phy_irq = gpio_to_irq(pdata->phy_irq_pin);
|
|
|
|
|
phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
|
|
|
|
|
}
|
|
|
|
|
}
|
2007-07-13 00:07:24 +07:00
|
|
|
|
|
|
|
|
/* attach the mac to the phy */
|
2013-01-14 07:52:52 +07:00
|
|
|
ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
|
2011-11-18 21:29:25 +07:00
|
|
|
bp->phy_interface);
|
2010-02-08 12:12:08 +07:00
|
|
|
if (ret) {
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_err(dev, "Could not attach to PHY\n");
|
2010-02-08 12:12:08 +07:00
|
|
|
return ret;
|
2007-07-13 00:07:24 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* mask with MAC supported features */
|
2014-07-24 18:50:58 +07:00
|
|
|
if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
|
2012-10-31 13:04:50 +07:00
|
|
|
phydev->supported &= PHY_GBIT_FEATURES;
|
|
|
|
|
else
|
|
|
|
|
phydev->supported &= PHY_BASIC_FEATURES;
|
2007-07-13 00:07:24 +07:00
|
|
|
|
|
|
|
|
phydev->advertising = phydev->supported;
|
|
|
|
|
|
|
|
|
|
bp->link = 0;
|
|
|
|
|
bp->speed = 0;
|
|
|
|
|
bp->duplex = -1;
|
|
|
|
|
bp->phy_dev = phydev;
|
|
|
|
|
|
|
|
|
|
return 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static int macb_mii_init(struct macb *bp)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2011-03-09 03:17:06 +07:00
|
|
|
struct macb_platform_data *pdata;
|
2013-08-22 22:57:28 +07:00
|
|
|
struct device_node *np;
|
2007-07-13 00:07:24 +07:00
|
|
|
int err = -ENXIO, i;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2009-07-23 13:31:31 +07:00
|
|
|
/* Enable management port */
|
2007-07-13 00:07:24 +07:00
|
|
|
macb_writel(bp, NCR, MACB_BIT(MPE));
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2008-10-09 06:29:57 +07:00
|
|
|
bp->mii_bus = mdiobus_alloc();
|
|
|
|
|
if (bp->mii_bus == NULL) {
|
|
|
|
|
err = -ENOMEM;
|
|
|
|
|
goto err_out;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bp->mii_bus->name = "MACB_mii_bus";
|
|
|
|
|
bp->mii_bus->read = &macb_mdio_read;
|
|
|
|
|
bp->mii_bus->write = &macb_mdio_write;
|
2012-01-10 06:59:11 +07:00
|
|
|
snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
|
|
|
|
|
bp->pdev->name, bp->pdev->id);
|
2008-10-09 06:29:57 +07:00
|
|
|
bp->mii_bus->priv = bp;
|
|
|
|
|
bp->mii_bus->parent = &bp->dev->dev;
|
2013-08-30 12:12:21 +07:00
|
|
|
pdata = dev_get_platdata(&bp->pdev->dev);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2008-10-09 06:29:57 +07:00
|
|
|
bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
|
|
|
|
|
if (!bp->mii_bus->irq) {
|
2007-07-13 00:07:24 +07:00
|
|
|
err = -ENOMEM;
|
2008-10-09 06:29:57 +07:00
|
|
|
goto err_out_free_mdiobus;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2011-02-28 11:05:25 +07:00
|
|
|
dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-08-22 22:57:28 +07:00
|
|
|
np = bp->pdev->dev.of_node;
|
|
|
|
|
if (np) {
|
|
|
|
|
/* try dt phy registration */
|
|
|
|
|
err = of_mdiobus_register(bp->mii_bus, np);
|
|
|
|
|
|
|
|
|
|
/* fallback to standard phy registration if no phy were
|
|
|
|
|
found during dt phy registration */
|
|
|
|
|
if (!err && !phy_find_first(bp->mii_bus)) {
|
|
|
|
|
for (i = 0; i < PHY_MAX_ADDR; i++) {
|
|
|
|
|
struct phy_device *phydev;
|
|
|
|
|
|
|
|
|
|
phydev = mdiobus_scan(bp->mii_bus, i);
|
|
|
|
|
if (IS_ERR(phydev)) {
|
|
|
|
|
err = PTR_ERR(phydev);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_out_unregister_bus;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0; i < PHY_MAX_ADDR; i++)
|
|
|
|
|
bp->mii_bus->irq[i] = PHY_POLL;
|
|
|
|
|
|
|
|
|
|
if (pdata)
|
|
|
|
|
bp->mii_bus->phy_mask = pdata->phy_mask;
|
|
|
|
|
|
|
|
|
|
err = mdiobus_register(bp->mii_bus);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (err)
|
2007-07-13 00:07:24 +07:00
|
|
|
goto err_out_free_mdio_irq;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-08-27 19:36:14 +07:00
|
|
|
err = macb_mii_probe(bp->dev);
|
|
|
|
|
if (err)
|
2007-07-13 00:07:24 +07:00
|
|
|
goto err_out_unregister_bus;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
return 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
err_out_unregister_bus:
|
2008-10-09 06:29:57 +07:00
|
|
|
mdiobus_unregister(bp->mii_bus);
|
2007-07-13 00:07:24 +07:00
|
|
|
err_out_free_mdio_irq:
|
2008-10-09 06:29:57 +07:00
|
|
|
kfree(bp->mii_bus->irq);
|
|
|
|
|
err_out_free_mdiobus:
|
|
|
|
|
mdiobus_free(bp->mii_bus);
|
2007-07-13 00:07:24 +07:00
|
|
|
err_out:
|
|
|
|
|
return err;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void macb_update_stats(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
u32 __iomem *reg = bp->regs + MACB_PFR;
|
2011-03-09 23:26:35 +07:00
|
|
|
u32 *p = &bp->hw_stats.macb.rx_pause_frames;
|
|
|
|
|
u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
|
|
|
|
|
|
|
|
|
|
for(; p < end; p++, reg++)
|
2015-02-18 18:29:35 +07:00
|
|
|
*p += readl_relaxed(reg);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
static int macb_halt_tx(struct macb *bp)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2012-10-31 13:04:57 +07:00
|
|
|
unsigned long halt_time, timeout;
|
|
|
|
|
u32 status;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
|
|
|
|
|
do {
|
|
|
|
|
halt_time = jiffies;
|
|
|
|
|
status = macb_readl(bp, TSR);
|
|
|
|
|
if (!(status & MACB_BIT(TGO)))
|
|
|
|
|
return 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
usleep_range(10, 250);
|
|
|
|
|
} while (time_before(halt_time, timeout));
|
2007-12-20 00:23:44 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
2009-01-19 12:57:35 +07:00
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
|
|
|
|
|
{
|
|
|
|
|
if (tx_skb->mapping) {
|
|
|
|
|
if (tx_skb->mapped_as_page)
|
|
|
|
|
dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
|
|
|
|
|
tx_skb->size, DMA_TO_DEVICE);
|
|
|
|
|
else
|
|
|
|
|
dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
|
|
|
|
|
tx_skb->size, DMA_TO_DEVICE);
|
|
|
|
|
tx_skb->mapping = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (tx_skb->skb) {
|
|
|
|
|
dev_kfree_skb_any(tx_skb->skb);
|
|
|
|
|
tx_skb->skb = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
static void macb_tx_error_task(struct work_struct *work)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue = container_of(work, struct macb_queue,
|
|
|
|
|
tx_error_task);
|
|
|
|
|
struct macb *bp = queue->bp;
|
2012-10-31 13:04:57 +07:00
|
|
|
struct macb_tx_skb *tx_skb;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_dma_desc *desc;
|
2012-10-31 13:04:57 +07:00
|
|
|
struct sk_buff *skb;
|
|
|
|
|
unsigned int tail;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
|
|
|
|
|
(unsigned int)(queue - bp->queues),
|
|
|
|
|
queue->tx_tail, queue->tx_head);
|
2007-12-20 00:23:44 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
/* Prevent the queue IRQ handlers from running: each of them may call
|
|
|
|
|
* macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
|
|
|
|
|
* As explained below, we have to halt the transmission before updating
|
|
|
|
|
* TBQP registers so we call netif_tx_stop_all_queues() to notify the
|
|
|
|
|
* network engine about the macb/gem being halted.
|
|
|
|
|
*/
|
|
|
|
|
spin_lock_irqsave(&bp->lock, flags);
|
2007-12-20 00:23:44 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
/* Make sure nobody is trying to queue up new packets */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
netif_tx_stop_all_queues(bp->dev);
|
2011-08-04 05:11:47 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
/*
|
|
|
|
|
* Stop transmission now
|
|
|
|
|
* (in case we have just queued new packets)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
* macb/gem must be halted to write TBQP register
|
2012-10-31 13:04:57 +07:00
|
|
|
*/
|
|
|
|
|
if (macb_halt_tx(bp))
|
|
|
|
|
/* Just complain for now, reinitializing TX path can be good */
|
|
|
|
|
netdev_err(bp->dev, "BUG: halt tx timed out\n");
|
2007-12-20 00:23:44 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
/*
|
|
|
|
|
* Treat frames in TX queue including the ones that caused the error.
|
|
|
|
|
* Free transmit buffers in upper layer.
|
|
|
|
|
*/
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
|
|
|
|
|
u32 ctrl;
|
2012-10-31 13:04:55 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
desc = macb_tx_desc(queue, tail);
|
2012-10-31 13:04:57 +07:00
|
|
|
ctrl = desc->ctrl;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = macb_tx_skb(queue, tail);
|
2012-10-31 13:04:57 +07:00
|
|
|
skb = tx_skb->skb;
|
2007-12-20 00:23:44 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
if (ctrl & MACB_BIT(TX_USED)) {
|
2014-07-24 18:50:59 +07:00
|
|
|
/* skb is set for the last buffer of the frame */
|
|
|
|
|
while (!skb) {
|
|
|
|
|
macb_tx_unmap(bp, tx_skb);
|
|
|
|
|
tail++;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = macb_tx_skb(queue, tail);
|
2014-07-24 18:50:59 +07:00
|
|
|
skb = tx_skb->skb;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* ctrl still refers to the first buffer descriptor
|
|
|
|
|
* since it's the only one written back by the hardware
|
|
|
|
|
*/
|
|
|
|
|
if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
|
|
|
|
|
netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
|
|
|
|
|
macb_tx_ring_wrap(tail), skb->data);
|
|
|
|
|
bp->stats.tx_packets++;
|
|
|
|
|
bp->stats.tx_bytes += skb->len;
|
|
|
|
|
}
|
2012-10-31 13:04:57 +07:00
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* "Buffers exhausted mid-frame" errors may only happen
|
|
|
|
|
* if the driver is buggy, so complain loudly about those.
|
|
|
|
|
* Statistics are updated by hardware.
|
|
|
|
|
*/
|
|
|
|
|
if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
|
|
|
|
|
netdev_err(bp->dev,
|
|
|
|
|
"BUG: TX buffers exhausted mid-frame\n");
|
2009-01-19 12:57:35 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
desc->ctrl = ctrl | MACB_BIT(TX_USED);
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
macb_tx_unmap(bp, tx_skb);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
/* Set end of TX queue */
|
|
|
|
|
desc = macb_tx_desc(queue, 0);
|
|
|
|
|
desc->addr = 0;
|
|
|
|
|
desc->ctrl = MACB_BIT(TX_USED);
|
|
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
/* Make descriptor updates visible to hardware */
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
|
|
/* Reinitialize the TX desc queue */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, TBQP, queue->tx_ring_dma);
|
2012-10-31 13:04:57 +07:00
|
|
|
/* Make TX ring reflect state of hardware */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue->tx_head = 0;
|
|
|
|
|
queue->tx_tail = 0;
|
2012-10-31 13:04:57 +07:00
|
|
|
|
|
|
|
|
/* Housework before enabling TX IRQ */
|
|
|
|
|
macb_writel(bp, TSR, macb_readl(bp, TSR));
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, IER, MACB_TX_INT_FLAGS);
|
|
|
|
|
|
|
|
|
|
/* Now we are ready to start transmission again */
|
|
|
|
|
netif_tx_start_all_queues(bp->dev);
|
|
|
|
|
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
2012-10-31 13:04:57 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
static void macb_tx_interrupt(struct macb_queue *queue)
|
2012-10-31 13:04:57 +07:00
|
|
|
{
|
|
|
|
|
unsigned int tail;
|
|
|
|
|
unsigned int head;
|
|
|
|
|
u32 status;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb *bp = queue->bp;
|
|
|
|
|
u16 queue_index = queue - bp->queues;
|
2012-10-31 13:04:57 +07:00
|
|
|
|
|
|
|
|
status = macb_readl(bp, TSR);
|
|
|
|
|
macb_writel(bp, TSR, status);
|
|
|
|
|
|
2013-05-14 10:00:16 +07:00
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, ISR, MACB_BIT(TCOMP));
|
2013-03-28 06:07:05 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
|
|
|
|
|
(unsigned long)status);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
head = queue->tx_head;
|
|
|
|
|
for (tail = queue->tx_tail; tail != head; tail++) {
|
2012-10-31 13:04:55 +07:00
|
|
|
struct macb_tx_skb *tx_skb;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
struct macb_dma_desc *desc;
|
|
|
|
|
u32 ctrl;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
desc = macb_tx_desc(queue, tail);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:51 +07:00
|
|
|
/* Make hw descriptor updates visible to CPU */
|
2006-11-09 20:51:17 +07:00
|
|
|
rmb();
|
2012-10-31 13:04:51 +07:00
|
|
|
|
2012-10-31 13:04:55 +07:00
|
|
|
ctrl = desc->ctrl;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* TX_USED bit is only set by hardware on the very first buffer
|
|
|
|
|
* descriptor of the transmitted frame.
|
|
|
|
|
*/
|
2012-10-31 13:04:55 +07:00
|
|
|
if (!(ctrl & MACB_BIT(TX_USED)))
|
2006-11-09 20:51:17 +07:00
|
|
|
break;
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* Process all buffers of the current transmitted frame */
|
|
|
|
|
for (;; tail++) {
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = macb_tx_skb(queue, tail);
|
2014-07-24 18:50:59 +07:00
|
|
|
skb = tx_skb->skb;
|
|
|
|
|
|
|
|
|
|
/* First, update TX stats if needed */
|
|
|
|
|
if (skb) {
|
|
|
|
|
netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
|
|
|
|
|
macb_tx_ring_wrap(tail), skb->data);
|
|
|
|
|
bp->stats.tx_packets++;
|
|
|
|
|
bp->stats.tx_bytes += skb->len;
|
|
|
|
|
}
|
2012-10-31 13:04:55 +07:00
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* Now we can safely release resources */
|
|
|
|
|
macb_tx_unmap(bp, tx_skb);
|
|
|
|
|
|
|
|
|
|
/* skb is set only for the last buffer of the frame.
|
|
|
|
|
* WARNING: at this point skb has been freed by
|
|
|
|
|
* macb_tx_unmap().
|
|
|
|
|
*/
|
|
|
|
|
if (skb)
|
|
|
|
|
break;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue->tx_tail = tail;
|
|
|
|
|
if (__netif_subqueue_stopped(bp->dev, queue_index) &&
|
|
|
|
|
CIRC_CNT(queue->tx_head, queue->tx_tail,
|
|
|
|
|
TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
|
|
|
|
|
netif_wake_subqueue(bp->dev, queue_index);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
static void gem_rx_refill(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
unsigned int entry;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
dma_addr_t paddr;
|
|
|
|
|
|
|
|
|
|
while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
|
|
|
|
|
entry = macb_rx_ring_wrap(bp->rx_prepared_head);
|
|
|
|
|
|
|
|
|
|
/* Make hw descriptor updates visible to CPU */
|
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
|
|
bp->rx_prepared_head++;
|
|
|
|
|
|
|
|
|
|
if (bp->rx_skbuff[entry] == NULL) {
|
|
|
|
|
/* allocate sk_buff for this free entry in ring */
|
|
|
|
|
skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
|
|
|
|
|
if (unlikely(skb == NULL)) {
|
|
|
|
|
netdev_err(bp->dev,
|
|
|
|
|
"Unable to allocate sk_buff\n");
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* now fill corresponding descriptor entry */
|
|
|
|
|
paddr = dma_map_single(&bp->pdev->dev, skb->data,
|
|
|
|
|
bp->rx_buffer_size, DMA_FROM_DEVICE);
|
2014-03-04 23:46:39 +07:00
|
|
|
if (dma_mapping_error(&bp->pdev->dev, paddr)) {
|
|
|
|
|
dev_kfree_skb(skb);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bp->rx_skbuff[entry] = skb;
|
2013-06-05 04:57:12 +07:00
|
|
|
|
|
|
|
|
if (entry == RX_RING_SIZE - 1)
|
|
|
|
|
paddr |= MACB_BIT(RX_WRAP);
|
|
|
|
|
bp->rx_ring[entry].addr = paddr;
|
|
|
|
|
bp->rx_ring[entry].ctrl = 0;
|
|
|
|
|
|
|
|
|
|
/* properly align Ethernet header */
|
|
|
|
|
skb_reserve(skb, NET_IP_ALIGN);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Make descriptor updates visible to hardware */
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
|
|
netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
|
|
|
|
|
bp->rx_prepared_head, bp->rx_tail);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Mark DMA descriptors from begin up to and not including end as unused */
|
|
|
|
|
static void discard_partial_frame(struct macb *bp, unsigned int begin,
|
|
|
|
|
unsigned int end)
|
|
|
|
|
{
|
|
|
|
|
unsigned int frag;
|
|
|
|
|
|
|
|
|
|
for (frag = begin; frag != end; frag++) {
|
|
|
|
|
struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
|
|
|
|
|
desc->addr &= ~MACB_BIT(RX_USED);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Make descriptor updates visible to hardware */
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* When this happens, the hardware stats registers for
|
|
|
|
|
* whatever caused this is updated, so we don't have to record
|
|
|
|
|
* anything.
|
|
|
|
|
*/
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int gem_rx(struct macb *bp, int budget)
|
|
|
|
|
{
|
|
|
|
|
unsigned int len;
|
|
|
|
|
unsigned int entry;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
struct macb_dma_desc *desc;
|
|
|
|
|
int count = 0;
|
|
|
|
|
|
|
|
|
|
while (count < budget) {
|
|
|
|
|
u32 addr, ctrl;
|
|
|
|
|
|
|
|
|
|
entry = macb_rx_ring_wrap(bp->rx_tail);
|
|
|
|
|
desc = &bp->rx_ring[entry];
|
|
|
|
|
|
|
|
|
|
/* Make hw descriptor updates visible to CPU */
|
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
|
|
addr = desc->addr;
|
|
|
|
|
ctrl = desc->ctrl;
|
|
|
|
|
|
|
|
|
|
if (!(addr & MACB_BIT(RX_USED)))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
bp->rx_tail++;
|
|
|
|
|
count++;
|
|
|
|
|
|
|
|
|
|
if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
|
|
|
|
|
netdev_err(bp->dev,
|
|
|
|
|
"not whole frame pointed by descriptor\n");
|
|
|
|
|
bp->stats.rx_dropped++;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
skb = bp->rx_skbuff[entry];
|
|
|
|
|
if (unlikely(!skb)) {
|
|
|
|
|
netdev_err(bp->dev,
|
|
|
|
|
"inconsistent Rx descriptor chain\n");
|
|
|
|
|
bp->stats.rx_dropped++;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
/* now everything is ready for receiving packet */
|
|
|
|
|
bp->rx_skbuff[entry] = NULL;
|
|
|
|
|
len = MACB_BFEXT(RX_FRMLEN, ctrl);
|
|
|
|
|
|
|
|
|
|
netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
|
|
|
|
|
|
|
|
|
|
skb_put(skb, len);
|
|
|
|
|
addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
|
|
|
|
|
dma_unmap_single(&bp->pdev->dev, addr,
|
2014-03-04 23:46:40 +07:00
|
|
|
bp->rx_buffer_size, DMA_FROM_DEVICE);
|
2013-06-05 04:57:12 +07:00
|
|
|
|
|
|
|
|
skb->protocol = eth_type_trans(skb, bp->dev);
|
|
|
|
|
skb_checksum_none_assert(skb);
|
2014-07-24 18:51:01 +07:00
|
|
|
if (bp->dev->features & NETIF_F_RXCSUM &&
|
|
|
|
|
!(bp->dev->flags & IFF_PROMISC) &&
|
|
|
|
|
GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
|
|
|
|
|
skb->ip_summed = CHECKSUM_UNNECESSARY;
|
2013-06-05 04:57:12 +07:00
|
|
|
|
|
|
|
|
bp->stats.rx_packets++;
|
|
|
|
|
bp->stats.rx_bytes += skb->len;
|
|
|
|
|
|
|
|
|
|
#if defined(DEBUG) && defined(VERBOSE_DEBUG)
|
|
|
|
|
netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
|
|
|
|
|
skb->len, skb->csum);
|
|
|
|
|
print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
|
2014-12-11 17:15:54 +07:00
|
|
|
skb_mac_header(skb), 16, true);
|
2013-06-05 04:57:12 +07:00
|
|
|
print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
|
|
|
|
|
skb->data, 32, true);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
netif_receive_skb(skb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
gem_rx_refill(bp);
|
|
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
|
|
|
|
|
unsigned int last_frag)
|
|
|
|
|
{
|
|
|
|
|
unsigned int len;
|
|
|
|
|
unsigned int frag;
|
2012-10-31 13:04:58 +07:00
|
|
|
unsigned int offset;
|
2006-11-09 20:51:17 +07:00
|
|
|
struct sk_buff *skb;
|
2012-10-31 13:04:55 +07:00
|
|
|
struct macb_dma_desc *desc;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:55 +07:00
|
|
|
desc = macb_rx_desc(bp, last_frag);
|
|
|
|
|
len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:52 +07:00
|
|
|
netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
|
2012-10-31 13:04:55 +07:00
|
|
|
macb_rx_ring_wrap(first_frag),
|
|
|
|
|
macb_rx_ring_wrap(last_frag), len);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:58 +07:00
|
|
|
/*
|
|
|
|
|
* The ethernet header starts NET_IP_ALIGN bytes into the
|
|
|
|
|
* first buffer. Since the header is 14 bytes, this makes the
|
|
|
|
|
* payload word-aligned.
|
|
|
|
|
*
|
|
|
|
|
* Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
|
|
|
|
|
* the two padding bytes into the skb so that we avoid hitting
|
|
|
|
|
* the slowpath in memcpy(), and pull them off afterwards.
|
|
|
|
|
*/
|
|
|
|
|
skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
|
2006-11-09 20:51:17 +07:00
|
|
|
if (!skb) {
|
|
|
|
|
bp->stats.rx_dropped++;
|
2012-10-31 13:04:55 +07:00
|
|
|
for (frag = first_frag; ; frag++) {
|
|
|
|
|
desc = macb_rx_desc(bp, frag);
|
|
|
|
|
desc->addr &= ~MACB_BIT(RX_USED);
|
2006-11-09 20:51:17 +07:00
|
|
|
if (frag == last_frag)
|
|
|
|
|
break;
|
|
|
|
|
}
|
2012-10-31 13:04:51 +07:00
|
|
|
|
|
|
|
|
/* Make descriptor updates visible to hardware */
|
2006-11-09 20:51:17 +07:00
|
|
|
wmb();
|
2012-10-31 13:04:51 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:58 +07:00
|
|
|
offset = 0;
|
|
|
|
|
len += NET_IP_ALIGN;
|
2010-09-03 03:07:41 +07:00
|
|
|
skb_checksum_none_assert(skb);
|
2006-11-09 20:51:17 +07:00
|
|
|
skb_put(skb, len);
|
|
|
|
|
|
2012-10-31 13:04:55 +07:00
|
|
|
for (frag = first_frag; ; frag++) {
|
2013-06-05 04:57:11 +07:00
|
|
|
unsigned int frag_len = bp->rx_buffer_size;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
if (offset + frag_len > len) {
|
|
|
|
|
BUG_ON(frag != last_frag);
|
|
|
|
|
frag_len = len - offset;
|
|
|
|
|
}
|
2007-03-31 21:55:19 +07:00
|
|
|
skb_copy_to_linear_data_offset(skb, offset,
|
2012-10-31 13:04:55 +07:00
|
|
|
macb_rx_buffer(bp, frag), frag_len);
|
2013-06-05 04:57:11 +07:00
|
|
|
offset += bp->rx_buffer_size;
|
2012-10-31 13:04:55 +07:00
|
|
|
desc = macb_rx_desc(bp, frag);
|
|
|
|
|
desc->addr &= ~MACB_BIT(RX_USED);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
if (frag == last_frag)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:51 +07:00
|
|
|
/* Make descriptor updates visible to hardware */
|
|
|
|
|
wmb();
|
|
|
|
|
|
2012-10-31 13:04:58 +07:00
|
|
|
__skb_pull(skb, NET_IP_ALIGN);
|
2006-11-09 20:51:17 +07:00
|
|
|
skb->protocol = eth_type_trans(skb, bp->dev);
|
|
|
|
|
|
|
|
|
|
bp->stats.rx_packets++;
|
2012-10-31 13:04:58 +07:00
|
|
|
bp->stats.rx_bytes += skb->len;
|
2012-10-31 13:04:52 +07:00
|
|
|
netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
|
2011-03-09 03:27:08 +07:00
|
|
|
skb->len, skb->csum);
|
2006-11-09 20:51:17 +07:00
|
|
|
netif_receive_skb(skb);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_rx(struct macb *bp, int budget)
|
|
|
|
|
{
|
|
|
|
|
int received = 0;
|
2012-10-31 13:04:55 +07:00
|
|
|
unsigned int tail;
|
2006-11-09 20:51:17 +07:00
|
|
|
int first_frag = -1;
|
|
|
|
|
|
2012-10-31 13:04:55 +07:00
|
|
|
for (tail = bp->rx_tail; budget > 0; tail++) {
|
|
|
|
|
struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 addr, ctrl;
|
|
|
|
|
|
2012-10-31 13:04:51 +07:00
|
|
|
/* Make hw descriptor updates visible to CPU */
|
2006-11-09 20:51:17 +07:00
|
|
|
rmb();
|
2012-10-31 13:04:51 +07:00
|
|
|
|
2012-10-31 13:04:55 +07:00
|
|
|
addr = desc->addr;
|
|
|
|
|
ctrl = desc->ctrl;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
if (!(addr & MACB_BIT(RX_USED)))
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
if (ctrl & MACB_BIT(RX_SOF)) {
|
|
|
|
|
if (first_frag != -1)
|
|
|
|
|
discard_partial_frame(bp, first_frag, tail);
|
|
|
|
|
first_frag = tail;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (ctrl & MACB_BIT(RX_EOF)) {
|
|
|
|
|
int dropped;
|
|
|
|
|
BUG_ON(first_frag == -1);
|
|
|
|
|
|
|
|
|
|
dropped = macb_rx_frame(bp, first_frag, tail);
|
|
|
|
|
first_frag = -1;
|
|
|
|
|
if (!dropped) {
|
|
|
|
|
received++;
|
|
|
|
|
budget--;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (first_frag != -1)
|
|
|
|
|
bp->rx_tail = first_frag;
|
|
|
|
|
else
|
|
|
|
|
bp->rx_tail = tail;
|
|
|
|
|
|
|
|
|
|
return received;
|
|
|
|
|
}
|
|
|
|
|
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
static int macb_poll(struct napi_struct *napi, int budget)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
struct macb *bp = container_of(napi, struct macb, napi);
|
|
|
|
|
int work_done;
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 status;
|
|
|
|
|
|
|
|
|
|
status = macb_readl(bp, RSR);
|
|
|
|
|
macb_writel(bp, RSR, status);
|
|
|
|
|
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
work_done = 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:52 +07:00
|
|
|
netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
|
2011-03-09 03:27:08 +07:00
|
|
|
(unsigned long)status, budget);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
work_done = bp->macbgem_ops.mog_rx(bp, budget);
|
2010-10-25 08:44:22 +07:00
|
|
|
if (work_done < budget) {
|
2009-01-20 07:43:59 +07:00
|
|
|
napi_complete(napi);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-02-12 17:08:48 +07:00
|
|
|
/* Packets received while interrupts were disabled */
|
|
|
|
|
status = macb_readl(bp, RSR);
|
2014-05-05 05:43:01 +07:00
|
|
|
if (status) {
|
2014-05-05 05:43:00 +07:00
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
|
|
|
|
macb_writel(bp, ISR, MACB_BIT(RCOMP));
|
2013-02-12 17:08:48 +07:00
|
|
|
napi_reschedule(napi);
|
2014-05-05 05:43:00 +07:00
|
|
|
} else {
|
|
|
|
|
macb_writel(bp, IER, MACB_RX_INT_FLAGS);
|
|
|
|
|
}
|
2010-10-25 08:44:22 +07:00
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
/* TODO: Handle errors */
|
|
|
|
|
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
return work_done;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t macb_interrupt(int irq, void *dev_id)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue = dev_id;
|
|
|
|
|
struct macb *bp = queue->bp;
|
|
|
|
|
struct net_device *dev = bp->dev;
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 status;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
status = queue_readl(queue, ISR);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
if (unlikely(!status))
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
|
|
spin_lock(&bp->lock);
|
|
|
|
|
|
|
|
|
|
while (status) {
|
|
|
|
|
/* close possible race with dev_close */
|
|
|
|
|
if (unlikely(!netif_running(dev))) {
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, IDR, -1);
|
2006-11-09 20:51:17 +07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
|
|
|
|
|
(unsigned int)(queue - bp->queues),
|
|
|
|
|
(unsigned long)status);
|
2012-10-31 13:04:52 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
if (status & MACB_RX_INT_FLAGS) {
|
2010-10-25 08:44:22 +07:00
|
|
|
/*
|
|
|
|
|
* There's no point taking any more interrupts
|
|
|
|
|
* until we have processed the buffers. The
|
|
|
|
|
* scheduling call may fail if the poll routine
|
|
|
|
|
* is already scheduled, so disable interrupts
|
|
|
|
|
* now.
|
|
|
|
|
*/
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
|
2013-05-14 10:00:16 +07:00
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, ISR, MACB_BIT(RCOMP));
|
2010-10-25 08:44:22 +07:00
|
|
|
|
2009-01-20 07:43:59 +07:00
|
|
|
if (napi_schedule_prep(&bp->napi)) {
|
2012-10-31 13:04:52 +07:00
|
|
|
netdev_vdbg(bp->dev, "scheduling RX softirq\n");
|
2009-01-20 07:43:59 +07:00
|
|
|
__napi_schedule(&bp->napi);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
|
|
|
|
|
schedule_work(&queue->tx_error_task);
|
2014-05-05 05:42:59 +07:00
|
|
|
|
|
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
|
2014-05-05 05:42:59 +07:00
|
|
|
|
2012-10-31 13:04:57 +07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (status & MACB_BIT(TCOMP))
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
macb_tx_interrupt(queue);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Link change detection isn't possible with RMII, so we'll
|
|
|
|
|
* add that if/when we get our hands on a full-blown MII PHY.
|
|
|
|
|
*/
|
|
|
|
|
|
2011-04-13 12:03:24 +07:00
|
|
|
if (status & MACB_BIT(ISR_ROVR)) {
|
|
|
|
|
/* We missed at least one packet */
|
2011-11-08 17:12:32 +07:00
|
|
|
if (macb_is_gem(bp))
|
|
|
|
|
bp->hw_stats.gem.rx_overruns++;
|
|
|
|
|
else
|
|
|
|
|
bp->hw_stats.macb.rx_overruns++;
|
2014-05-05 05:42:59 +07:00
|
|
|
|
|
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
|
2011-04-13 12:03:24 +07:00
|
|
|
}
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
if (status & MACB_BIT(HRESP)) {
|
|
|
|
|
/*
|
2011-03-09 03:27:08 +07:00
|
|
|
* TODO: Reset the hardware, and maybe move the
|
|
|
|
|
* netdev_err to a lower-priority context as well
|
|
|
|
|
* (work queue?)
|
2006-11-09 20:51:17 +07:00
|
|
|
*/
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_err(dev, "DMA bus error: HRESP not OK\n");
|
2014-05-05 05:42:59 +07:00
|
|
|
|
|
|
|
|
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue_writel(queue, ISR, MACB_BIT(HRESP));
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
status = queue_readl(queue, ISR);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spin_unlock(&bp->lock);
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
2009-05-05 01:08:41 +07:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
/*
|
|
|
|
|
* Polling receive - used by netconsole and other diagnostic tools
|
|
|
|
|
* to allow network i/o with interrupts disabled.
|
|
|
|
|
*/
|
|
|
|
|
static void macb_poll_controller(struct net_device *dev)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
struct macb_queue *queue;
|
2009-05-05 01:08:41 +07:00
|
|
|
unsigned long flags;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
unsigned int q;
|
2009-05-05 01:08:41 +07:00
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
|
|
|
|
|
macb_interrupt(dev->irq, queue);
|
2009-05-05 01:08:41 +07:00
|
|
|
local_irq_restore(flags);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
|
|
|
|
|
unsigned int len)
|
|
|
|
|
{
|
|
|
|
|
return (len + bp->max_tx_length - 1) / bp->max_tx_length;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static unsigned int macb_tx_map(struct macb *bp,
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue,
|
2014-07-24 18:50:59 +07:00
|
|
|
struct sk_buff *skb)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
|
|
|
|
dma_addr_t mapping;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
unsigned int len, entry, i, tx_head = queue->tx_head;
|
2014-07-24 18:50:59 +07:00
|
|
|
struct macb_tx_skb *tx_skb = NULL;
|
2012-10-31 13:04:55 +07:00
|
|
|
struct macb_dma_desc *desc;
|
2014-07-24 18:50:59 +07:00
|
|
|
unsigned int offset, size, count = 0;
|
|
|
|
|
unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
|
|
|
|
|
unsigned int eof = 1;
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 ctrl;
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
/* First, map non-paged data */
|
|
|
|
|
len = skb_headlen(skb);
|
|
|
|
|
offset = 0;
|
|
|
|
|
while (len) {
|
|
|
|
|
size = min(len, bp->max_tx_length);
|
|
|
|
|
entry = macb_tx_ring_wrap(tx_head);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = &queue->tx_skb[entry];
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
mapping = dma_map_single(&bp->pdev->dev,
|
|
|
|
|
skb->data + offset,
|
|
|
|
|
size, DMA_TO_DEVICE);
|
|
|
|
|
if (dma_mapping_error(&bp->pdev->dev, mapping))
|
|
|
|
|
goto dma_error;
|
|
|
|
|
|
|
|
|
|
/* Save info to properly release resources */
|
|
|
|
|
tx_skb->skb = NULL;
|
|
|
|
|
tx_skb->mapping = mapping;
|
|
|
|
|
tx_skb->size = size;
|
|
|
|
|
tx_skb->mapped_as_page = false;
|
|
|
|
|
|
|
|
|
|
len -= size;
|
|
|
|
|
offset += size;
|
|
|
|
|
count++;
|
|
|
|
|
tx_head++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Then, map paged data from fragments */
|
|
|
|
|
for (f = 0; f < nr_frags; f++) {
|
|
|
|
|
const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
|
|
|
|
|
|
|
|
|
|
len = skb_frag_size(frag);
|
|
|
|
|
offset = 0;
|
|
|
|
|
while (len) {
|
|
|
|
|
size = min(len, bp->max_tx_length);
|
|
|
|
|
entry = macb_tx_ring_wrap(tx_head);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = &queue->tx_skb[entry];
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
|
|
|
|
|
offset, size, DMA_TO_DEVICE);
|
|
|
|
|
if (dma_mapping_error(&bp->pdev->dev, mapping))
|
|
|
|
|
goto dma_error;
|
|
|
|
|
|
|
|
|
|
/* Save info to properly release resources */
|
|
|
|
|
tx_skb->skb = NULL;
|
|
|
|
|
tx_skb->mapping = mapping;
|
|
|
|
|
tx_skb->size = size;
|
|
|
|
|
tx_skb->mapped_as_page = true;
|
|
|
|
|
|
|
|
|
|
len -= size;
|
|
|
|
|
offset += size;
|
|
|
|
|
count++;
|
|
|
|
|
tx_head++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Should never happen */
|
|
|
|
|
if (unlikely(tx_skb == NULL)) {
|
|
|
|
|
netdev_err(bp->dev, "BUG! empty skb!\n");
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* This is the last buffer of the frame: save socket buffer */
|
|
|
|
|
tx_skb->skb = skb;
|
|
|
|
|
|
|
|
|
|
/* Update TX ring: update buffer descriptors in reverse order
|
|
|
|
|
* to avoid race condition
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* Set 'TX_USED' bit in buffer descriptor at tx_head position
|
|
|
|
|
* to set the end of TX queue
|
|
|
|
|
*/
|
|
|
|
|
i = tx_head;
|
|
|
|
|
entry = macb_tx_ring_wrap(i);
|
|
|
|
|
ctrl = MACB_BIT(TX_USED);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
desc = &queue->tx_ring[entry];
|
2014-07-24 18:50:59 +07:00
|
|
|
desc->ctrl = ctrl;
|
|
|
|
|
|
|
|
|
|
do {
|
|
|
|
|
i--;
|
|
|
|
|
entry = macb_tx_ring_wrap(i);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tx_skb = &queue->tx_skb[entry];
|
|
|
|
|
desc = &queue->tx_ring[entry];
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
ctrl = (u32)tx_skb->size;
|
|
|
|
|
if (eof) {
|
|
|
|
|
ctrl |= MACB_BIT(TX_LAST);
|
|
|
|
|
eof = 0;
|
|
|
|
|
}
|
|
|
|
|
if (unlikely(entry == (TX_RING_SIZE - 1)))
|
|
|
|
|
ctrl |= MACB_BIT(TX_WRAP);
|
|
|
|
|
|
|
|
|
|
/* Set TX buffer descriptor */
|
|
|
|
|
desc->addr = tx_skb->mapping;
|
|
|
|
|
/* desc->addr must be visible to hardware before clearing
|
|
|
|
|
* 'TX_USED' bit in desc->ctrl.
|
|
|
|
|
*/
|
|
|
|
|
wmb();
|
|
|
|
|
desc->ctrl = ctrl;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
} while (i != queue->tx_head);
|
2014-07-24 18:50:59 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue->tx_head = tx_head;
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
return count;
|
|
|
|
|
|
|
|
|
|
dma_error:
|
|
|
|
|
netdev_err(bp->dev, "TX DMA map failed\n");
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (i = queue->tx_head; i != tx_head; i++) {
|
|
|
|
|
tx_skb = macb_tx_skb(queue, i);
|
2014-07-24 18:50:59 +07:00
|
|
|
|
|
|
|
|
macb_tx_unmap(bp, tx_skb);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
u16 queue_index = skb_get_queue_mapping(skb);
|
2014-07-24 18:50:59 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue = &bp->queues[queue_index];
|
2009-08-24 09:49:07 +07:00
|
|
|
unsigned long flags;
|
2014-07-24 18:50:59 +07:00
|
|
|
unsigned int count, nr_frags, frag_size, f;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-10-31 13:04:52 +07:00
|
|
|
#if defined(DEBUG) && defined(VERBOSE_DEBUG)
|
|
|
|
|
netdev_vdbg(bp->dev,
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
"start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
|
|
|
|
|
queue_index, skb->len, skb->head, skb->data,
|
2011-03-09 03:27:08 +07:00
|
|
|
skb_tail_pointer(skb), skb_end_pointer(skb));
|
|
|
|
|
print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
|
|
|
|
|
skb->data, 16, true);
|
2006-11-09 20:51:17 +07:00
|
|
|
#endif
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* Count how many TX buffer descriptors are needed to send this
|
|
|
|
|
* socket buffer: skb fragments of jumbo frames may need to be
|
|
|
|
|
* splitted into many buffer descriptors.
|
|
|
|
|
*/
|
|
|
|
|
count = macb_count_tx_descriptors(bp, skb_headlen(skb));
|
|
|
|
|
nr_frags = skb_shinfo(skb)->nr_frags;
|
|
|
|
|
for (f = 0; f < nr_frags; f++) {
|
|
|
|
|
frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
|
|
|
|
|
count += macb_count_tx_descriptors(bp, frag_size);
|
|
|
|
|
}
|
|
|
|
|
|
2009-08-24 09:49:07 +07:00
|
|
|
spin_lock_irqsave(&bp->lock, flags);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
/* This is a hard error, log it. */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
|
|
|
|
|
netif_stop_subqueue(dev, queue_index);
|
2009-08-24 09:49:07 +07:00
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue->tx_head, queue->tx_tail);
|
2009-06-12 13:22:29 +07:00
|
|
|
return NETDEV_TX_BUSY;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* Map socket buffer for DMA transfer */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
if (!macb_tx_map(bp, queue, skb)) {
|
2014-03-16 06:08:27 +07:00
|
|
|
dev_kfree_skb_any(skb);
|
2014-03-04 23:46:39 +07:00
|
|
|
goto unlock;
|
|
|
|
|
}
|
2012-10-31 13:04:55 +07:00
|
|
|
|
2012-10-31 13:04:51 +07:00
|
|
|
/* Make newly initialized descriptor visible to hardware */
|
2006-11-09 20:51:17 +07:00
|
|
|
wmb();
|
|
|
|
|
|
2011-06-20 04:51:28 +07:00
|
|
|
skb_tx_timestamp(skb);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
|
|
|
|
|
netif_stop_subqueue(dev, queue_index);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2014-03-04 23:46:39 +07:00
|
|
|
unlock:
|
2009-08-24 09:49:07 +07:00
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2009-06-23 13:03:08 +07:00
|
|
|
return NETDEV_TX_OK;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
|
2013-06-05 04:57:11 +07:00
|
|
|
{
|
|
|
|
|
if (!macb_is_gem(bp)) {
|
|
|
|
|
bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
|
|
|
|
|
} else {
|
2013-06-05 04:57:12 +07:00
|
|
|
bp->rx_buffer_size = size;
|
2013-06-05 04:57:11 +07:00
|
|
|
|
|
|
|
|
if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
|
2013-06-05 04:57:12 +07:00
|
|
|
netdev_dbg(bp->dev,
|
|
|
|
|
"RX buffer must be multiple of %d bytes, expanding\n",
|
2013-06-05 04:57:11 +07:00
|
|
|
RX_BUFFER_MULTIPLE);
|
|
|
|
|
bp->rx_buffer_size =
|
2013-06-05 04:57:12 +07:00
|
|
|
roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
|
2013-06-05 04:57:11 +07:00
|
|
|
}
|
|
|
|
|
}
|
2013-06-05 04:57:12 +07:00
|
|
|
|
|
|
|
|
netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
|
|
|
|
|
bp->dev->mtu, bp->rx_buffer_size);
|
2013-06-05 04:57:11 +07:00
|
|
|
}
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
static void gem_free_rx_buffers(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
struct macb_dma_desc *desc;
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (!bp->rx_skbuff)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < RX_RING_SIZE; i++) {
|
|
|
|
|
skb = bp->rx_skbuff[i];
|
|
|
|
|
|
|
|
|
|
if (skb == NULL)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
desc = &bp->rx_ring[i];
|
|
|
|
|
addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
|
2014-05-05 05:42:58 +07:00
|
|
|
dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
|
2013-06-05 04:57:12 +07:00
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
dev_kfree_skb_any(skb);
|
|
|
|
|
skb = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
kfree(bp->rx_skbuff);
|
|
|
|
|
bp->rx_skbuff = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void macb_free_rx_buffers(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
if (bp->rx_buffers) {
|
|
|
|
|
dma_free_coherent(&bp->pdev->dev,
|
|
|
|
|
RX_RING_SIZE * bp->rx_buffer_size,
|
|
|
|
|
bp->rx_buffers, bp->rx_buffers_dma);
|
|
|
|
|
bp->rx_buffers = NULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
2013-06-05 04:57:11 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static void macb_free_consistent(struct macb *bp)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue;
|
|
|
|
|
unsigned int q;
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
bp->macbgem_ops.mog_free_rx_buffers(bp);
|
2006-11-09 20:51:17 +07:00
|
|
|
if (bp->rx_ring) {
|
|
|
|
|
dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
|
|
|
|
|
bp->rx_ring, bp->rx_ring_dma);
|
|
|
|
|
bp->rx_ring = NULL;
|
|
|
|
|
}
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
|
|
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
|
|
kfree(queue->tx_skb);
|
|
|
|
|
queue->tx_skb = NULL;
|
|
|
|
|
if (queue->tx_ring) {
|
|
|
|
|
dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
|
|
|
|
|
queue->tx_ring, queue->tx_ring_dma);
|
|
|
|
|
queue->tx_ring = NULL;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
2013-06-05 04:57:12 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int gem_alloc_rx_buffers(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
int size;
|
|
|
|
|
|
|
|
|
|
size = RX_RING_SIZE * sizeof(struct sk_buff *);
|
|
|
|
|
bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
|
|
|
|
|
if (!bp->rx_skbuff)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
else
|
|
|
|
|
netdev_dbg(bp->dev,
|
|
|
|
|
"Allocated %d RX struct sk_buff entries at %p\n",
|
|
|
|
|
RX_RING_SIZE, bp->rx_skbuff);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_alloc_rx_buffers(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
int size;
|
|
|
|
|
|
|
|
|
|
size = RX_RING_SIZE * bp->rx_buffer_size;
|
|
|
|
|
bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
|
|
|
|
|
&bp->rx_buffers_dma, GFP_KERNEL);
|
|
|
|
|
if (!bp->rx_buffers)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
else
|
|
|
|
|
netdev_dbg(bp->dev,
|
|
|
|
|
"Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
|
|
|
|
|
size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
|
|
|
|
|
return 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_alloc_consistent(struct macb *bp)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue;
|
|
|
|
|
unsigned int q;
|
2006-11-09 20:51:17 +07:00
|
|
|
int size;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
|
|
size = TX_RING_BYTES;
|
|
|
|
|
queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
|
|
|
|
|
&queue->tx_ring_dma,
|
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
if (!queue->tx_ring)
|
|
|
|
|
goto out_err;
|
|
|
|
|
netdev_dbg(bp->dev,
|
|
|
|
|
"Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
|
|
|
|
|
q, size, (unsigned long)queue->tx_ring_dma,
|
|
|
|
|
queue->tx_ring);
|
|
|
|
|
|
|
|
|
|
size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
|
|
|
|
|
queue->tx_skb = kmalloc(size, GFP_KERNEL);
|
|
|
|
|
if (!queue->tx_skb)
|
|
|
|
|
goto out_err;
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
size = RX_RING_BYTES;
|
|
|
|
|
bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
|
|
|
|
|
&bp->rx_ring_dma, GFP_KERNEL);
|
|
|
|
|
if (!bp->rx_ring)
|
|
|
|
|
goto out_err;
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_dbg(bp->dev,
|
|
|
|
|
"Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
|
|
|
|
|
size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
|
2006-11-09 20:51:17 +07:00
|
|
|
goto out_err;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
out_err:
|
|
|
|
|
macb_free_consistent(bp);
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
static void gem_init_rings(struct macb *bp)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue;
|
|
|
|
|
unsigned int q;
|
2013-06-05 04:57:12 +07:00
|
|
|
int i;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
|
|
for (i = 0; i < TX_RING_SIZE; i++) {
|
|
|
|
|
queue->tx_ring[i].addr = 0;
|
|
|
|
|
queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
|
|
|
|
|
}
|
|
|
|
|
queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
|
|
|
|
|
queue->tx_head = 0;
|
|
|
|
|
queue->tx_tail = 0;
|
2013-06-05 04:57:12 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
bp->rx_tail = 0;
|
|
|
|
|
bp->rx_prepared_head = 0;
|
2013-06-05 04:57:12 +07:00
|
|
|
|
|
|
|
|
gem_rx_refill(bp);
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static void macb_init_rings(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
|
|
|
|
|
addr = bp->rx_buffers_dma;
|
|
|
|
|
for (i = 0; i < RX_RING_SIZE; i++) {
|
|
|
|
|
bp->rx_ring[i].addr = addr;
|
|
|
|
|
bp->rx_ring[i].ctrl = 0;
|
2013-06-05 04:57:11 +07:00
|
|
|
addr += bp->rx_buffer_size;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < TX_RING_SIZE; i++) {
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
bp->queues[0].tx_ring[i].addr = 0;
|
|
|
|
|
bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
|
|
|
|
|
bp->queues[0].tx_head = 0;
|
|
|
|
|
bp->queues[0].tx_tail = 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
bp->rx_tail = 0;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void macb_reset_hw(struct macb *bp)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue;
|
|
|
|
|
unsigned int q;
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
/*
|
|
|
|
|
* Disable RX and TX (XXX: Should we halt the transmission
|
|
|
|
|
* more gracefully?)
|
|
|
|
|
*/
|
|
|
|
|
macb_writel(bp, NCR, 0);
|
|
|
|
|
|
|
|
|
|
/* Clear the stats registers (XXX: Update stats first?) */
|
|
|
|
|
macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
|
|
|
|
|
|
|
|
|
|
/* Clear all status flags */
|
2012-10-22 15:45:31 +07:00
|
|
|
macb_writel(bp, TSR, -1);
|
|
|
|
|
macb_writel(bp, RSR, -1);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
/* Disable all interrupts */
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
|
|
queue_writel(queue, IDR, -1);
|
|
|
|
|
queue_readl(queue, ISR);
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2011-03-09 23:22:54 +07:00
|
|
|
static u32 gem_mdc_clk_div(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
u32 config;
|
|
|
|
|
unsigned long pclk_hz = clk_get_rate(bp->pclk);
|
|
|
|
|
|
|
|
|
|
if (pclk_hz <= 20000000)
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV8);
|
|
|
|
|
else if (pclk_hz <= 40000000)
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV16);
|
|
|
|
|
else if (pclk_hz <= 80000000)
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV32);
|
|
|
|
|
else if (pclk_hz <= 120000000)
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV48);
|
|
|
|
|
else if (pclk_hz <= 160000000)
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV64);
|
|
|
|
|
else
|
|
|
|
|
config = GEM_BF(CLK, GEM_CLK_DIV96);
|
|
|
|
|
|
|
|
|
|
return config;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 macb_mdc_clk_div(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
u32 config;
|
|
|
|
|
unsigned long pclk_hz;
|
|
|
|
|
|
|
|
|
|
if (macb_is_gem(bp))
|
|
|
|
|
return gem_mdc_clk_div(bp);
|
|
|
|
|
|
|
|
|
|
pclk_hz = clk_get_rate(bp->pclk);
|
|
|
|
|
if (pclk_hz <= 20000000)
|
|
|
|
|
config = MACB_BF(CLK, MACB_CLK_DIV8);
|
|
|
|
|
else if (pclk_hz <= 40000000)
|
|
|
|
|
config = MACB_BF(CLK, MACB_CLK_DIV16);
|
|
|
|
|
else if (pclk_hz <= 80000000)
|
|
|
|
|
config = MACB_BF(CLK, MACB_CLK_DIV32);
|
|
|
|
|
else
|
|
|
|
|
config = MACB_BF(CLK, MACB_CLK_DIV64);
|
|
|
|
|
|
|
|
|
|
return config;
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 23:29:59 +07:00
|
|
|
/*
|
|
|
|
|
* Get the DMA bus width field of the network configuration register that we
|
|
|
|
|
* should program. We find the width from decoding the design configuration
|
|
|
|
|
* register to find the maximum supported data bus width.
|
|
|
|
|
*/
|
|
|
|
|
static u32 macb_dbw(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
if (!macb_is_gem(bp))
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
|
|
|
|
|
case 4:
|
|
|
|
|
return GEM_BF(DBW, GEM_DBW128);
|
|
|
|
|
case 2:
|
|
|
|
|
return GEM_BF(DBW, GEM_DBW64);
|
|
|
|
|
case 1:
|
|
|
|
|
default:
|
|
|
|
|
return GEM_BF(DBW, GEM_DBW32);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-15 00:38:30 +07:00
|
|
|
/*
|
2012-11-23 10:49:01 +07:00
|
|
|
* Configure the receive DMA engine
|
|
|
|
|
* - use the correct receive buffer size
|
2014-07-24 18:50:58 +07:00
|
|
|
* - set best burst length for DMA operations
|
2012-11-23 10:49:01 +07:00
|
|
|
* (if not supported by FIFO, it will fallback to default)
|
|
|
|
|
* - set both rx/tx packet buffers to full memory size
|
|
|
|
|
* These are configurable parameters for GEM.
|
2011-03-15 00:38:30 +07:00
|
|
|
*/
|
|
|
|
|
static void macb_configure_dma(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
u32 dmacfg;
|
2015-03-01 13:08:02 +07:00
|
|
|
u32 tmp, ncr;
|
2011-03-15 00:38:30 +07:00
|
|
|
|
|
|
|
|
if (macb_is_gem(bp)) {
|
|
|
|
|
dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
|
2013-06-05 04:57:11 +07:00
|
|
|
dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
|
2014-07-24 18:50:58 +07:00
|
|
|
if (bp->dma_burst_length)
|
|
|
|
|
dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
|
2012-11-23 10:49:01 +07:00
|
|
|
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
|
2015-02-18 18:29:35 +07:00
|
|
|
dmacfg &= ~GEM_BIT(ENDIA_PKT);
|
2015-03-01 13:08:02 +07:00
|
|
|
|
|
|
|
|
/* Find the CPU endianness by using the loopback bit of net_ctrl
|
|
|
|
|
* register. save it first. When the CPU is in big endian we
|
|
|
|
|
* need to program swaped mode for management descriptor access.
|
|
|
|
|
*/
|
|
|
|
|
ncr = macb_readl(bp, NCR);
|
|
|
|
|
__raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
|
|
|
|
|
tmp = __raw_readl(bp->regs + MACB_NCR);
|
|
|
|
|
|
|
|
|
|
if (tmp == MACB_BIT(LLB))
|
|
|
|
|
dmacfg &= ~GEM_BIT(ENDIA_DESC);
|
|
|
|
|
else
|
|
|
|
|
dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
|
|
|
|
|
|
|
|
|
|
/* Restore net_ctrl */
|
|
|
|
|
macb_writel(bp, NCR, ncr);
|
|
|
|
|
|
2014-07-24 18:51:00 +07:00
|
|
|
if (bp->dev->features & NETIF_F_HW_CSUM)
|
|
|
|
|
dmacfg |= GEM_BIT(TXCOEN);
|
|
|
|
|
else
|
|
|
|
|
dmacfg &= ~GEM_BIT(TXCOEN);
|
2014-07-24 18:50:58 +07:00
|
|
|
netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
|
|
|
|
|
dmacfg);
|
2011-03-15 00:38:30 +07:00
|
|
|
gem_writel(bp, DMACFG, dmacfg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static void macb_init_hw(struct macb *bp)
|
|
|
|
|
{
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
struct macb_queue *queue;
|
|
|
|
|
unsigned int q;
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
u32 config;
|
|
|
|
|
|
|
|
|
|
macb_reset_hw(bp);
|
2012-11-07 15:14:52 +07:00
|
|
|
macb_set_hwaddr(bp);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2011-03-09 23:22:54 +07:00
|
|
|
config = macb_mdc_clk_div(bp);
|
2012-10-31 13:04:58 +07:00
|
|
|
config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
|
2006-11-09 20:51:17 +07:00
|
|
|
config |= MACB_BIT(PAE); /* PAuse Enable */
|
|
|
|
|
config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
|
2010-04-08 11:53:41 +07:00
|
|
|
config |= MACB_BIT(BIG); /* Receive oversized frames */
|
2006-11-09 20:51:17 +07:00
|
|
|
if (bp->dev->flags & IFF_PROMISC)
|
|
|
|
|
config |= MACB_BIT(CAF); /* Copy All Frames */
|
2014-07-24 18:51:01 +07:00
|
|
|
else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
|
|
|
|
|
config |= GEM_BIT(RXCOEN);
|
2006-11-09 20:51:17 +07:00
|
|
|
if (!(bp->dev->flags & IFF_BROADCAST))
|
|
|
|
|
config |= MACB_BIT(NBC); /* No BroadCast */
|
2011-03-09 23:29:59 +07:00
|
|
|
config |= macb_dbw(bp);
|
2006-11-09 20:51:17 +07:00
|
|
|
macb_writel(bp, NCFGR, config);
|
2012-11-02 14:09:24 +07:00
|
|
|
bp->speed = SPEED_10;
|
|
|
|
|
bp->duplex = DUPLEX_HALF;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2011-03-15 00:38:30 +07:00
|
|
|
macb_configure_dma(bp);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
/* Initialize TX and RX buffers */
|
|
|
|
|
macb_writel(bp, RBQP, bp->rx_ring_dma);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
|
|
|
|
|
queue_writel(queue, TBQP, queue->tx_ring_dma);
|
|
|
|
|
|
|
|
|
|
/* Enable interrupts */
|
|
|
|
|
queue_writel(queue, IER,
|
|
|
|
|
MACB_RX_INT_FLAGS |
|
|
|
|
|
MACB_TX_INT_FLAGS |
|
|
|
|
|
MACB_BIT(HRESP));
|
|
|
|
|
}
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
/* Enable TX and RX */
|
2007-07-13 00:07:24 +07:00
|
|
|
macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:25 +07:00
|
|
|
/*
|
|
|
|
|
* The hash address register is 64 bits long and takes up two
|
|
|
|
|
* locations in the memory map. The least significant bits are stored
|
|
|
|
|
* in EMAC_HSL and the most significant bits in EMAC_HSH.
|
|
|
|
|
*
|
|
|
|
|
* The unicast hash enable and the multicast hash enable bits in the
|
|
|
|
|
* network configuration register enable the reception of hash matched
|
|
|
|
|
* frames. The destination address is reduced to a 6 bit index into
|
|
|
|
|
* the 64 bit hash register using the following hash function. The
|
|
|
|
|
* hash function is an exclusive or of every sixth bit of the
|
|
|
|
|
* destination address.
|
|
|
|
|
*
|
|
|
|
|
* hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
|
|
|
|
|
* hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
|
|
|
|
|
* hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
|
|
|
|
|
* hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
|
|
|
|
|
* hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
|
|
|
|
|
* hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
|
|
|
|
|
*
|
|
|
|
|
* da[0] represents the least significant bit of the first byte
|
|
|
|
|
* received, that is, the multicast/unicast indicator, and da[47]
|
|
|
|
|
* represents the most significant bit of the last byte received. If
|
|
|
|
|
* the hash index, hi[n], points to a bit that is set in the hash
|
|
|
|
|
* register then the frame will be matched according to whether the
|
|
|
|
|
* frame is multicast or unicast. A multicast match will be signalled
|
|
|
|
|
* if the multicast hash enable bit is set, da[0] is 1 and the hash
|
|
|
|
|
* index points to a bit set in the hash register. A unicast match
|
|
|
|
|
* will be signalled if the unicast hash enable bit is set, da[0] is 0
|
|
|
|
|
* and the hash index points to a bit set in the hash register. To
|
|
|
|
|
* receive all multicast frames, the hash register should be set with
|
|
|
|
|
* all ones and the multicast hash enable bit should be set in the
|
|
|
|
|
* network configuration register.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static inline int hash_bit_value(int bitnr, __u8 *addr)
|
|
|
|
|
{
|
|
|
|
|
if (addr[bitnr / 8] & (1 << (bitnr % 8)))
|
|
|
|
|
return 1;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Return the hash index value for the specified address.
|
|
|
|
|
*/
|
|
|
|
|
static int hash_get_index(__u8 *addr)
|
|
|
|
|
{
|
|
|
|
|
int i, j, bitval;
|
|
|
|
|
int hash_index = 0;
|
|
|
|
|
|
|
|
|
|
for (j = 0; j < 6; j++) {
|
|
|
|
|
for (i = 0, bitval = 0; i < 8; i++)
|
2015-01-16 04:55:19 +07:00
|
|
|
bitval ^= hash_bit_value(i * 6 + j, addr);
|
2007-07-13 00:07:25 +07:00
|
|
|
|
|
|
|
|
hash_index |= (bitval << j);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return hash_index;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Add multicast addresses to the internal multicast-hash table.
|
|
|
|
|
*/
|
|
|
|
|
static void macb_sethashtable(struct net_device *dev)
|
|
|
|
|
{
|
2010-04-02 04:22:57 +07:00
|
|
|
struct netdev_hw_addr *ha;
|
2007-07-13 00:07:25 +07:00
|
|
|
unsigned long mc_filter[2];
|
2010-02-23 16:19:49 +07:00
|
|
|
unsigned int bitnr;
|
2007-07-13 00:07:25 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
mc_filter[0] = mc_filter[1] = 0;
|
|
|
|
|
|
2010-04-02 04:22:57 +07:00
|
|
|
netdev_for_each_mc_addr(ha, dev) {
|
|
|
|
|
bitnr = hash_get_index(ha->addr);
|
2007-07-13 00:07:25 +07:00
|
|
|
mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
|
|
|
|
|
}
|
|
|
|
|
|
2011-11-08 17:12:32 +07:00
|
|
|
macb_or_gem_writel(bp, HRB, mc_filter[0]);
|
|
|
|
|
macb_or_gem_writel(bp, HRT, mc_filter[1]);
|
2007-07-13 00:07:25 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Enable/Disable promiscuous and multicast modes.
|
|
|
|
|
*/
|
2015-03-07 13:23:32 +07:00
|
|
|
static void macb_set_rx_mode(struct net_device *dev)
|
2007-07-13 00:07:25 +07:00
|
|
|
{
|
|
|
|
|
unsigned long cfg;
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
cfg = macb_readl(bp, NCFGR);
|
|
|
|
|
|
2014-07-24 18:51:01 +07:00
|
|
|
if (dev->flags & IFF_PROMISC) {
|
2007-07-13 00:07:25 +07:00
|
|
|
/* Enable promiscuous mode */
|
|
|
|
|
cfg |= MACB_BIT(CAF);
|
2014-07-24 18:51:01 +07:00
|
|
|
|
|
|
|
|
/* Disable RX checksum offload */
|
|
|
|
|
if (macb_is_gem(bp))
|
|
|
|
|
cfg &= ~GEM_BIT(RXCOEN);
|
|
|
|
|
} else {
|
|
|
|
|
/* Disable promiscuous mode */
|
2007-07-13 00:07:25 +07:00
|
|
|
cfg &= ~MACB_BIT(CAF);
|
|
|
|
|
|
2014-07-24 18:51:01 +07:00
|
|
|
/* Enable RX checksum offload only if requested */
|
|
|
|
|
if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
|
|
|
|
|
cfg |= GEM_BIT(RXCOEN);
|
|
|
|
|
}
|
|
|
|
|
|
2007-07-13 00:07:25 +07:00
|
|
|
if (dev->flags & IFF_ALLMULTI) {
|
|
|
|
|
/* Enable all multicast mode */
|
2011-11-08 17:12:32 +07:00
|
|
|
macb_or_gem_writel(bp, HRB, -1);
|
|
|
|
|
macb_or_gem_writel(bp, HRT, -1);
|
2007-07-13 00:07:25 +07:00
|
|
|
cfg |= MACB_BIT(NCFGR_MTI);
|
2010-02-08 11:30:35 +07:00
|
|
|
} else if (!netdev_mc_empty(dev)) {
|
2007-07-13 00:07:25 +07:00
|
|
|
/* Enable specific multicasts */
|
|
|
|
|
macb_sethashtable(dev);
|
|
|
|
|
cfg |= MACB_BIT(NCFGR_MTI);
|
|
|
|
|
} else if (dev->flags & (~IFF_ALLMULTI)) {
|
|
|
|
|
/* Disable all multicast mode */
|
2011-11-08 17:12:32 +07:00
|
|
|
macb_or_gem_writel(bp, HRB, 0);
|
|
|
|
|
macb_or_gem_writel(bp, HRT, 0);
|
2007-07-13 00:07:25 +07:00
|
|
|
cfg &= ~MACB_BIT(NCFGR_MTI);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
macb_writel(bp, NCFGR, cfg);
|
|
|
|
|
}
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static int macb_open(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
2013-06-05 04:57:12 +07:00
|
|
|
size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
|
2006-11-09 20:51:17 +07:00
|
|
|
int err;
|
|
|
|
|
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_dbg(bp->dev, "open\n");
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-07-04 06:14:13 +07:00
|
|
|
/* carrier starts down */
|
|
|
|
|
netif_carrier_off(dev);
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* if the phy is not yet register, retry later*/
|
|
|
|
|
if (!bp->phy_dev)
|
|
|
|
|
return -EAGAIN;
|
2013-06-05 04:57:11 +07:00
|
|
|
|
|
|
|
|
/* RX buffers initialization */
|
2013-06-05 04:57:12 +07:00
|
|
|
macb_init_rx_buffer_size(bp, bufsz);
|
2007-07-13 00:07:24 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
err = macb_alloc_consistent(bp);
|
|
|
|
|
if (err) {
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
|
|
|
|
|
err);
|
2006-11-09 20:51:17 +07:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
napi_enable(&bp->napi);
|
|
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
bp->macbgem_ops.mog_init_rings(bp);
|
2006-11-09 20:51:17 +07:00
|
|
|
macb_init_hw(bp);
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* schedule a link state check */
|
|
|
|
|
phy_start(bp->phy_dev);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
netif_tx_start_all_queues(dev);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_close(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
netif_tx_stop_all_queues(dev);
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
napi_disable(&bp->napi);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
if (bp->phy_dev)
|
|
|
|
|
phy_stop(bp->phy_dev);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
spin_lock_irqsave(&bp->lock, flags);
|
|
|
|
|
macb_reset_hw(bp);
|
|
|
|
|
netif_carrier_off(dev);
|
|
|
|
|
spin_unlock_irqrestore(&bp->lock, flags);
|
|
|
|
|
|
|
|
|
|
macb_free_consistent(bp);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-03-09 23:26:35 +07:00
|
|
|
static void gem_update_stats(struct macb *bp)
|
|
|
|
|
{
|
2015-01-14 05:15:51 +07:00
|
|
|
int i;
|
2011-03-09 23:26:35 +07:00
|
|
|
u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
|
|
|
|
|
|
2015-01-14 05:15:51 +07:00
|
|
|
for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
|
|
|
|
|
u32 offset = gem_statistics[i].offset;
|
2015-02-18 18:29:35 +07:00
|
|
|
u64 val = readl_relaxed(bp->regs + offset);
|
2015-01-14 05:15:51 +07:00
|
|
|
|
|
|
|
|
bp->ethtool_stats[i] += val;
|
|
|
|
|
*p += val;
|
|
|
|
|
|
|
|
|
|
if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
|
|
|
|
|
/* Add GEM_OCTTXH, GEM_OCTRXH */
|
2015-02-18 18:29:35 +07:00
|
|
|
val = readl_relaxed(bp->regs + offset + 4);
|
2015-01-16 04:55:19 +07:00
|
|
|
bp->ethtool_stats[i] += ((u64)val) << 32;
|
2015-01-14 05:15:51 +07:00
|
|
|
*(++p) += val;
|
|
|
|
|
}
|
|
|
|
|
}
|
2011-03-09 23:26:35 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct net_device_stats *gem_get_stats(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
struct gem_stats *hwstat = &bp->hw_stats.gem;
|
|
|
|
|
struct net_device_stats *nstat = &bp->stats;
|
|
|
|
|
|
|
|
|
|
gem_update_stats(bp);
|
|
|
|
|
|
|
|
|
|
nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
|
|
|
|
|
hwstat->rx_alignment_errors +
|
|
|
|
|
hwstat->rx_resource_errors +
|
|
|
|
|
hwstat->rx_overruns +
|
|
|
|
|
hwstat->rx_oversize_frames +
|
|
|
|
|
hwstat->rx_jabbers +
|
|
|
|
|
hwstat->rx_undersized_frames +
|
|
|
|
|
hwstat->rx_length_field_frame_errors);
|
|
|
|
|
nstat->tx_errors = (hwstat->tx_late_collisions +
|
|
|
|
|
hwstat->tx_excessive_collisions +
|
|
|
|
|
hwstat->tx_underrun +
|
|
|
|
|
hwstat->tx_carrier_sense_errors);
|
|
|
|
|
nstat->multicast = hwstat->rx_multicast_frames;
|
|
|
|
|
nstat->collisions = (hwstat->tx_single_collision_frames +
|
|
|
|
|
hwstat->tx_multiple_collision_frames +
|
|
|
|
|
hwstat->tx_excessive_collisions);
|
|
|
|
|
nstat->rx_length_errors = (hwstat->rx_oversize_frames +
|
|
|
|
|
hwstat->rx_jabbers +
|
|
|
|
|
hwstat->rx_undersized_frames +
|
|
|
|
|
hwstat->rx_length_field_frame_errors);
|
|
|
|
|
nstat->rx_over_errors = hwstat->rx_resource_errors;
|
|
|
|
|
nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
|
|
|
|
|
nstat->rx_frame_errors = hwstat->rx_alignment_errors;
|
|
|
|
|
nstat->rx_fifo_errors = hwstat->rx_overruns;
|
|
|
|
|
nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
|
|
|
|
|
nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
|
|
|
|
|
nstat->tx_fifo_errors = hwstat->tx_underrun;
|
|
|
|
|
|
|
|
|
|
return nstat;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-14 05:15:51 +07:00
|
|
|
static void gem_get_ethtool_stats(struct net_device *dev,
|
|
|
|
|
struct ethtool_stats *stats, u64 *data)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp;
|
|
|
|
|
|
|
|
|
|
bp = netdev_priv(dev);
|
|
|
|
|
gem_update_stats(bp);
|
2015-01-16 04:55:19 +07:00
|
|
|
memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
|
2015-01-14 05:15:51 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int gem_get_sset_count(struct net_device *dev, int sset)
|
|
|
|
|
{
|
|
|
|
|
switch (sset) {
|
|
|
|
|
case ETH_SS_STATS:
|
|
|
|
|
return GEM_STATS_LEN;
|
|
|
|
|
default:
|
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
|
|
|
|
|
{
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
switch (sset) {
|
|
|
|
|
case ETH_SS_STATS:
|
|
|
|
|
for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
|
|
|
|
|
memcpy(p, gem_statistics[i].stat_string,
|
|
|
|
|
ETH_GSTRING_LEN);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static struct net_device_stats *macb_get_stats(struct net_device *dev)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
struct net_device_stats *nstat = &bp->stats;
|
2011-03-09 23:26:35 +07:00
|
|
|
struct macb_stats *hwstat = &bp->hw_stats.macb;
|
|
|
|
|
|
|
|
|
|
if (macb_is_gem(bp))
|
|
|
|
|
return gem_get_stats(bp);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
/* read stats from hardware */
|
|
|
|
|
macb_update_stats(bp);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
/* Convert HW stats into netdevice stats */
|
|
|
|
|
nstat->rx_errors = (hwstat->rx_fcs_errors +
|
|
|
|
|
hwstat->rx_align_errors +
|
|
|
|
|
hwstat->rx_resource_errors +
|
|
|
|
|
hwstat->rx_overruns +
|
|
|
|
|
hwstat->rx_oversize_pkts +
|
|
|
|
|
hwstat->rx_jabbers +
|
|
|
|
|
hwstat->rx_undersize_pkts +
|
|
|
|
|
hwstat->sqe_test_errors +
|
|
|
|
|
hwstat->rx_length_mismatch);
|
|
|
|
|
nstat->tx_errors = (hwstat->tx_late_cols +
|
|
|
|
|
hwstat->tx_excessive_cols +
|
|
|
|
|
hwstat->tx_underruns +
|
|
|
|
|
hwstat->tx_carrier_errors);
|
|
|
|
|
nstat->collisions = (hwstat->tx_single_cols +
|
|
|
|
|
hwstat->tx_multiple_cols +
|
|
|
|
|
hwstat->tx_excessive_cols);
|
|
|
|
|
nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
|
|
|
|
|
hwstat->rx_jabbers +
|
|
|
|
|
hwstat->rx_undersize_pkts +
|
|
|
|
|
hwstat->rx_length_mismatch);
|
2011-04-13 12:03:24 +07:00
|
|
|
nstat->rx_over_errors = hwstat->rx_resource_errors +
|
|
|
|
|
hwstat->rx_overruns;
|
2006-11-09 20:51:17 +07:00
|
|
|
nstat->rx_crc_errors = hwstat->rx_fcs_errors;
|
|
|
|
|
nstat->rx_frame_errors = hwstat->rx_align_errors;
|
|
|
|
|
nstat->rx_fifo_errors = hwstat->rx_overruns;
|
|
|
|
|
/* XXX: What does "missed" mean? */
|
|
|
|
|
nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
|
|
|
|
|
nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
|
|
|
|
|
nstat->tx_fifo_errors = hwstat->tx_underruns;
|
|
|
|
|
/* Don't know about heartbeat or window errors... */
|
|
|
|
|
|
|
|
|
|
return nstat;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
2007-07-13 00:07:24 +07:00
|
|
|
struct phy_device *phydev = bp->phy_dev;
|
|
|
|
|
|
|
|
|
|
if (!phydev)
|
|
|
|
|
return -ENODEV;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
return phy_ethtool_gset(phydev, cmd);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
2007-07-13 00:07:24 +07:00
|
|
|
struct phy_device *phydev = bp->phy_dev;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
if (!phydev)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
|
|
return phy_ethtool_sset(phydev, cmd);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2012-10-31 13:04:56 +07:00
|
|
|
static int macb_get_regs_len(struct net_device *netdev)
|
|
|
|
|
{
|
|
|
|
|
return MACB_GREGS_NBR * sizeof(u32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
|
|
|
|
|
void *p)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
unsigned int tail, head;
|
|
|
|
|
u32 *regs_buff = p;
|
|
|
|
|
|
|
|
|
|
regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
|
|
|
|
|
| MACB_GREGS_VERSION;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
|
|
|
|
|
head = macb_tx_ring_wrap(bp->queues[0].tx_head);
|
2012-10-31 13:04:56 +07:00
|
|
|
|
|
|
|
|
regs_buff[0] = macb_readl(bp, NCR);
|
|
|
|
|
regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
|
|
|
|
|
regs_buff[2] = macb_readl(bp, NSR);
|
|
|
|
|
regs_buff[3] = macb_readl(bp, TSR);
|
|
|
|
|
regs_buff[4] = macb_readl(bp, RBQP);
|
|
|
|
|
regs_buff[5] = macb_readl(bp, TBQP);
|
|
|
|
|
regs_buff[6] = macb_readl(bp, RSR);
|
|
|
|
|
regs_buff[7] = macb_readl(bp, IMR);
|
|
|
|
|
|
|
|
|
|
regs_buff[8] = tail;
|
|
|
|
|
regs_buff[9] = head;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
|
|
|
|
|
regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
|
2012-10-31 13:04:56 +07:00
|
|
|
|
|
|
|
|
if (macb_is_gem(bp)) {
|
|
|
|
|
regs_buff[12] = gem_readl(bp, USRIO);
|
|
|
|
|
regs_buff[13] = gem_readl(bp, DMACFG);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static const struct ethtool_ops macb_ethtool_ops = {
|
2006-11-09 20:51:17 +07:00
|
|
|
.get_settings = macb_get_settings,
|
|
|
|
|
.set_settings = macb_set_settings,
|
2012-10-31 13:04:56 +07:00
|
|
|
.get_regs_len = macb_get_regs_len,
|
|
|
|
|
.get_regs = macb_get_regs,
|
2006-11-09 20:51:17 +07:00
|
|
|
.get_link = ethtool_op_get_link,
|
2012-04-04 05:59:31 +07:00
|
|
|
.get_ts_info = ethtool_op_get_ts_info,
|
2015-01-16 04:55:20 +07:00
|
|
|
};
|
|
|
|
|
|
2015-02-05 23:21:07 +07:00
|
|
|
static const struct ethtool_ops gem_ethtool_ops = {
|
2015-01-16 04:55:20 +07:00
|
|
|
.get_settings = macb_get_settings,
|
|
|
|
|
.set_settings = macb_set_settings,
|
|
|
|
|
.get_regs_len = macb_get_regs_len,
|
|
|
|
|
.get_regs = macb_get_regs,
|
|
|
|
|
.get_link = ethtool_op_get_link,
|
|
|
|
|
.get_ts_info = ethtool_op_get_ts_info,
|
2015-01-14 05:15:51 +07:00
|
|
|
.get_ethtool_stats = gem_get_ethtool_stats,
|
|
|
|
|
.get_strings = gem_get_ethtool_strings,
|
|
|
|
|
.get_sset_count = gem_get_sset_count,
|
2006-11-09 20:51:17 +07:00
|
|
|
};
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
2007-07-13 00:07:24 +07:00
|
|
|
struct phy_device *phydev = bp->phy_dev;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
if (!netif_running(dev))
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
if (!phydev)
|
|
|
|
|
return -ENODEV;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2010-07-17 15:48:55 +07:00
|
|
|
return phy_mii_ioctl(phydev, rq, cmd);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:51:00 +07:00
|
|
|
static int macb_set_features(struct net_device *netdev,
|
|
|
|
|
netdev_features_t features)
|
|
|
|
|
{
|
|
|
|
|
struct macb *bp = netdev_priv(netdev);
|
|
|
|
|
netdev_features_t changed = features ^ netdev->features;
|
|
|
|
|
|
|
|
|
|
/* TX checksum offload */
|
|
|
|
|
if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
|
|
|
|
|
u32 dmacfg;
|
|
|
|
|
|
|
|
|
|
dmacfg = gem_readl(bp, DMACFG);
|
|
|
|
|
if (features & NETIF_F_HW_CSUM)
|
|
|
|
|
dmacfg |= GEM_BIT(TXCOEN);
|
|
|
|
|
else
|
|
|
|
|
dmacfg &= ~GEM_BIT(TXCOEN);
|
|
|
|
|
gem_writel(bp, DMACFG, dmacfg);
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:51:01 +07:00
|
|
|
/* RX checksum offload */
|
|
|
|
|
if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
|
|
|
|
|
u32 netcfg;
|
|
|
|
|
|
|
|
|
|
netcfg = gem_readl(bp, NCFGR);
|
|
|
|
|
if (features & NETIF_F_RXCSUM &&
|
|
|
|
|
!(netdev->flags & IFF_PROMISC))
|
|
|
|
|
netcfg |= GEM_BIT(RXCOEN);
|
|
|
|
|
else
|
|
|
|
|
netcfg &= ~GEM_BIT(RXCOEN);
|
|
|
|
|
gem_writel(bp, NCFGR, netcfg);
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:51:00 +07:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-04-11 14:42:26 +07:00
|
|
|
static const struct net_device_ops macb_netdev_ops = {
|
|
|
|
|
.ndo_open = macb_open,
|
|
|
|
|
.ndo_stop = macb_close,
|
|
|
|
|
.ndo_start_xmit = macb_start_xmit,
|
2011-08-16 13:29:01 +07:00
|
|
|
.ndo_set_rx_mode = macb_set_rx_mode,
|
2009-04-11 14:42:26 +07:00
|
|
|
.ndo_get_stats = macb_get_stats,
|
|
|
|
|
.ndo_do_ioctl = macb_ioctl,
|
|
|
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
|
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
|
|
|
.ndo_set_mac_address = eth_mac_addr,
|
2009-05-05 01:08:41 +07:00
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
.ndo_poll_controller = macb_poll_controller,
|
|
|
|
|
#endif
|
2014-07-24 18:51:00 +07:00
|
|
|
.ndo_set_features = macb_set_features,
|
2009-04-11 14:42:26 +07:00
|
|
|
};
|
|
|
|
|
|
2014-07-24 18:50:58 +07:00
|
|
|
/*
|
|
|
|
|
* Configure peripheral capacities according to device tree
|
|
|
|
|
* and integration options used
|
|
|
|
|
*/
|
|
|
|
|
static void macb_configure_caps(struct macb *bp)
|
|
|
|
|
{
|
|
|
|
|
u32 dcfg;
|
|
|
|
|
|
|
|
|
|
if (MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2)
|
|
|
|
|
bp->caps |= MACB_CAPS_MACB_IS_GEM;
|
|
|
|
|
|
|
|
|
|
if (macb_is_gem(bp)) {
|
|
|
|
|
dcfg = gem_readl(bp, DCFG1);
|
|
|
|
|
if (GEM_BFEXT(IRQCOR, dcfg) == 0)
|
|
|
|
|
bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
|
|
|
|
|
dcfg = gem_readl(bp, DCFG2);
|
|
|
|
|
if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
|
|
|
|
|
bp->caps |= MACB_CAPS_FIFO_MODE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
|
|
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
static void macb_probe_queues(void __iomem *mem,
|
|
|
|
|
unsigned int *queue_mask,
|
|
|
|
|
unsigned int *num_queues)
|
|
|
|
|
{
|
|
|
|
|
unsigned int hw_q;
|
|
|
|
|
u32 mid;
|
|
|
|
|
|
|
|
|
|
*queue_mask = 0x1;
|
|
|
|
|
*num_queues = 1;
|
|
|
|
|
|
|
|
|
|
/* is it macb or gem ? */
|
2015-02-18 18:29:35 +07:00
|
|
|
mid = readl_relaxed(mem + MACB_MID);
|
|
|
|
|
|
2015-03-07 00:29:11 +07:00
|
|
|
if (MACB_BFEXT(IDNUM, mid) < 0x2)
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
/* bit 0 is never set but queue 0 always exists */
|
2015-02-18 18:29:35 +07:00
|
|
|
*queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
*queue_mask |= 0x1;
|
|
|
|
|
|
|
|
|
|
for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
|
|
|
|
|
if (*queue_mask & (1 << hw_q))
|
|
|
|
|
(*num_queues)++;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
static int macb_init(struct platform_device *pdev)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
2015-03-07 13:23:32 +07:00
|
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
2014-12-15 21:13:32 +07:00
|
|
|
unsigned int hw_q, queue_mask, q, num_queues;
|
2015-03-07 13:23:32 +07:00
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
struct macb_queue *queue;
|
|
|
|
|
int err;
|
|
|
|
|
u32 val;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
bp->pclk = devm_clk_get(&pdev->dev, "pclk");
|
|
|
|
|
if (IS_ERR(bp->pclk)) {
|
|
|
|
|
err = PTR_ERR(bp->pclk);
|
2013-12-11 07:07:20 +07:00
|
|
|
dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
|
2015-03-07 13:23:32 +07:00
|
|
|
return err;
|
2007-02-07 22:40:44 +07:00
|
|
|
}
|
2011-03-09 03:19:23 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
bp->hclk = devm_clk_get(&pdev->dev, "hclk");
|
|
|
|
|
if (IS_ERR(bp->hclk)) {
|
|
|
|
|
err = PTR_ERR(bp->hclk);
|
2013-12-11 07:07:20 +07:00
|
|
|
dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
|
2015-03-07 13:23:32 +07:00
|
|
|
return err;
|
2013-12-11 07:07:20 +07:00
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
|
|
|
|
|
if (IS_ERR(bp->tx_clk))
|
|
|
|
|
bp->tx_clk = NULL;
|
2013-12-11 07:07:23 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
err = clk_prepare_enable(bp->pclk);
|
2013-12-11 07:07:20 +07:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
|
2015-03-07 13:23:32 +07:00
|
|
|
return err;
|
2013-12-11 07:07:20 +07:00
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
err = clk_prepare_enable(bp->hclk);
|
2013-12-11 07:07:20 +07:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
|
2015-03-07 13:23:32 +07:00
|
|
|
goto err_disable_pclk;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
err = clk_prepare_enable(bp->tx_clk);
|
2015-03-07 13:23:31 +07:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
|
2015-03-07 13:23:32 +07:00
|
|
|
goto err_disable_hclk;
|
2013-12-11 07:07:23 +07:00
|
|
|
}
|
|
|
|
|
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
/* set the queue register mapping once for all: queue0 has a special
|
|
|
|
|
* register mapping but we don't want to test the queue index then
|
|
|
|
|
* compute the corresponding register offset at run time.
|
|
|
|
|
*/
|
2015-03-07 13:23:32 +07:00
|
|
|
macb_probe_queues(bp->regs, &queue_mask, &num_queues);
|
|
|
|
|
|
2014-12-15 21:13:32 +07:00
|
|
|
for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
if (!(queue_mask & (1 << hw_q)))
|
|
|
|
|
continue;
|
|
|
|
|
|
2014-12-15 21:13:32 +07:00
|
|
|
queue = &bp->queues[q];
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
queue->bp = bp;
|
|
|
|
|
if (hw_q) {
|
|
|
|
|
queue->ISR = GEM_ISR(hw_q - 1);
|
|
|
|
|
queue->IER = GEM_IER(hw_q - 1);
|
|
|
|
|
queue->IDR = GEM_IDR(hw_q - 1);
|
|
|
|
|
queue->IMR = GEM_IMR(hw_q - 1);
|
|
|
|
|
queue->TBQP = GEM_TBQP(hw_q - 1);
|
|
|
|
|
} else {
|
|
|
|
|
/* queue0 uses legacy registers */
|
|
|
|
|
queue->ISR = MACB_ISR;
|
|
|
|
|
queue->IER = MACB_IER;
|
|
|
|
|
queue->IDR = MACB_IDR;
|
|
|
|
|
queue->IMR = MACB_IMR;
|
|
|
|
|
queue->TBQP = MACB_TBQP;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* get irq: here we use the linux queue index, not the hardware
|
|
|
|
|
* queue index. the queue irq definitions in the device tree
|
|
|
|
|
* must remove the optional gaps that could exist in the
|
|
|
|
|
* hardware queue mask.
|
|
|
|
|
*/
|
2014-12-15 21:13:32 +07:00
|
|
|
queue->irq = platform_get_irq(pdev, q);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
|
2015-03-07 00:29:12 +07:00
|
|
|
IRQF_SHARED, dev->name, queue);
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"Unable to request IRQ %d (error %d)\n",
|
|
|
|
|
queue->irq, err);
|
2015-03-07 13:23:32 +07:00
|
|
|
goto err_disable_tx_clk;
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
|
2014-12-15 21:13:32 +07:00
|
|
|
q++;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2009-04-11 14:42:26 +07:00
|
|
|
dev->netdev_ops = &macb_netdev_ops;
|
[NET]: Make NAPI polling independent of struct net_device objects.
Several devices have multiple independant RX queues per net
device, and some have a single interrupt doorbell for several
queues.
In either case, it's easier to support layouts like that if the
structure representing the poll is independant from the net
device itself.
The signature of the ->poll() call back goes from:
int foo_poll(struct net_device *dev, int *budget)
to
int foo_poll(struct napi_struct *napi, int budget)
The caller is returned the number of RX packets processed (or
the number of "NAPI credits" consumed if you want to get
abstract). The callee no longer messes around bumping
dev->quota, *budget, etc. because that is all handled in the
caller upon return.
The napi_struct is to be embedded in the device driver private data
structures.
Furthermore, it is the driver's responsibility to disable all NAPI
instances in it's ->stop() device close handler. Since the
napi_struct is privatized into the driver's private data structures,
only the driver knows how to get at all of the napi_struct instances
it may have per-device.
With lots of help and suggestions from Rusty Russell, Roland Dreier,
Michael Chan, Jeff Garzik, and Jamal Hadi Salim.
Bug fixes from Thomas Graf, Roland Dreier, Peter Zijlstra,
Joseph Fannin, Scott Wood, Hans J. Koch, and Michael Chan.
[ Ported to current tree and all drivers converted. Integrated
Stephen's follow-on kerneldoc additions, and restored poll_list
handling to the old style to fix mutual exclusion issues. -DaveM ]
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2007-10-04 06:41:36 +07:00
|
|
|
netif_napi_add(dev, &bp->napi, macb_poll, 64);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2013-06-05 04:57:12 +07:00
|
|
|
/* setup appropriated routines according to adapter type */
|
|
|
|
|
if (macb_is_gem(bp)) {
|
2014-07-24 18:50:59 +07:00
|
|
|
bp->max_tx_length = GEM_MAX_TX_LEN;
|
2013-06-05 04:57:12 +07:00
|
|
|
bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
|
|
|
|
|
bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
|
|
|
|
|
bp->macbgem_ops.mog_init_rings = gem_init_rings;
|
|
|
|
|
bp->macbgem_ops.mog_rx = gem_rx;
|
2015-01-16 04:55:20 +07:00
|
|
|
dev->ethtool_ops = &gem_ethtool_ops;
|
2013-06-05 04:57:12 +07:00
|
|
|
} else {
|
2014-07-24 18:50:59 +07:00
|
|
|
bp->max_tx_length = MACB_MAX_TX_LEN;
|
2013-06-05 04:57:12 +07:00
|
|
|
bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
|
|
|
|
|
bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
|
|
|
|
|
bp->macbgem_ops.mog_init_rings = macb_init_rings;
|
|
|
|
|
bp->macbgem_ops.mog_rx = macb_rx;
|
2015-01-16 04:55:20 +07:00
|
|
|
dev->ethtool_ops = &macb_ethtool_ops;
|
2013-06-05 04:57:12 +07:00
|
|
|
}
|
|
|
|
|
|
2014-07-24 18:50:59 +07:00
|
|
|
/* Set features */
|
|
|
|
|
dev->hw_features = NETIF_F_SG;
|
2014-07-24 18:51:00 +07:00
|
|
|
/* Checksum offload is only available on gem with packet buffer */
|
|
|
|
|
if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
|
2014-07-24 18:51:01 +07:00
|
|
|
dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
|
2014-07-24 18:50:59 +07:00
|
|
|
if (bp->caps & MACB_CAPS_SG_DISABLED)
|
|
|
|
|
dev->hw_features &= ~NETIF_F_SG;
|
|
|
|
|
dev->features = dev->hw_features;
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
val = 0;
|
|
|
|
|
if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
|
|
|
|
|
val = GEM_BIT(RGMII);
|
|
|
|
|
else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
|
|
|
|
|
(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
|
|
|
|
|
val = MACB_BIT(RMII);
|
|
|
|
|
else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
|
|
|
|
|
val = MACB_BIT(MII);
|
|
|
|
|
|
|
|
|
|
if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
|
|
|
|
|
val |= MACB_BIT(CLKEN);
|
|
|
|
|
|
|
|
|
|
macb_or_gem_writel(bp, USRIO, val);
|
|
|
|
|
|
|
|
|
|
/* setup capacities */
|
|
|
|
|
macb_configure_caps(bp);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
/* Set MII management clock divider */
|
2015-03-07 13:23:32 +07:00
|
|
|
val = macb_mdc_clk_div(bp);
|
|
|
|
|
val |= macb_dbw(bp);
|
|
|
|
|
macb_writel(bp, NCFGR, val);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_disable_tx_clk:
|
|
|
|
|
clk_disable_unprepare(bp->tx_clk);
|
|
|
|
|
|
|
|
|
|
err_disable_hclk:
|
|
|
|
|
clk_disable_unprepare(bp->hclk);
|
|
|
|
|
|
|
|
|
|
err_disable_pclk:
|
|
|
|
|
clk_disable_unprepare(bp->pclk);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
|
/* 1518 rounded up */
|
|
|
|
|
#define AT91ETHER_MAX_RBUFF_SZ 0x600
|
|
|
|
|
/* max number of receive buffers */
|
|
|
|
|
#define AT91ETHER_MAX_RX_DESCR 9
|
|
|
|
|
|
|
|
|
|
/* Initialize and start the Receiver and Transmit subsystems */
|
|
|
|
|
static int at91ether_start(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
dma_addr_t addr;
|
|
|
|
|
u32 ctl;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
|
|
|
|
|
(AT91ETHER_MAX_RX_DESCR *
|
|
|
|
|
sizeof(struct macb_dma_desc)),
|
|
|
|
|
&lp->rx_ring_dma, GFP_KERNEL);
|
|
|
|
|
if (!lp->rx_ring)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
|
|
|
|
|
AT91ETHER_MAX_RX_DESCR *
|
|
|
|
|
AT91ETHER_MAX_RBUFF_SZ,
|
|
|
|
|
&lp->rx_buffers_dma, GFP_KERNEL);
|
|
|
|
|
if (!lp->rx_buffers) {
|
|
|
|
|
dma_free_coherent(&lp->pdev->dev,
|
|
|
|
|
AT91ETHER_MAX_RX_DESCR *
|
|
|
|
|
sizeof(struct macb_dma_desc),
|
|
|
|
|
lp->rx_ring, lp->rx_ring_dma);
|
|
|
|
|
lp->rx_ring = NULL;
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
addr = lp->rx_buffers_dma;
|
|
|
|
|
for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
|
|
|
|
|
lp->rx_ring[i].addr = addr;
|
|
|
|
|
lp->rx_ring[i].ctrl = 0;
|
|
|
|
|
addr += AT91ETHER_MAX_RBUFF_SZ;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set the Wrap bit on the last descriptor */
|
|
|
|
|
lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
|
|
|
|
|
|
|
|
|
|
/* Reset buffer index */
|
|
|
|
|
lp->rx_tail = 0;
|
|
|
|
|
|
|
|
|
|
/* Program address of descriptor list in Rx Buffer Queue register */
|
|
|
|
|
macb_writel(lp, RBQP, lp->rx_ring_dma);
|
|
|
|
|
|
|
|
|
|
/* Enable Receive and Transmit */
|
|
|
|
|
ctl = macb_readl(lp, NCR);
|
|
|
|
|
macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Open the ethernet interface */
|
|
|
|
|
static int at91ether_open(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
u32 ctl;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
/* Clear internal statistics */
|
|
|
|
|
ctl = macb_readl(lp, NCR);
|
|
|
|
|
macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
|
|
|
|
|
|
|
|
|
|
macb_set_hwaddr(lp);
|
|
|
|
|
|
|
|
|
|
ret = at91ether_start(dev);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
|
|
/* Enable MAC interrupts */
|
|
|
|
|
macb_writel(lp, IER, MACB_BIT(RCOMP) |
|
|
|
|
|
MACB_BIT(RXUBR) |
|
|
|
|
|
MACB_BIT(ISR_TUND) |
|
|
|
|
|
MACB_BIT(ISR_RLE) |
|
|
|
|
|
MACB_BIT(TCOMP) |
|
|
|
|
|
MACB_BIT(ISR_ROVR) |
|
|
|
|
|
MACB_BIT(HRESP));
|
|
|
|
|
|
|
|
|
|
/* schedule a link state check */
|
|
|
|
|
phy_start(lp->phy_dev);
|
|
|
|
|
|
|
|
|
|
netif_start_queue(dev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Close the interface */
|
|
|
|
|
static int at91ether_close(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
u32 ctl;
|
|
|
|
|
|
|
|
|
|
/* Disable Receiver and Transmitter */
|
|
|
|
|
ctl = macb_readl(lp, NCR);
|
|
|
|
|
macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
|
|
|
|
|
|
|
|
|
|
/* Disable MAC interrupts */
|
|
|
|
|
macb_writel(lp, IDR, MACB_BIT(RCOMP) |
|
|
|
|
|
MACB_BIT(RXUBR) |
|
|
|
|
|
MACB_BIT(ISR_TUND) |
|
|
|
|
|
MACB_BIT(ISR_RLE) |
|
|
|
|
|
MACB_BIT(TCOMP) |
|
|
|
|
|
MACB_BIT(ISR_ROVR) |
|
|
|
|
|
MACB_BIT(HRESP));
|
|
|
|
|
|
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
|
|
|
|
|
|
dma_free_coherent(&lp->pdev->dev,
|
|
|
|
|
AT91ETHER_MAX_RX_DESCR *
|
|
|
|
|
sizeof(struct macb_dma_desc),
|
|
|
|
|
lp->rx_ring, lp->rx_ring_dma);
|
|
|
|
|
lp->rx_ring = NULL;
|
|
|
|
|
|
|
|
|
|
dma_free_coherent(&lp->pdev->dev,
|
|
|
|
|
AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
|
|
|
|
|
lp->rx_buffers, lp->rx_buffers_dma);
|
|
|
|
|
lp->rx_buffers = NULL;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Transmit packet */
|
|
|
|
|
static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
|
|
|
|
|
if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
|
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
|
|
|
|
|
|
/* Store packet information (to free when Tx completed) */
|
|
|
|
|
lp->skb = skb;
|
|
|
|
|
lp->skb_length = skb->len;
|
|
|
|
|
lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
|
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
|
|
|
|
|
/* Set address of the data in the Transmit Address register */
|
|
|
|
|
macb_writel(lp, TAR, lp->skb_physaddr);
|
|
|
|
|
/* Set length of the packet in the Transmit Control register */
|
|
|
|
|
macb_writel(lp, TCR, skb->len);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
} else {
|
|
|
|
|
netdev_err(dev, "%s called, but device is busy!\n", __func__);
|
|
|
|
|
return NETDEV_TX_BUSY;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Extract received frame from buffer descriptors and sent to upper layers.
|
|
|
|
|
* (Called from interrupt context)
|
|
|
|
|
*/
|
|
|
|
|
static void at91ether_rx(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
unsigned char *p_recv;
|
|
|
|
|
struct sk_buff *skb;
|
|
|
|
|
unsigned int pktlen;
|
|
|
|
|
|
|
|
|
|
while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
|
|
|
|
|
p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
|
|
|
|
|
pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
|
|
|
|
|
skb = netdev_alloc_skb(dev, pktlen + 2);
|
|
|
|
|
if (skb) {
|
|
|
|
|
skb_reserve(skb, 2);
|
|
|
|
|
memcpy(skb_put(skb, pktlen), p_recv, pktlen);
|
|
|
|
|
|
|
|
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
|
|
|
lp->stats.rx_packets++;
|
|
|
|
|
lp->stats.rx_bytes += pktlen;
|
|
|
|
|
netif_rx(skb);
|
|
|
|
|
} else {
|
|
|
|
|
lp->stats.rx_dropped++;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
|
|
|
|
|
lp->stats.multicast++;
|
|
|
|
|
|
|
|
|
|
/* reset ownership bit */
|
|
|
|
|
lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
|
|
|
|
|
|
|
|
|
|
/* wrap after last buffer */
|
|
|
|
|
if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
|
|
|
|
|
lp->rx_tail = 0;
|
|
|
|
|
else
|
|
|
|
|
lp->rx_tail++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* MAC interrupt handler */
|
|
|
|
|
static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = dev_id;
|
|
|
|
|
struct macb *lp = netdev_priv(dev);
|
|
|
|
|
u32 intstatus, ctl;
|
|
|
|
|
|
|
|
|
|
/* MAC Interrupt Status register indicates what interrupts are pending.
|
|
|
|
|
* It is automatically cleared once read.
|
|
|
|
|
*/
|
|
|
|
|
intstatus = macb_readl(lp, ISR);
|
|
|
|
|
|
|
|
|
|
/* Receive complete */
|
|
|
|
|
if (intstatus & MACB_BIT(RCOMP))
|
|
|
|
|
at91ether_rx(dev);
|
|
|
|
|
|
|
|
|
|
/* Transmit complete */
|
|
|
|
|
if (intstatus & MACB_BIT(TCOMP)) {
|
|
|
|
|
/* The TCOM bit is set even if the transmission failed */
|
|
|
|
|
if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
|
|
|
|
|
lp->stats.tx_errors++;
|
|
|
|
|
|
|
|
|
|
if (lp->skb) {
|
|
|
|
|
dev_kfree_skb_irq(lp->skb);
|
|
|
|
|
lp->skb = NULL;
|
|
|
|
|
dma_unmap_single(NULL, lp->skb_physaddr,
|
|
|
|
|
lp->skb_length, DMA_TO_DEVICE);
|
|
|
|
|
lp->stats.tx_packets++;
|
|
|
|
|
lp->stats.tx_bytes += lp->skb_length;
|
|
|
|
|
}
|
|
|
|
|
netif_wake_queue(dev);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Work-around for EMAC Errata section 41.3.1 */
|
|
|
|
|
if (intstatus & MACB_BIT(RXUBR)) {
|
|
|
|
|
ctl = macb_readl(lp, NCR);
|
|
|
|
|
macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
|
|
|
|
|
macb_writel(lp, NCR, ctl | MACB_BIT(RE));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (intstatus & MACB_BIT(ISR_ROVR))
|
|
|
|
|
netdev_err(dev, "ROVR error\n");
|
|
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
static void at91ether_poll_controller(struct net_device *dev)
|
|
|
|
|
{
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
at91ether_interrupt(dev->irq, dev);
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
static const struct net_device_ops at91ether_netdev_ops = {
|
|
|
|
|
.ndo_open = at91ether_open,
|
|
|
|
|
.ndo_stop = at91ether_close,
|
|
|
|
|
.ndo_start_xmit = at91ether_start_xmit,
|
|
|
|
|
.ndo_get_stats = macb_get_stats,
|
|
|
|
|
.ndo_set_rx_mode = macb_set_rx_mode,
|
|
|
|
|
.ndo_set_mac_address = eth_mac_addr,
|
|
|
|
|
.ndo_do_ioctl = macb_ioctl,
|
|
|
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
|
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
|
|
|
.ndo_poll_controller = at91ether_poll_controller,
|
|
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int at91ether_init(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
|
|
|
struct macb *bp = netdev_priv(dev);
|
|
|
|
|
int err;
|
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
|
|
bp->pclk = devm_clk_get(&pdev->dev, "ether_clk");
|
|
|
|
|
if (IS_ERR(bp->pclk))
|
|
|
|
|
return PTR_ERR(bp->pclk);
|
|
|
|
|
|
|
|
|
|
err = clk_prepare_enable(bp->pclk);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev->netdev_ops = &at91ether_netdev_ops;
|
|
|
|
|
dev->ethtool_ops = &macb_ethtool_ops;
|
|
|
|
|
|
|
|
|
|
err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
|
|
|
|
|
0, dev->name, dev);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_disable_clk;
|
|
|
|
|
|
|
|
|
|
macb_writel(bp, NCR, 0);
|
|
|
|
|
|
|
|
|
|
reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
|
|
|
|
|
if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
|
|
|
|
|
reg |= MACB_BIT(RM9200_RMII);
|
|
|
|
|
|
|
|
|
|
macb_writel(bp, NCFGR, reg);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
err_disable_clk:
|
|
|
|
|
clk_disable_unprepare(bp->pclk);
|
|
|
|
|
|
|
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-10 10:38:02 +07:00
|
|
|
static const struct macb_config at91sam9260_config = {
|
2015-03-07 13:23:32 +07:00
|
|
|
.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
|
|
|
|
|
.init = macb_init,
|
|
|
|
|
};
|
|
|
|
|
|
2015-03-10 10:38:02 +07:00
|
|
|
static const struct macb_config pc302gem_config = {
|
2015-03-07 13:23:32 +07:00
|
|
|
.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
|
|
|
|
|
.dma_burst_length = 16,
|
|
|
|
|
.init = macb_init,
|
|
|
|
|
};
|
|
|
|
|
|
2015-03-10 10:38:02 +07:00
|
|
|
static const struct macb_config sama5d3_config = {
|
2015-03-07 13:23:32 +07:00
|
|
|
.caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
|
|
|
|
|
.dma_burst_length = 16,
|
|
|
|
|
.init = macb_init,
|
|
|
|
|
};
|
|
|
|
|
|
2015-03-10 10:38:02 +07:00
|
|
|
static const struct macb_config sama5d4_config = {
|
2015-03-07 13:23:32 +07:00
|
|
|
.caps = 0,
|
|
|
|
|
.dma_burst_length = 4,
|
|
|
|
|
.init = macb_init,
|
|
|
|
|
};
|
|
|
|
|
|
2015-03-10 10:38:02 +07:00
|
|
|
static const struct macb_config emac_config = {
|
2015-03-07 13:23:32 +07:00
|
|
|
.init = at91ether_init,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct of_device_id macb_dt_ids[] = {
|
|
|
|
|
{ .compatible = "cdns,at32ap7000-macb" },
|
|
|
|
|
{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
|
|
|
|
|
{ .compatible = "cdns,macb" },
|
|
|
|
|
{ .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
|
|
|
|
|
{ .compatible = "cdns,gem", .data = &pc302gem_config },
|
|
|
|
|
{ .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
|
|
|
|
|
{ .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
|
|
|
|
|
{ .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
|
|
|
|
|
{ .compatible = "cdns,emac", .data = &emac_config },
|
|
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, macb_dt_ids);
|
|
|
|
|
#endif /* CONFIG_OF */
|
|
|
|
|
|
|
|
|
|
static int macb_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
int (*init)(struct platform_device *) = macb_init;
|
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
|
const struct macb_config *macb_config = NULL;
|
|
|
|
|
unsigned int queue_mask, num_queues;
|
|
|
|
|
struct macb_platform_data *pdata;
|
|
|
|
|
struct phy_device *phydev;
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct resource *regs;
|
|
|
|
|
void __iomem *mem;
|
|
|
|
|
const char *mac;
|
|
|
|
|
struct macb *bp;
|
|
|
|
|
int err;
|
|
|
|
|
|
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
|
mem = devm_ioremap_resource(&pdev->dev, regs);
|
|
|
|
|
if (IS_ERR(mem))
|
|
|
|
|
return PTR_ERR(mem);
|
|
|
|
|
|
|
|
|
|
macb_probe_queues(mem, &queue_mask, &num_queues);
|
|
|
|
|
dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
|
|
|
|
|
if (!dev)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
dev->base_addr = regs->start;
|
|
|
|
|
|
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
|
|
|
|
|
|
bp = netdev_priv(dev);
|
|
|
|
|
bp->pdev = pdev;
|
|
|
|
|
bp->dev = dev;
|
|
|
|
|
bp->regs = mem;
|
|
|
|
|
bp->num_queues = num_queues;
|
|
|
|
|
spin_lock_init(&bp->lock);
|
|
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
|
|
|
|
|
|
dev->irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (dev->irq < 0)
|
|
|
|
|
return dev->irq;
|
|
|
|
|
|
|
|
|
|
mac = of_get_mac_address(np);
|
2013-04-02 16:35:09 +07:00
|
|
|
if (mac)
|
|
|
|
|
memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
|
|
|
|
|
else
|
2011-11-18 21:29:25 +07:00
|
|
|
macb_get_hwaddr(bp);
|
|
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
err = of_get_phy_mode(np);
|
2011-11-18 21:29:25 +07:00
|
|
|
if (err < 0) {
|
2013-08-30 12:12:21 +07:00
|
|
|
pdata = dev_get_platdata(&pdev->dev);
|
2011-11-18 21:29:25 +07:00
|
|
|
if (pdata && pdata->is_rmii)
|
|
|
|
|
bp->phy_interface = PHY_INTERFACE_MODE_RMII;
|
|
|
|
|
else
|
|
|
|
|
bp->phy_interface = PHY_INTERFACE_MODE_MII;
|
|
|
|
|
} else {
|
|
|
|
|
bp->phy_interface = err;
|
|
|
|
|
}
|
2007-07-13 00:07:24 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
if (np) {
|
|
|
|
|
const struct of_device_id *match;
|
2015-03-07 13:23:30 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
match = of_match_node(macb_dt_ids, np);
|
|
|
|
|
if (match)
|
|
|
|
|
macb_config = match->data;
|
|
|
|
|
}
|
2015-03-07 13:23:30 +07:00
|
|
|
|
2015-03-07 13:23:32 +07:00
|
|
|
if (macb_config) {
|
|
|
|
|
bp->caps = macb_config->caps;
|
|
|
|
|
bp->dma_burst_length = macb_config->dma_burst_length;
|
|
|
|
|
init = macb_config->init;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* IP specific init */
|
|
|
|
|
err = init(pdev);
|
|
|
|
|
if (err)
|
|
|
|
|
goto err_out_free_netdev;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
err = register_netdev(dev);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
|
2015-03-07 13:23:32 +07:00
|
|
|
goto err_disable_clocks;
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
2013-04-15 05:04:33 +07:00
|
|
|
err = macb_mii_init(bp);
|
|
|
|
|
if (err)
|
2007-07-13 00:07:24 +07:00
|
|
|
goto err_out_unregister_netdev;
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2012-07-04 06:14:13 +07:00
|
|
|
netif_carrier_off(dev);
|
|
|
|
|
|
2014-09-13 06:57:49 +07:00
|
|
|
netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
|
|
|
|
|
macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
|
|
|
|
|
dev->base_addr, dev->irq, dev->dev_addr);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
phydev = bp->phy_dev;
|
2011-03-09 03:27:08 +07:00
|
|
|
netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
|
|
|
|
|
phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
|
2007-07-13 00:07:24 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
return 0;
|
|
|
|
|
|
2007-07-13 00:07:24 +07:00
|
|
|
err_out_unregister_netdev:
|
|
|
|
|
unregister_netdev(dev);
|
2015-03-07 13:23:32 +07:00
|
|
|
|
|
|
|
|
err_disable_clocks:
|
|
|
|
|
clk_disable_unprepare(bp->tx_clk);
|
|
|
|
|
clk_disable_unprepare(bp->hclk);
|
|
|
|
|
clk_disable_unprepare(bp->pclk);
|
|
|
|
|
|
2014-12-15 21:13:32 +07:00
|
|
|
err_out_free_netdev:
|
net/macb: add TX multiqueue support for gem
gem devices designed with multiqueue CANNOT work without this patch.
When probing a gem device, the driver must first prepare and enable the
peripheral clock before accessing I/O registers. The second step is to read the
MID register to find whether the device is a gem or an old macb IP.
For gem devices, it reads the Design Configuration Register 6 (DCFG6) to
compute to total number of queues, whereas macb devices always have a single
queue.
Only then it can call alloc_etherdev_mq() with the correct number of queues.
This is the reason why the order of some initializations has been changed in
macb_probe().
Eventually, the dedicated IRQ and TX ring buffer descriptors are initialized
for each queue.
For backward compatibility reasons, queue0 uses the legacy registers ISR, IER,
IDR, IMR, TBQP and RBQP. On the other hand, the other queues use new registers
ISR[1..7], IER[1..7], IDR[1..7], IMR[1..7], TBQP[1..7] and RBQP[1..7].
Except this hardware detail there is no real difference between queue0 and the
others. The driver hides that thanks to the struct macb_queue.
This structure allows us to share a common set of functions for all the queues.
Besides when a TX error occurs, the gem MUST be halted before writing any of
the TBQP registers to reset the relevant queue. An immediate side effect is
that the other queues too aren't processed anymore by the gem.
So macb_tx_error_task() calls netif_tx_stop_all_queues() to notify the Linux
network engine that all transmissions are stopped.
Also macb_tx_error_task() now calls spin_lock_irqsave() to prevent the
interrupt handlers of the other queues from running as each of them may wake
its associated queue up (please refer to macb_tx_interrupt()).
Finally, as all queues have previously been stopped, they should be restarted
calling netif_tx_start_all_queues() and setting the TSTART bit into the Network
Control Register. Before this patch, when dealing with a single queue, the
driver used to defer the reset of the faulting queue and the write of the
TSTART bit until the next call of macb_start_xmit().
As explained before, this bit is now set by macb_tx_error_task() too. That's
why the faulting queue MUST be reset by setting the TX_USED bit in its first
buffer descriptor before writing the TSTART bit.
Queue 0 always exits and is the lowest priority when other queues are available.
The higher the index of the queue is, the higher its priority is.
When transmitting frames, the TX queue is selected by the skb->queue_mapping
value. So queue discipline can be used to define the queue priority policy.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-12 19:26:44 +07:00
|
|
|
free_netdev(dev);
|
2015-03-07 13:23:32 +07:00
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
return err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-23 00:31:05 +07:00
|
|
|
static int macb_remove(struct platform_device *pdev)
|
2006-11-09 20:51:17 +07:00
|
|
|
{
|
|
|
|
|
struct net_device *dev;
|
|
|
|
|
struct macb *bp;
|
|
|
|
|
|
|
|
|
|
dev = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
if (dev) {
|
|
|
|
|
bp = netdev_priv(dev);
|
2008-04-10 21:30:07 +07:00
|
|
|
if (bp->phy_dev)
|
|
|
|
|
phy_disconnect(bp->phy_dev);
|
2008-10-09 06:29:57 +07:00
|
|
|
mdiobus_unregister(bp->mii_bus);
|
|
|
|
|
kfree(bp->mii_bus->irq);
|
|
|
|
|
mdiobus_free(bp->mii_bus);
|
2006-11-09 20:51:17 +07:00
|
|
|
unregister_netdev(dev);
|
2015-03-07 13:23:31 +07:00
|
|
|
clk_disable_unprepare(bp->tx_clk);
|
2013-03-28 06:07:07 +07:00
|
|
|
clk_disable_unprepare(bp->hclk);
|
|
|
|
|
clk_disable_unprepare(bp->pclk);
|
2014-12-15 21:13:31 +07:00
|
|
|
free_netdev(dev);
|
2006-11-09 20:51:17 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-23 15:36:03 +07:00
|
|
|
static int __maybe_unused macb_suspend(struct device *dev)
|
2008-03-04 19:39:29 +07:00
|
|
|
{
|
2013-12-11 07:07:19 +07:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2008-03-04 19:39:29 +07:00
|
|
|
struct net_device *netdev = platform_get_drvdata(pdev);
|
|
|
|
|
struct macb *bp = netdev_priv(netdev);
|
|
|
|
|
|
2012-07-04 06:14:13 +07:00
|
|
|
netif_carrier_off(netdev);
|
2008-03-04 19:39:29 +07:00
|
|
|
netif_device_detach(netdev);
|
|
|
|
|
|
2015-03-07 13:23:31 +07:00
|
|
|
clk_disable_unprepare(bp->tx_clk);
|
2013-03-28 06:07:07 +07:00
|
|
|
clk_disable_unprepare(bp->hclk);
|
|
|
|
|
clk_disable_unprepare(bp->pclk);
|
2008-03-04 19:39:29 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-23 15:36:03 +07:00
|
|
|
static int __maybe_unused macb_resume(struct device *dev)
|
2008-03-04 19:39:29 +07:00
|
|
|
{
|
2013-12-11 07:07:19 +07:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2008-03-04 19:39:29 +07:00
|
|
|
struct net_device *netdev = platform_get_drvdata(pdev);
|
|
|
|
|
struct macb *bp = netdev_priv(netdev);
|
|
|
|
|
|
2013-03-28 06:07:07 +07:00
|
|
|
clk_prepare_enable(bp->pclk);
|
|
|
|
|
clk_prepare_enable(bp->hclk);
|
2015-03-07 13:23:31 +07:00
|
|
|
clk_prepare_enable(bp->tx_clk);
|
2008-03-04 19:39:29 +07:00
|
|
|
|
|
|
|
|
netif_device_attach(netdev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-12-11 07:07:19 +07:00
|
|
|
static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
|
|
|
|
|
|
2006-11-09 20:51:17 +07:00
|
|
|
static struct platform_driver macb_driver = {
|
2015-01-23 00:31:05 +07:00
|
|
|
.probe = macb_probe,
|
|
|
|
|
.remove = macb_remove,
|
2006-11-09 20:51:17 +07:00
|
|
|
.driver = {
|
|
|
|
|
.name = "macb",
|
2011-11-18 21:29:25 +07:00
|
|
|
.of_match_table = of_match_ptr(macb_dt_ids),
|
2013-12-11 07:07:19 +07:00
|
|
|
.pm = &macb_pm_ops,
|
2006-11-09 20:51:17 +07:00
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
2015-01-23 00:31:05 +07:00
|
|
|
module_platform_driver(macb_driver);
|
2006-11-09 20:51:17 +07:00
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
2011-11-08 17:12:32 +07:00
|
|
|
MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
|
2011-05-18 21:49:24 +07:00
|
|
|
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
|
2008-04-19 03:50:44 +07:00
|
|
|
MODULE_ALIAS("platform:macb");
|