2012-04-24 21:47:39 +07:00
|
|
|
/*
|
|
|
|
* Copyright © 2008-2012 Intel Corporation
|
|
|
|
*
|
|
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
|
|
* to deal in the Software without restriction, including without limitation
|
|
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
|
|
*
|
|
|
|
* The above copyright notice and this permission notice (including the next
|
|
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
|
|
* Software.
|
|
|
|
*
|
|
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
|
|
|
* IN THE SOFTWARE.
|
|
|
|
*
|
|
|
|
* Authors:
|
|
|
|
* Eric Anholt <eric@anholt.net>
|
|
|
|
* Chris Wilson <chris@chris-wilson.co.uk>
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
|
2012-10-03 00:01:07 +07:00
|
|
|
#include <drm/drmP.h>
|
|
|
|
#include <drm/i915_drm.h>
|
2012-04-24 21:47:39 +07:00
|
|
|
#include "i915_drv.h"
|
|
|
|
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
#define KB(x) ((x) * 1024)
|
|
|
|
#define MB(x) (KB(x) * 1024)
|
|
|
|
|
2012-04-24 21:47:39 +07:00
|
|
|
/*
|
|
|
|
* The BIOS typically reserves some of the system's memory for the exclusive
|
|
|
|
* use of the integrated graphics. This memory is no longer available for
|
|
|
|
* use by the OS and so the user finds that his system has less memory
|
|
|
|
* available than he put in. We refer to this memory as stolen.
|
|
|
|
*
|
|
|
|
* The BIOS will allocate its framebuffer from the stolen memory. Our
|
|
|
|
* goal is try to reuse that object for our own fbcon which must always
|
|
|
|
* be available for panics. Anything else we can reuse the stolen memory
|
|
|
|
* for is a boon.
|
|
|
|
*/
|
|
|
|
|
2015-09-15 01:19:57 +07:00
|
|
|
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_mm_node *node, u64 size,
|
|
|
|
unsigned alignment, u64 start, u64 end)
|
2015-07-03 05:25:07 +07:00
|
|
|
{
|
2015-07-03 05:25:09 +07:00
|
|
|
int ret;
|
|
|
|
|
2015-07-03 05:25:07 +07:00
|
|
|
if (!drm_mm_initialized(&dev_priv->mm.stolen))
|
|
|
|
return -ENODEV;
|
|
|
|
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_lock(&dev_priv->mm.stolen_lock);
|
2017-02-03 04:04:38 +07:00
|
|
|
ret = drm_mm_insert_node_in_range(&dev_priv->mm.stolen, node,
|
|
|
|
size, alignment, 0,
|
|
|
|
start, end, DRM_MM_INSERT_BEST);
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_unlock(&dev_priv->mm.stolen_lock);
|
|
|
|
|
|
|
|
return ret;
|
2015-07-03 05:25:07 +07:00
|
|
|
}
|
|
|
|
|
2015-09-15 01:19:57 +07:00
|
|
|
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_mm_node *node, u64 size,
|
|
|
|
unsigned alignment)
|
|
|
|
{
|
|
|
|
return i915_gem_stolen_insert_node_in_range(dev_priv, node, size,
|
2016-12-15 20:23:55 +07:00
|
|
|
alignment, 0, U64_MAX);
|
2015-09-15 01:19:57 +07:00
|
|
|
}
|
|
|
|
|
2015-07-03 05:25:07 +07:00
|
|
|
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
|
|
|
|
struct drm_mm_node *node)
|
|
|
|
{
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_lock(&dev_priv->mm.stolen_lock);
|
2015-07-03 05:25:07 +07:00
|
|
|
drm_mm_remove_node(node);
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_unlock(&dev_priv->mm.stolen_lock);
|
2015-07-03 05:25:07 +07:00
|
|
|
}
|
|
|
|
|
2017-01-27 23:55:30 +07:00
|
|
|
static dma_addr_t i915_stolen_to_dma(struct drm_i915_private *dev_priv)
|
2012-04-24 21:47:39 +07:00
|
|
|
{
|
2016-08-22 17:32:44 +07:00
|
|
|
struct pci_dev *pdev = dev_priv->drm.pdev;
|
2016-03-30 20:57:10 +07:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2013-07-04 18:28:35 +07:00
|
|
|
struct resource *r;
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t base;
|
2012-04-24 21:47:39 +07:00
|
|
|
|
2013-07-04 06:23:33 +07:00
|
|
|
/* Almost universally we can find the Graphics Base of Stolen Memory
|
2016-04-15 16:03:39 +07:00
|
|
|
* at register BSM (0x5c) in the igfx configuration space. On a few
|
|
|
|
* (desktop) machines this is also mirrored in the bridge device at
|
|
|
|
* different locations, or in the MCHBAR.
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
*
|
|
|
|
* On 865 we just check the TOUD register.
|
|
|
|
*
|
|
|
|
* On 830/845/85x the stolen memory base isn't available in any
|
|
|
|
* register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
|
2012-11-15 18:32:18 +07:00
|
|
|
*
|
2012-04-24 21:47:39 +07:00
|
|
|
*/
|
2012-11-15 18:32:18 +07:00
|
|
|
base = 0;
|
2016-11-01 03:37:20 +07:00
|
|
|
if (INTEL_GEN(dev_priv) >= 3) {
|
2016-04-15 16:03:39 +07:00
|
|
|
u32 bsm;
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_read_config_dword(pdev, INTEL_BSM, &bsm);
|
2016-04-15 16:03:39 +07:00
|
|
|
|
2016-04-22 17:29:26 +07:00
|
|
|
base = bsm & INTEL_BSM_MASK;
|
2016-10-13 17:02:58 +07:00
|
|
|
} else if (IS_I865G(dev_priv)) {
|
2016-08-08 17:58:39 +07:00
|
|
|
u32 tseg_size = 0;
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
u16 toud = 0;
|
2016-08-08 17:58:39 +07:00
|
|
|
u8 tmp;
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
2016-08-08 17:58:39 +07:00
|
|
|
I845_ESMRAMC, &tmp);
|
|
|
|
|
|
|
|
if (tmp & TSEG_ENABLE) {
|
|
|
|
switch (tmp & I845_TSEG_SIZE_MASK) {
|
|
|
|
case I845_TSEG_SIZE_512K:
|
|
|
|
tseg_size = KB(512);
|
|
|
|
break;
|
|
|
|
case I845_TSEG_SIZE_1M:
|
|
|
|
tseg_size = MB(1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_word(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I865_TOUD, &toud);
|
|
|
|
|
2016-08-08 17:58:39 +07:00
|
|
|
base = (toud << 16) + tseg_size;
|
2016-11-01 03:37:20 +07:00
|
|
|
} else if (IS_I85X(dev_priv)) {
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
u32 tseg_size = 0;
|
|
|
|
u32 tom;
|
|
|
|
u8 tmp;
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I85X_ESMRAMC, &tmp);
|
|
|
|
|
|
|
|
if (tmp & TSEG_ENABLE)
|
|
|
|
tseg_size = MB(1);
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 1),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I85X_DRB3, &tmp);
|
|
|
|
tom = tmp * MB(32);
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
base = tom - tseg_size - ggtt->stolen_size;
|
2016-11-30 22:43:04 +07:00
|
|
|
} else if (IS_I845G(dev_priv)) {
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
u32 tseg_size = 0;
|
|
|
|
u32 tom;
|
|
|
|
u8 tmp;
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I845_ESMRAMC, &tmp);
|
|
|
|
|
|
|
|
if (tmp & TSEG_ENABLE) {
|
|
|
|
switch (tmp & I845_TSEG_SIZE_MASK) {
|
|
|
|
case I845_TSEG_SIZE_512K:
|
|
|
|
tseg_size = KB(512);
|
|
|
|
break;
|
|
|
|
case I845_TSEG_SIZE_1M:
|
|
|
|
tseg_size = MB(1);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I830_DRB3, &tmp);
|
|
|
|
tom = tmp * MB(32);
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
base = tom - tseg_size - ggtt->stolen_size;
|
2016-10-13 17:02:58 +07:00
|
|
|
} else if (IS_I830(dev_priv)) {
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
u32 tseg_size = 0;
|
|
|
|
u32 tom;
|
|
|
|
u8 tmp;
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I830_ESMRAMC, &tmp);
|
|
|
|
|
|
|
|
if (tmp & TSEG_ENABLE) {
|
|
|
|
if (tmp & I830_TSEG_SIZE_1M)
|
|
|
|
tseg_size = MB(1);
|
|
|
|
else
|
|
|
|
tseg_size = KB(512);
|
|
|
|
}
|
|
|
|
|
2016-08-22 17:32:44 +07:00
|
|
|
pci_bus_read_config_byte(pdev->bus, PCI_DEVFN(0, 0),
|
drm/i915: Determine the stolen memory base address on gen2
There isn't an explicit stolen memory base register on gen2.
Some old comment in the i915 code suggests we should get it via
max_low_pfn_mapped, but that's clearly a bad idea on my MGM.
The e820 map in said machine looks like this:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009f7ff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f800-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000ce000-0x00000000000cffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000001f6effff] usable
[ 0.000000] BIOS-e820: [mem 0x000000001f6f0000-0x000000001f6f7fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x000000001f6f8000-0x000000001f6fffff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x000000001f700000-0x000000001fffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ffb00000-0x00000000ffbfffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fff00000-0x00000000ffffffff] reserved
That makes max_low_pfn_mapped = 1f6f0000, so assuming our stolen memory
would start there would place it on top of some ACPI memory regions.
So not a good idea as already stated.
The 9MB region after the ACPI regions at 0x1f700000 however looks
promising given that the macine reports the stolen memory size to be
8MB. Looking at the PGTBL_CTL register, the GTT entries are at offset
0x1fee00000, and given that the GTT entries occupy 128KB, it looks like
the stolen memory could start at 0x1f700000 and the GTT entries would
occupy the last 128KB of the stolen memory.
After some more digging through chipset documentation, I've determined
the BIOS first allocates space for something called TSEG (something to
do with SMM) from the top of memory, and then it allocates the graphics
stolen memory below that. Accordind to the chipset documentation TSEG
has a fixed size of 1MB on 855. So that explains the top 1MB in the
e820 region. And it also confirms that the GTT entries are in fact at
the end of the the stolen memory region.
Derive the stolen memory base address on gen2 the same as the BIOS does
(TOM-TSEG_SIZE-stolen_size). There are a few differences between the
registers on various gen2 chipsets, so a few different codepaths are
required.
865G is again bit more special since it seems to support enough memory
to hit 4GB address space issues. This means the PCI allocations will
also affect the location of the stolen memory. Fortunately there
appears to be the TOUD register which may give us the correct answer
directly. But the chipset docs are a bit unclear, so I'm not 100%
sure that the graphics stolen memory is always the last thing the
BIOS steals. Someone would need to verify it on a real system.
I tested this on the my 830 and 855 machines, and so far everything
looks peachy.
v2: Rewrite to use the TOM-TSEG_SIZE-stolen_size and TOUD methods
v3: Fix TSEG size for 830
v4: Add missing 'else' (Chris)
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-10-08 16:08:20 +07:00
|
|
|
I830_DRB3, &tmp);
|
|
|
|
tom = tmp * MB(32);
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
base = tom - tseg_size - ggtt->stolen_size;
|
2012-11-15 18:32:18 +07:00
|
|
|
}
|
2012-04-24 21:47:39 +07:00
|
|
|
|
2017-01-30 20:47:21 +07:00
|
|
|
if (base == 0 || add_overflows(base, ggtt->stolen_size))
|
2013-07-04 18:28:35 +07:00
|
|
|
return 0;
|
|
|
|
|
2014-06-06 00:02:59 +07:00
|
|
|
/* make sure we don't clobber the GTT if it's within stolen memory */
|
2016-12-08 03:48:09 +07:00
|
|
|
if (INTEL_GEN(dev_priv) <= 4 &&
|
|
|
|
!IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
|
2014-06-06 00:02:59 +07:00
|
|
|
struct {
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t start, end;
|
2014-06-06 00:02:59 +07:00
|
|
|
} stolen[2] = {
|
2016-03-30 20:57:10 +07:00
|
|
|
{ .start = base, .end = base + ggtt->stolen_size, },
|
|
|
|
{ .start = base, .end = base + ggtt->stolen_size, },
|
2014-06-06 00:02:59 +07:00
|
|
|
};
|
2016-03-30 20:57:10 +07:00
|
|
|
u64 ggtt_start, ggtt_end;
|
2014-06-06 00:02:59 +07:00
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt_start = I915_READ(PGTBL_CTL);
|
2016-10-13 17:03:10 +07:00
|
|
|
if (IS_GEN4(dev_priv))
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) |
|
|
|
|
(ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
|
2014-06-06 00:02:59 +07:00
|
|
|
else
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt_start &= PGTBL_ADDRESS_LO_MASK;
|
|
|
|
ggtt_end = ggtt_start + ggtt_total_entries(ggtt) * 4;
|
2014-06-06 00:02:59 +07:00
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
if (ggtt_start >= stolen[0].start && ggtt_start < stolen[0].end)
|
|
|
|
stolen[0].end = ggtt_start;
|
|
|
|
if (ggtt_end > stolen[1].start && ggtt_end <= stolen[1].end)
|
|
|
|
stolen[1].start = ggtt_end;
|
2014-06-06 00:02:59 +07:00
|
|
|
|
|
|
|
/* pick the larger of the two chunks */
|
|
|
|
if (stolen[0].end - stolen[0].start >
|
|
|
|
stolen[1].end - stolen[1].start) {
|
|
|
|
base = stolen[0].start;
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt->stolen_size = stolen[0].end - stolen[0].start;
|
2014-06-06 00:02:59 +07:00
|
|
|
} else {
|
|
|
|
base = stolen[1].start;
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt->stolen_size = stolen[1].end - stolen[1].start;
|
2014-06-06 00:02:59 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (stolen[0].start != stolen[1].start ||
|
|
|
|
stolen[0].end != stolen[1].end) {
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t end = base + ggtt->stolen_size - 1;
|
2017-01-27 03:19:07 +07:00
|
|
|
|
2014-06-06 00:02:59 +07:00
|
|
|
DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
|
2016-03-30 20:57:10 +07:00
|
|
|
(unsigned long long)ggtt_start,
|
|
|
|
(unsigned long long)ggtt_end - 1);
|
2017-01-27 23:55:30 +07:00
|
|
|
DRM_DEBUG_KMS("Stolen memory adjusted to %pad - %pad\n",
|
2017-01-27 03:19:07 +07:00
|
|
|
&base, &end);
|
2014-06-06 00:02:59 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2013-07-04 18:28:35 +07:00
|
|
|
/* Verify that nothing else uses this physical address. Stolen
|
|
|
|
* memory should be reserved by the BIOS and hidden from the
|
|
|
|
* kernel. So if the region is already marked as busy, something
|
|
|
|
* is seriously wrong.
|
|
|
|
*/
|
2016-11-16 15:55:35 +07:00
|
|
|
r = devm_request_mem_region(dev_priv->drm.dev, base, ggtt->stolen_size,
|
2013-07-04 18:28:35 +07:00
|
|
|
"Graphics Stolen Memory");
|
|
|
|
if (r == NULL) {
|
2014-01-13 17:55:21 +07:00
|
|
|
/*
|
|
|
|
* One more attempt but this time requesting region from
|
|
|
|
* base + 1, as we have seen that this resolves the region
|
|
|
|
* conflict with the PCI Bus.
|
|
|
|
* This is a BIOS w/a: Some BIOS wrap stolen in the root
|
|
|
|
* PCI bus, but have an off-by-one error. Hence retry the
|
|
|
|
* reservation starting from 1 instead of 0.
|
|
|
|
*/
|
2016-11-16 15:55:35 +07:00
|
|
|
r = devm_request_mem_region(dev_priv->drm.dev, base + 1,
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt->stolen_size - 1,
|
2014-01-13 17:55:21 +07:00
|
|
|
"Graphics Stolen Memory");
|
2014-04-11 20:55:17 +07:00
|
|
|
/*
|
|
|
|
* GEN3 firmware likes to smash pci bridges into the stolen
|
|
|
|
* range. Apparently this works.
|
|
|
|
*/
|
2016-10-13 17:03:10 +07:00
|
|
|
if (r == NULL && !IS_GEN3(dev_priv)) {
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t end = base + ggtt->stolen_size;
|
2017-01-27 03:19:07 +07:00
|
|
|
|
2017-01-27 23:55:30 +07:00
|
|
|
DRM_ERROR("conflict detected with stolen region: [%pad - %pad]\n",
|
2017-01-27 03:19:07 +07:00
|
|
|
&base, &end);
|
2014-01-13 17:55:21 +07:00
|
|
|
base = 0;
|
|
|
|
}
|
2013-07-04 18:28:35 +07:00
|
|
|
}
|
|
|
|
|
2012-11-15 18:32:18 +07:00
|
|
|
return base;
|
2012-04-24 21:47:39 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void i915_gem_cleanup_stolen(struct drm_device *dev)
|
|
|
|
{
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-12-18 21:24:37 +07:00
|
|
|
|
2013-07-02 15:48:31 +07:00
|
|
|
if (!drm_mm_initialized(&dev_priv->mm.stolen))
|
|
|
|
return;
|
|
|
|
|
2012-12-18 21:24:37 +07:00
|
|
|
drm_mm_takedown(&dev_priv->mm.stolen);
|
2012-04-24 21:47:39 +07:00
|
|
|
}
|
|
|
|
|
2015-09-17 01:28:50 +07:00
|
|
|
static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv,
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t *base, u32 *size)
|
2015-09-17 01:28:50 +07:00
|
|
|
{
|
2016-03-30 20:57:10 +07:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2015-09-17 01:28:50 +07:00
|
|
|
uint32_t reg_val = I915_READ(IS_GM45(dev_priv) ?
|
|
|
|
CTG_STOLEN_RESERVED :
|
|
|
|
ELK_STOLEN_RESERVED);
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
|
2015-09-17 01:28:50 +07:00
|
|
|
|
|
|
|
*base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16;
|
|
|
|
|
|
|
|
WARN_ON((reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base);
|
|
|
|
|
|
|
|
/* On these platforms, the register doesn't have a size field, so the
|
|
|
|
* size is the distance between the base and the top of the stolen
|
|
|
|
* memory. We also have the genuine case where base is zero and there's
|
|
|
|
* nothing reserved. */
|
|
|
|
if (*base == 0)
|
|
|
|
*size = 0;
|
|
|
|
else
|
|
|
|
*size = stolen_top - *base;
|
|
|
|
}
|
|
|
|
|
2015-08-11 00:57:32 +07:00
|
|
|
static void gen6_get_stolen_reserved(struct drm_i915_private *dev_priv,
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t *base, u32 *size)
|
2015-08-11 00:57:32 +07:00
|
|
|
{
|
|
|
|
uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
|
|
|
|
|
|
|
|
*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
|
|
|
|
|
|
|
|
switch (reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK) {
|
|
|
|
case GEN6_STOLEN_RESERVED_1M:
|
|
|
|
*size = 1024 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN6_STOLEN_RESERVED_512K:
|
|
|
|
*size = 512 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN6_STOLEN_RESERVED_256K:
|
|
|
|
*size = 256 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN6_STOLEN_RESERVED_128K:
|
|
|
|
*size = 128 * 1024;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*size = 1024 * 1024;
|
|
|
|
MISSING_CASE(reg_val & GEN6_STOLEN_RESERVED_SIZE_MASK);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen7_get_stolen_reserved(struct drm_i915_private *dev_priv,
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t *base, u32 *size)
|
2015-08-11 00:57:32 +07:00
|
|
|
{
|
|
|
|
uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
|
|
|
|
|
|
|
|
*base = reg_val & GEN7_STOLEN_RESERVED_ADDR_MASK;
|
|
|
|
|
|
|
|
switch (reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK) {
|
|
|
|
case GEN7_STOLEN_RESERVED_1M:
|
|
|
|
*size = 1024 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN7_STOLEN_RESERVED_256K:
|
|
|
|
*size = 256 * 1024;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*size = 1024 * 1024;
|
|
|
|
MISSING_CASE(reg_val & GEN7_STOLEN_RESERVED_SIZE_MASK);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-19 04:36:27 +07:00
|
|
|
static void chv_get_stolen_reserved(struct drm_i915_private *dev_priv,
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t *base, u32 *size)
|
2015-08-11 00:57:32 +07:00
|
|
|
{
|
|
|
|
uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
|
|
|
|
|
|
|
|
*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
|
|
|
|
|
|
|
|
switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
|
|
|
|
case GEN8_STOLEN_RESERVED_1M:
|
|
|
|
*size = 1024 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN8_STOLEN_RESERVED_2M:
|
|
|
|
*size = 2 * 1024 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN8_STOLEN_RESERVED_4M:
|
|
|
|
*size = 4 * 1024 * 1024;
|
|
|
|
break;
|
|
|
|
case GEN8_STOLEN_RESERVED_8M:
|
|
|
|
*size = 8 * 1024 * 1024;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*size = 8 * 1024 * 1024;
|
|
|
|
MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t *base, u32 *size)
|
2015-08-11 00:57:32 +07:00
|
|
|
{
|
2016-03-30 20:57:10 +07:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2015-08-11 00:57:32 +07:00
|
|
|
uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t stolen_top;
|
2015-08-11 00:57:32 +07:00
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
|
2015-08-11 00:57:32 +07:00
|
|
|
|
|
|
|
*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
|
|
|
|
|
|
|
|
/* On these platforms, the register doesn't have a size field, so the
|
|
|
|
* size is the distance between the base and the top of the stolen
|
|
|
|
* memory. We also have the genuine case where base is zero and there's
|
|
|
|
* nothing reserved. */
|
|
|
|
if (*base == 0)
|
|
|
|
*size = 0;
|
|
|
|
else
|
|
|
|
*size = stolen_top - *base;
|
|
|
|
}
|
|
|
|
|
2016-11-16 15:55:35 +07:00
|
|
|
int i915_gem_init_stolen(struct drm_i915_private *dev_priv)
|
2012-04-24 21:47:39 +07:00
|
|
|
{
|
2016-03-30 20:57:10 +07:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t reserved_base, stolen_top;
|
2017-01-06 22:20:11 +07:00
|
|
|
u32 reserved_total, reserved_size;
|
|
|
|
u32 stolen_usable_start;
|
2012-04-24 21:47:39 +07:00
|
|
|
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_init(&dev_priv->mm.stolen_lock);
|
|
|
|
|
2016-11-09 17:39:05 +07:00
|
|
|
if (intel_vgpu_active(dev_priv)) {
|
|
|
|
DRM_INFO("iGVT-g active, disabling use of stolen memory\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-05-25 19:16:12 +07:00
|
|
|
if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) {
|
2014-03-18 19:50:50 +07:00
|
|
|
DRM_INFO("DMAR active, disabling use of stolen memory\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
if (ggtt->stolen_size == 0)
|
2013-09-05 19:40:25 +07:00
|
|
|
return 0;
|
|
|
|
|
2017-01-27 23:55:30 +07:00
|
|
|
dev_priv->mm.stolen_base = i915_stolen_to_dma(dev_priv);
|
2012-11-15 18:32:18 +07:00
|
|
|
if (dev_priv->mm.stolen_base == 0)
|
|
|
|
return 0;
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
|
2017-01-06 22:20:10 +07:00
|
|
|
reserved_base = 0;
|
|
|
|
reserved_size = 0;
|
2015-08-11 00:57:32 +07:00
|
|
|
|
|
|
|
switch (INTEL_INFO(dev_priv)->gen) {
|
|
|
|
case 2:
|
|
|
|
case 3:
|
2015-09-17 01:28:50 +07:00
|
|
|
break;
|
2015-08-11 00:57:32 +07:00
|
|
|
case 4:
|
2016-10-13 17:03:06 +07:00
|
|
|
if (IS_G4X(dev_priv))
|
2017-01-06 22:20:10 +07:00
|
|
|
g4x_get_stolen_reserved(dev_priv,
|
|
|
|
&reserved_base, &reserved_size);
|
2015-09-17 01:28:50 +07:00
|
|
|
break;
|
2015-08-11 00:57:32 +07:00
|
|
|
case 5:
|
|
|
|
/* Assume the gen6 maximum for the older platforms. */
|
|
|
|
reserved_size = 1024 * 1024;
|
|
|
|
reserved_base = stolen_top - reserved_size;
|
|
|
|
break;
|
|
|
|
case 6:
|
2017-01-06 22:20:10 +07:00
|
|
|
gen6_get_stolen_reserved(dev_priv,
|
|
|
|
&reserved_base, &reserved_size);
|
2015-08-11 00:57:32 +07:00
|
|
|
break;
|
|
|
|
case 7:
|
2017-01-06 22:20:10 +07:00
|
|
|
gen7_get_stolen_reserved(dev_priv,
|
|
|
|
&reserved_base, &reserved_size);
|
2015-08-11 00:57:32 +07:00
|
|
|
break;
|
|
|
|
default:
|
2016-12-20 02:05:47 +07:00
|
|
|
if (IS_LP(dev_priv))
|
2017-01-06 22:20:10 +07:00
|
|
|
chv_get_stolen_reserved(dev_priv,
|
|
|
|
&reserved_base, &reserved_size);
|
2015-08-11 00:57:32 +07:00
|
|
|
else
|
2017-01-06 22:20:10 +07:00
|
|
|
bdw_get_stolen_reserved(dev_priv,
|
|
|
|
&reserved_base, &reserved_size);
|
2015-08-11 00:57:32 +07:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* It is possible for the reserved base to be zero, but the register
|
|
|
|
* field for size doesn't have a zero option. */
|
|
|
|
if (reserved_base == 0) {
|
|
|
|
reserved_size = 0;
|
|
|
|
reserved_base = stolen_top;
|
2014-09-11 18:28:08 +07:00
|
|
|
}
|
2013-05-09 00:45:13 +07:00
|
|
|
|
2015-08-11 00:57:32 +07:00
|
|
|
if (reserved_base < dev_priv->mm.stolen_base ||
|
|
|
|
reserved_base + reserved_size > stolen_top) {
|
2017-01-27 23:55:30 +07:00
|
|
|
dma_addr_t reserved_top = reserved_base + reserved_size;
|
|
|
|
DRM_DEBUG_KMS("Stolen reserved area [%pad - %pad] outside stolen memory [%pad - %pad]\n",
|
2017-01-06 22:20:10 +07:00
|
|
|
&reserved_base, &reserved_top,
|
|
|
|
&dev_priv->mm.stolen_base, &stolen_top);
|
2013-07-09 19:44:27 +07:00
|
|
|
return 0;
|
2015-08-11 00:57:32 +07:00
|
|
|
}
|
|
|
|
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt->stolen_reserved_base = reserved_base;
|
|
|
|
ggtt->stolen_reserved_size = reserved_size;
|
2016-02-06 01:43:29 +07:00
|
|
|
|
2015-08-11 00:57:32 +07:00
|
|
|
/* It is possible for the reserved area to end before the end of stolen
|
|
|
|
* memory, so just consider the start. */
|
|
|
|
reserved_total = stolen_top - reserved_base;
|
|
|
|
|
2017-01-06 22:20:11 +07:00
|
|
|
DRM_DEBUG_KMS("Memory reserved for graphics device: %uK, usable: %uK\n",
|
2016-03-30 20:57:10 +07:00
|
|
|
ggtt->stolen_size >> 10,
|
|
|
|
(ggtt->stolen_size - reserved_total) >> 10);
|
2013-07-09 19:44:27 +07:00
|
|
|
|
2016-12-15 20:23:55 +07:00
|
|
|
stolen_usable_start = 0;
|
|
|
|
/* WaSkipStolenMemoryFirstPage:bdw+ */
|
|
|
|
if (INTEL_GEN(dev_priv) >= 8)
|
|
|
|
stolen_usable_start = 4096;
|
2015-09-15 01:19:57 +07:00
|
|
|
|
2017-01-06 22:20:11 +07:00
|
|
|
ggtt->stolen_usable_size =
|
|
|
|
ggtt->stolen_size - reserved_total - stolen_usable_start;
|
2016-12-15 20:23:55 +07:00
|
|
|
|
|
|
|
/* Basic memrange allocator for stolen space. */
|
|
|
|
drm_mm_init(&dev_priv->mm.stolen, stolen_usable_start,
|
|
|
|
ggtt->stolen_usable_size);
|
2012-04-24 21:47:39 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2012-11-15 18:32:26 +07:00
|
|
|
|
|
|
|
static struct sg_table *
|
|
|
|
i915_pages_create_for_stolen(struct drm_device *dev,
|
|
|
|
u32 offset, u32 size)
|
|
|
|
{
|
2016-03-30 20:57:10 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
2012-11-15 18:32:26 +07:00
|
|
|
struct sg_table *st;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
|
2017-01-06 22:20:12 +07:00
|
|
|
GEM_BUG_ON(range_overflows(offset, size, dev_priv->ggtt.stolen_size));
|
2012-11-15 18:32:26 +07:00
|
|
|
|
|
|
|
/* We hide that we have no struct page backing our stolen object
|
|
|
|
* by wrapping the contiguous physical allocation with a fake
|
|
|
|
* dma mapping in a single scatterlist.
|
|
|
|
*/
|
|
|
|
|
|
|
|
st = kmalloc(sizeof(*st), GFP_KERNEL);
|
|
|
|
if (st == NULL)
|
2016-11-19 00:02:16 +07:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2012-11-15 18:32:26 +07:00
|
|
|
|
|
|
|
if (sg_alloc_table(st, 1, GFP_KERNEL)) {
|
|
|
|
kfree(st);
|
2016-11-19 00:02:16 +07:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2012-11-15 18:32:26 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
sg = st->sgl;
|
2014-01-13 17:54:45 +07:00
|
|
|
sg->offset = 0;
|
2013-03-26 20:14:19 +07:00
|
|
|
sg->length = size;
|
2012-11-15 18:32:26 +07:00
|
|
|
|
|
|
|
sg_dma_address(sg) = (dma_addr_t)dev_priv->mm.stolen_base + offset;
|
|
|
|
sg_dma_len(sg) = size;
|
|
|
|
|
|
|
|
return st;
|
|
|
|
}
|
|
|
|
|
2016-10-28 19:58:36 +07:00
|
|
|
static struct sg_table *
|
|
|
|
i915_gem_object_get_pages_stolen(struct drm_i915_gem_object *obj)
|
2012-11-15 18:32:26 +07:00
|
|
|
{
|
2016-10-28 19:58:36 +07:00
|
|
|
return i915_pages_create_for_stolen(obj->base.dev,
|
|
|
|
obj->stolen->start,
|
|
|
|
obj->stolen->size);
|
2012-11-15 18:32:26 +07:00
|
|
|
}
|
|
|
|
|
2016-10-28 19:58:36 +07:00
|
|
|
static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj,
|
|
|
|
struct sg_table *pages)
|
2012-11-15 18:32:26 +07:00
|
|
|
{
|
2016-11-17 22:58:46 +07:00
|
|
|
/* Should only be called from i915_gem_object_release_stolen() */
|
2016-10-28 19:58:36 +07:00
|
|
|
sg_free_table(pages);
|
|
|
|
kfree(pages);
|
2012-11-15 18:32:26 +07:00
|
|
|
}
|
|
|
|
|
2014-06-06 16:22:54 +07:00
|
|
|
static void
|
|
|
|
i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
|
|
|
|
{
|
2016-07-04 17:34:36 +07:00
|
|
|
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
|
2016-11-17 22:58:46 +07:00
|
|
|
struct drm_mm_node *stolen = fetch_and_zero(&obj->stolen);
|
|
|
|
|
|
|
|
GEM_BUG_ON(!stolen);
|
2015-07-03 05:25:07 +07:00
|
|
|
|
2016-10-28 19:58:35 +07:00
|
|
|
__i915_gem_object_unpin_pages(obj);
|
|
|
|
|
2016-11-17 22:58:46 +07:00
|
|
|
i915_gem_stolen_remove_node(dev_priv, stolen);
|
|
|
|
kfree(stolen);
|
2014-06-06 16:22:54 +07:00
|
|
|
}
|
2016-11-17 22:58:46 +07:00
|
|
|
|
2012-11-15 18:32:26 +07:00
|
|
|
static const struct drm_i915_gem_object_ops i915_gem_object_stolen_ops = {
|
|
|
|
.get_pages = i915_gem_object_get_pages_stolen,
|
|
|
|
.put_pages = i915_gem_object_put_pages_stolen,
|
2014-06-06 16:22:54 +07:00
|
|
|
.release = i915_gem_object_release_stolen,
|
2012-11-15 18:32:26 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static struct drm_i915_gem_object *
|
2016-12-01 21:16:36 +07:00
|
|
|
_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
|
2012-11-15 18:32:26 +07:00
|
|
|
struct drm_mm_node *stolen)
|
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
|
2016-12-01 21:16:36 +07:00
|
|
|
obj = i915_gem_object_alloc(dev_priv);
|
2012-11-15 18:32:26 +07:00
|
|
|
if (obj == NULL)
|
|
|
|
return NULL;
|
|
|
|
|
2016-12-01 21:16:36 +07:00
|
|
|
drm_gem_private_object_init(&dev_priv->drm, &obj->base, stolen->size);
|
2012-11-15 18:32:26 +07:00
|
|
|
i915_gem_object_init(obj, &i915_gem_object_stolen_ops);
|
|
|
|
|
|
|
|
obj->stolen = stolen;
|
2013-08-08 20:41:06 +07:00
|
|
|
obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
|
2016-12-01 21:16:36 +07:00
|
|
|
obj->cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
|
2012-11-15 18:32:26 +07:00
|
|
|
|
2016-10-28 19:58:36 +07:00
|
|
|
if (i915_gem_object_pin_pages(obj))
|
|
|
|
goto cleanup;
|
|
|
|
|
2012-11-15 18:32:26 +07:00
|
|
|
return obj;
|
|
|
|
|
|
|
|
cleanup:
|
2012-11-15 18:32:30 +07:00
|
|
|
i915_gem_object_free(obj);
|
2012-11-15 18:32:26 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct drm_i915_gem_object *
|
2016-12-01 21:16:36 +07:00
|
|
|
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size)
|
2012-11-15 18:32:26 +07:00
|
|
|
{
|
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct drm_mm_node *stolen;
|
2013-07-27 21:21:27 +07:00
|
|
|
int ret;
|
2012-11-15 18:32:26 +07:00
|
|
|
|
2013-07-02 15:48:31 +07:00
|
|
|
if (!drm_mm_initialized(&dev_priv->mm.stolen))
|
2012-11-15 18:32:26 +07:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (size == 0)
|
|
|
|
return NULL;
|
|
|
|
|
2013-07-27 21:21:27 +07:00
|
|
|
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
|
|
|
|
if (!stolen)
|
2012-11-15 18:32:26 +07:00
|
|
|
return NULL;
|
|
|
|
|
2015-07-03 05:25:07 +07:00
|
|
|
ret = i915_gem_stolen_insert_node(dev_priv, stolen, size, 4096);
|
2013-07-27 21:21:27 +07:00
|
|
|
if (ret) {
|
|
|
|
kfree(stolen);
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-12-01 21:16:36 +07:00
|
|
|
obj = _i915_gem_object_create_stolen(dev_priv, stolen);
|
2012-11-15 18:32:26 +07:00
|
|
|
if (obj)
|
|
|
|
return obj;
|
|
|
|
|
2015-07-03 05:25:07 +07:00
|
|
|
i915_gem_stolen_remove_node(dev_priv, stolen);
|
2013-07-27 21:21:27 +07:00
|
|
|
kfree(stolen);
|
2012-11-15 18:32:26 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2013-02-20 04:31:37 +07:00
|
|
|
struct drm_i915_gem_object *
|
2016-12-01 21:16:36 +07:00
|
|
|
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
|
2013-02-20 04:31:37 +07:00
|
|
|
u32 stolen_offset,
|
|
|
|
u32 gtt_offset,
|
|
|
|
u32 size)
|
|
|
|
{
|
2016-03-30 20:57:10 +07:00
|
|
|
struct i915_ggtt *ggtt = &dev_priv->ggtt;
|
2013-02-20 04:31:37 +07:00
|
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
struct drm_mm_node *stolen;
|
2013-07-18 02:19:03 +07:00
|
|
|
struct i915_vma *vma;
|
2013-07-06 04:41:02 +07:00
|
|
|
int ret;
|
2013-02-20 04:31:37 +07:00
|
|
|
|
2013-07-02 15:48:31 +07:00
|
|
|
if (!drm_mm_initialized(&dev_priv->mm.stolen))
|
2013-02-20 04:31:37 +07:00
|
|
|
return NULL;
|
|
|
|
|
2016-12-01 21:16:36 +07:00
|
|
|
lockdep_assert_held(&dev_priv->drm.struct_mutex);
|
2016-02-11 17:27:29 +07:00
|
|
|
|
2013-02-20 04:31:37 +07:00
|
|
|
DRM_DEBUG_KMS("creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x\n",
|
|
|
|
stolen_offset, gtt_offset, size);
|
|
|
|
|
|
|
|
/* KISS and expect everything to be page-aligned */
|
2017-01-10 21:47:34 +07:00
|
|
|
if (WARN_ON(size == 0) ||
|
|
|
|
WARN_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE)) ||
|
|
|
|
WARN_ON(!IS_ALIGNED(stolen_offset, I915_GTT_MIN_ALIGNMENT)))
|
2013-02-20 04:31:37 +07:00
|
|
|
return NULL;
|
|
|
|
|
2013-07-06 04:41:02 +07:00
|
|
|
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
|
|
|
|
if (!stolen)
|
|
|
|
return NULL;
|
|
|
|
|
2013-07-06 04:41:03 +07:00
|
|
|
stolen->start = stolen_offset;
|
|
|
|
stolen->size = size;
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_lock(&dev_priv->mm.stolen_lock);
|
2013-07-06 04:41:03 +07:00
|
|
|
ret = drm_mm_reserve_node(&dev_priv->mm.stolen, stolen);
|
2015-07-03 05:25:09 +07:00
|
|
|
mutex_unlock(&dev_priv->mm.stolen_lock);
|
2013-07-06 04:41:02 +07:00
|
|
|
if (ret) {
|
2013-02-20 04:31:37 +07:00
|
|
|
DRM_DEBUG_KMS("failed to allocate stolen space\n");
|
2013-07-06 04:41:02 +07:00
|
|
|
kfree(stolen);
|
2013-02-20 04:31:37 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-12-01 21:16:36 +07:00
|
|
|
obj = _i915_gem_object_create_stolen(dev_priv, stolen);
|
2013-02-20 04:31:37 +07:00
|
|
|
if (obj == NULL) {
|
|
|
|
DRM_DEBUG_KMS("failed to allocate stolen object\n");
|
2015-07-03 05:25:07 +07:00
|
|
|
i915_gem_stolen_remove_node(dev_priv, stolen);
|
2013-07-27 21:21:27 +07:00
|
|
|
kfree(stolen);
|
2013-02-20 04:31:37 +07:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2013-05-09 00:45:14 +07:00
|
|
|
/* Some objects just need physical mem from stolen space */
|
2013-07-04 18:06:28 +07:00
|
|
|
if (gtt_offset == I915_GTT_OFFSET_NONE)
|
2013-05-09 00:45:14 +07:00
|
|
|
return obj;
|
|
|
|
|
2016-10-28 19:58:36 +07:00
|
|
|
ret = i915_gem_object_pin_pages(obj);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
2017-01-16 22:21:28 +07:00
|
|
|
vma = i915_vma_instance(obj, &ggtt->base, NULL);
|
2013-07-19 12:45:46 +07:00
|
|
|
if (IS_ERR(vma)) {
|
|
|
|
ret = PTR_ERR(vma);
|
2016-10-28 19:58:36 +07:00
|
|
|
goto err_pages;
|
2013-07-18 02:19:03 +07:00
|
|
|
}
|
|
|
|
|
2013-02-20 04:31:37 +07:00
|
|
|
/* To simplify the initialisation sequence between KMS and GTT,
|
|
|
|
* we allow construction of the stolen object prior to
|
|
|
|
* setting up the GTT space. The actual reservation will occur
|
|
|
|
* later.
|
|
|
|
*/
|
2017-01-11 18:23:11 +07:00
|
|
|
ret = i915_gem_gtt_reserve(&ggtt->base, &vma->node,
|
|
|
|
size, gtt_offset, obj->cache_level,
|
|
|
|
0);
|
2016-08-04 13:52:23 +07:00
|
|
|
if (ret) {
|
|
|
|
DRM_DEBUG_KMS("failed to allocate stolen GTT space\n");
|
2016-10-28 19:58:36 +07:00
|
|
|
goto err_pages;
|
2015-09-24 17:57:45 +07:00
|
|
|
}
|
2013-02-20 04:31:37 +07:00
|
|
|
|
2017-01-20 02:26:58 +07:00
|
|
|
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
|
|
|
|
|
2016-10-28 19:58:35 +07:00
|
|
|
vma->pages = obj->mm.pages;
|
2016-08-04 22:32:32 +07:00
|
|
|
vma->flags |= I915_VMA_GLOBAL_BIND;
|
2016-08-04 13:52:23 +07:00
|
|
|
__i915_vma_set_map_and_fenceable(vma);
|
2016-08-04 13:52:46 +07:00
|
|
|
list_move_tail(&vma->vm_link, &ggtt->base.inactive_list);
|
2016-11-02 17:16:04 +07:00
|
|
|
list_move_tail(&obj->global_link, &dev_priv->mm.bound_list);
|
2016-08-04 13:52:26 +07:00
|
|
|
obj->bind_count++;
|
2016-08-04 13:52:23 +07:00
|
|
|
|
2013-02-20 04:31:37 +07:00
|
|
|
return obj;
|
2013-07-06 04:41:02 +07:00
|
|
|
|
2016-10-28 19:58:36 +07:00
|
|
|
err_pages:
|
|
|
|
i915_gem_object_unpin_pages(obj);
|
2015-09-24 17:57:45 +07:00
|
|
|
err:
|
2016-07-20 19:31:53 +07:00
|
|
|
i915_gem_object_put(obj);
|
2013-07-06 04:41:02 +07:00
|
|
|
return NULL;
|
2013-02-20 04:31:37 +07:00
|
|
|
}
|