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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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137 lines
8.0 KiB
C
137 lines
8.0 KiB
C
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/******************************************************************************
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*
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* Name: actbl1.h - ACPI 1.0 tables
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*
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*****************************************************************************/
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/*
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* Copyright (C) 2000 - 2005, R. Byron Moore
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*/
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#ifndef __ACTBL1_H__
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#define __ACTBL1_H__
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#pragma pack(1)
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/*
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* ACPI 1.0 Root System Description Table (RSDT)
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*/
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struct rsdt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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u32 table_offset_entry [1]; /* Array of pointers to other */
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/* ACPI tables */
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};
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/*
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* ACPI 1.0 Firmware ACPI Control Structure (FACS)
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*/
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struct facs_descriptor_rev1
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{
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char signature[4]; /* ACPI Signature */
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u32 length; /* Length of structure, in bytes */
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u32 hardware_signature; /* Hardware configuration signature */
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u32 firmware_waking_vector; /* ACPI OS waking vector */
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u32 global_lock; /* Global Lock */
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u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */
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u32 reserved1 : 31; /* Must be 0 */
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u8 resverved3 [40]; /* Reserved - must be zero */
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};
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/*
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* ACPI 1.0 Fixed ACPI Description Table (FADT)
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*/
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struct fadt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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u32 firmware_ctrl; /* Physical address of FACS */
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u32 dsdt; /* Physical address of DSDT */
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u8 model; /* System Interrupt Model */
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u8 reserved1; /* Reserved */
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u16 sci_int; /* System vector of SCI interrupt */
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u32 smi_cmd; /* Port address of SMI command port */
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u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
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u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
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u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
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u8 reserved2; /* Reserved - must be zero */
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u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
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u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
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u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
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u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
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u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
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u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
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u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
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u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
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u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
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u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
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u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
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u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
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u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
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u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
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u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
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u8 reserved3; /* Reserved */
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u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
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u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
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u16 flush_size; /* Size of area read to flush caches */
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u16 flush_stride; /* Stride used in flushing caches */
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u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
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u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
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u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
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u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
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u8 century; /* Index to century in RTC CMOS RAM */
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u8 reserved4; /* Reserved */
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u8 reserved4a; /* Reserved */
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u8 reserved4b; /* Reserved */
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u32 wb_invd : 1; /* The wbinvd instruction works properly */
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u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
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u32 proc_c1 : 1; /* All processors support C1 state */
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u32 plvl2_up : 1; /* C2 state works on MP system */
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u32 pwr_button : 1; /* Power button is handled as a generic feature */
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u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
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u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
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u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
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u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
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u32 reserved5 : 23; /* Reserved - must be zero */
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};
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#pragma pack()
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#endif /* __ACTBL1_H__ */
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