2015-10-29 15:36:23 +07:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2015 Free Electrons
|
|
|
|
* Copyright (C) 2015 NextThing Co
|
|
|
|
*
|
|
|
|
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License as
|
|
|
|
* published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <drm/drmP.h>
|
|
|
|
#include <drm/drm_atomic_helper.h>
|
2018-09-07 11:19:45 +07:00
|
|
|
#include <drm/drm_connector.h>
|
2015-10-29 15:36:23 +07:00
|
|
|
#include <drm/drm_crtc.h>
|
2017-10-10 10:19:58 +07:00
|
|
|
#include <drm/drm_encoder.h>
|
2015-10-29 15:36:23 +07:00
|
|
|
#include <drm/drm_modes.h>
|
2017-03-30 01:55:46 +07:00
|
|
|
#include <drm/drm_of.h>
|
2018-07-18 21:23:57 +07:00
|
|
|
#include <drm/drm_panel.h>
|
2019-01-18 04:03:34 +07:00
|
|
|
#include <drm/drm_probe_helper.h>
|
2015-10-29 15:36:23 +07:00
|
|
|
|
2017-10-10 10:19:58 +07:00
|
|
|
#include <uapi/drm/drm_mode.h>
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
#include <linux/component.h>
|
|
|
|
#include <linux/ioport.h>
|
|
|
|
#include <linux/of_address.h>
|
2016-10-20 10:43:39 +07:00
|
|
|
#include <linux/of_device.h>
|
2015-10-29 15:36:23 +07:00
|
|
|
#include <linux/of_irq.h>
|
|
|
|
#include <linux/regmap.h>
|
|
|
|
#include <linux/reset.h>
|
|
|
|
|
|
|
|
#include "sun4i_crtc.h"
|
|
|
|
#include "sun4i_dotclock.h"
|
|
|
|
#include "sun4i_drv.h"
|
2017-12-21 18:02:33 +07:00
|
|
|
#include "sun4i_lvds.h"
|
2015-10-29 15:37:32 +07:00
|
|
|
#include "sun4i_rgb.h"
|
2015-10-29 15:36:23 +07:00
|
|
|
#include "sun4i_tcon.h"
|
2018-04-04 16:57:12 +07:00
|
|
|
#include "sun6i_mipi_dsi.h"
|
2018-07-11 03:35:05 +07:00
|
|
|
#include "sun8i_tcon_top.h"
|
2017-05-17 21:47:17 +07:00
|
|
|
#include "sunxi_engine.h"
|
2015-10-29 15:36:23 +07:00
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct drm_connector_list_iter iter;
|
|
|
|
|
|
|
|
drm_connector_list_iter_begin(encoder->dev, &iter);
|
|
|
|
drm_for_each_connector_iter(connector, &iter)
|
|
|
|
if (connector->encoder == encoder) {
|
|
|
|
drm_connector_list_iter_end(&iter);
|
|
|
|
return connector;
|
|
|
|
}
|
|
|
|
drm_connector_list_iter_end(&iter);
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector;
|
|
|
|
struct drm_display_info *info;
|
|
|
|
|
|
|
|
connector = sun4i_tcon_get_connector(encoder);
|
|
|
|
if (!connector)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
info = &connector->display_info;
|
|
|
|
if (info->num_bus_formats != 1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (info->bus_formats[0]) {
|
|
|
|
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
|
|
|
|
return 18;
|
|
|
|
|
|
|
|
case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
|
|
|
|
case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
|
|
|
|
return 24;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
|
|
|
|
bool enabled)
|
2015-10-29 15:36:23 +07:00
|
|
|
{
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
struct clk *clk;
|
2015-10-29 15:36:23 +07:00
|
|
|
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
switch (channel) {
|
|
|
|
case 0:
|
2018-02-15 03:09:01 +07:00
|
|
|
WARN_ON(!tcon->quirks->has_channel_0);
|
2015-10-29 15:36:23 +07:00
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
SUN4I_TCON0_CTL_TCON_ENABLE,
|
|
|
|
enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
|
|
|
|
clk = tcon->dclk;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
WARN_ON(!tcon->quirks->has_channel_1);
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
|
|
|
|
SUN4I_TCON1_CTL_TCON_ENABLE,
|
|
|
|
enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
|
|
|
|
clk = tcon->sclk1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_WARN("Unknown channel... doing nothing\n");
|
2016-01-07 18:32:07 +07:00
|
|
|
return;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
2016-01-07 18:32:07 +07:00
|
|
|
|
2018-03-02 04:34:32 +07:00
|
|
|
if (enabled) {
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
clk_prepare_enable(clk);
|
2018-03-10 18:05:11 +07:00
|
|
|
clk_rate_exclusive_get(clk);
|
2018-03-02 04:34:32 +07:00
|
|
|
} else {
|
|
|
|
clk_rate_exclusive_put(clk);
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
clk_disable_unprepare(clk);
|
2018-03-02 04:34:32 +07:00
|
|
|
}
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder,
|
|
|
|
bool enabled)
|
|
|
|
{
|
|
|
|
if (enabled) {
|
|
|
|
u8 val;
|
|
|
|
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
|
|
|
|
SUN4I_TCON0_LVDS_IF_EN,
|
|
|
|
SUN4I_TCON0_LVDS_IF_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* As their name suggest, these values only apply to the A31
|
|
|
|
* and later SoCs. We'll have to rework this when merging
|
|
|
|
* support for the older SoCs.
|
|
|
|
*/
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_C(2) |
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_V(3) |
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_PD(2) |
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_LDO);
|
|
|
|
udelay(2);
|
|
|
|
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_MB,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_MB);
|
|
|
|
udelay(2);
|
|
|
|
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
|
|
|
|
|
|
|
|
if (sun4i_tcon_get_pixel_depth(encoder) == 18)
|
|
|
|
val = 7;
|
|
|
|
else
|
|
|
|
val = 0xf;
|
|
|
|
|
|
|
|
regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
|
|
|
|
SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
|
|
|
|
} else {
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
|
|
|
|
SUN4I_TCON0_LVDS_IF_EN, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder,
|
|
|
|
bool enabled)
|
2015-10-29 15:36:23 +07:00
|
|
|
{
|
2017-12-21 18:02:33 +07:00
|
|
|
bool is_lvds = false;
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
int channel;
|
|
|
|
|
|
|
|
switch (encoder->encoder_type) {
|
2017-12-21 18:02:33 +07:00
|
|
|
case DRM_MODE_ENCODER_LVDS:
|
|
|
|
is_lvds = true;
|
|
|
|
/* Fallthrough */
|
2018-04-04 16:57:12 +07:00
|
|
|
case DRM_MODE_ENCODER_DSI:
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
case DRM_MODE_ENCODER_NONE:
|
|
|
|
channel = 0;
|
|
|
|
break;
|
|
|
|
case DRM_MODE_ENCODER_TMDS:
|
|
|
|
case DRM_MODE_ENCODER_TVDAC:
|
|
|
|
channel = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
|
2016-01-07 18:32:07 +07:00
|
|
|
return;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
2016-01-07 18:32:07 +07:00
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
if (is_lvds && !enabled)
|
|
|
|
sun4i_tcon_lvds_set_status(tcon, encoder, false);
|
|
|
|
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
|
|
|
|
SUN4I_TCON_GCTL_TCON_ENABLE,
|
|
|
|
enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
|
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
if (is_lvds && enabled)
|
|
|
|
sun4i_tcon_lvds_set_status(tcon, encoder, true);
|
|
|
|
|
drm/sun4i: tcon: Don't rely on encoders to enable the TCON
So far, we've required all the TCON-connected encoders to call the TCON
enable and disable functions.
This was made this way because in the RGB/LVDS case, the TCON is the CRTC
and the encoder. However, in all the other cases (HDMI, TV, DSI, etc.), we
have another encoder down the road that needs to be programmed.
We also needed to know which channel the encoder is connected to, which is
encoder-specific.
The CRTC's enable and disable callbacks can work just fine for our use
case, and we can get the channel to use just by looking at the type of
encoder, since that is fixed. Implement those callbacks, which will
remove some of the encoder boilerplate.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/90b4396e19b3eca61b2ebfdae0672074b88ad74d.1508231063.git-series.maxime.ripard@free-electrons.com
2017-10-17 16:06:12 +07:00
|
|
|
sun4i_tcon_channel_set_status(tcon, channel, enabled);
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
|
|
|
|
{
|
|
|
|
u32 mask, val = 0;
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
|
|
|
|
|
|
|
|
mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
|
2018-04-04 16:57:09 +07:00
|
|
|
SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
|
|
|
|
SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
|
2015-10-29 15:36:23 +07:00
|
|
|
|
|
|
|
if (enable)
|
|
|
|
val = mask;
|
|
|
|
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
|
|
|
|
|
2017-10-10 10:19:59 +07:00
|
|
|
/*
|
|
|
|
* This function is a helper for TCON output muxing. The TCON output
|
|
|
|
* muxing control register in earlier SoCs (without the TCON TOP block)
|
|
|
|
* are located in TCON0. This helper returns a pointer to TCON0's
|
|
|
|
* sun4i_tcon structure, or NULL if not found.
|
|
|
|
*/
|
|
|
|
static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
|
|
|
|
{
|
|
|
|
struct sun4i_drv *drv = drm->dev_private;
|
|
|
|
struct sun4i_tcon *tcon;
|
|
|
|
|
|
|
|
list_for_each_entry(tcon, &drv->tcon_list, list)
|
|
|
|
if (tcon->id == 0)
|
|
|
|
return tcon;
|
|
|
|
|
|
|
|
dev_warn(drm->dev,
|
|
|
|
"TCON0 not found, display output muxing may not work\n");
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2019-04-16 21:58:55 +07:00
|
|
|
static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
|
|
|
|
const struct drm_encoder *encoder)
|
2017-05-27 23:09:27 +07:00
|
|
|
{
|
2017-10-10 10:19:58 +07:00
|
|
|
int ret = -ENOTSUPP;
|
2017-05-27 23:09:27 +07:00
|
|
|
|
2017-10-10 10:19:58 +07:00
|
|
|
if (tcon->quirks->set_mux)
|
|
|
|
ret = tcon->quirks->set_mux(tcon, encoder);
|
2017-05-27 23:09:28 +07:00
|
|
|
|
2017-10-10 10:19:58 +07:00
|
|
|
DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
|
|
|
|
encoder->name, encoder->crtc->name, ret);
|
2017-05-27 23:09:27 +07:00
|
|
|
}
|
|
|
|
|
2017-10-17 16:06:11 +07:00
|
|
|
static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
|
2015-10-29 15:36:23 +07:00
|
|
|
int channel)
|
|
|
|
{
|
|
|
|
int delay = mode->vtotal - mode->vdisplay;
|
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
|
|
delay /= 2;
|
|
|
|
|
|
|
|
if (channel == 1)
|
|
|
|
delay -= 2;
|
|
|
|
|
|
|
|
delay = min(delay, 30);
|
|
|
|
|
|
|
|
DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
|
|
|
|
|
|
|
|
return delay;
|
|
|
|
}
|
|
|
|
|
2017-10-17 16:06:14 +07:00
|
|
|
static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
/* Configure the dot clock */
|
|
|
|
clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
|
|
|
|
|
|
|
|
/* Set the resolution */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
|
|
|
|
SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
|
|
|
|
SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
|
|
|
|
}
|
|
|
|
|
2018-09-07 11:19:45 +07:00
|
|
|
static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
u32 bus_format = 0;
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
/* XXX Would this ever happen? */
|
|
|
|
if (!connector)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: Undocumented bits
|
|
|
|
*
|
|
|
|
* The whole dithering process and these parameters are not
|
|
|
|
* explained in the vendor documents or BSP kernel code.
|
|
|
|
*/
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
|
|
|
|
|
|
|
|
/* Do dithering if panel only supports 6 bits per color */
|
|
|
|
if (connector->display_info.bpc == 6)
|
|
|
|
val |= SUN4I_TCON0_FRM_CTL_EN;
|
|
|
|
|
|
|
|
if (connector->display_info.num_bus_formats == 1)
|
|
|
|
bus_format = connector->display_info.bus_formats[0];
|
|
|
|
|
|
|
|
/* Check the connection format */
|
|
|
|
switch (bus_format) {
|
|
|
|
case MEDIA_BUS_FMT_RGB565_1X16:
|
|
|
|
/* R and B components are only 5 bits deep */
|
|
|
|
val |= SUN4I_TCON0_FRM_CTL_MODE_R;
|
|
|
|
val |= SUN4I_TCON0_FRM_CTL_MODE_B;
|
|
|
|
case MEDIA_BUS_FMT_RGB666_1X18:
|
|
|
|
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
|
|
|
|
/* Fall through: enable dithering */
|
|
|
|
val |= SUN4I_TCON0_FRM_CTL_EN;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write dithering settings */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
|
|
|
|
}
|
|
|
|
|
2018-04-04 16:57:12 +07:00
|
|
|
static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
|
2018-09-07 11:19:43 +07:00
|
|
|
const struct drm_encoder *encoder,
|
2018-04-04 16:57:12 +07:00
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
2018-09-07 11:19:43 +07:00
|
|
|
/* TODO support normal CPU interface modes */
|
|
|
|
struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
|
|
|
|
struct mipi_dsi_device *device = dsi->device;
|
2018-04-04 16:57:12 +07:00
|
|
|
u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
|
|
|
|
u8 lanes = device->lanes;
|
|
|
|
u32 block_space, start_delay;
|
|
|
|
u32 tcon_div;
|
|
|
|
|
2019-02-11 21:41:22 +07:00
|
|
|
tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
|
|
|
|
tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
|
2018-04-04 16:57:12 +07:00
|
|
|
|
|
|
|
sun4i_tcon0_mode_set_common(tcon, mode);
|
|
|
|
|
2018-09-07 11:19:45 +07:00
|
|
|
/* Set dithering if needed */
|
|
|
|
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
|
|
|
|
|
2018-04-04 16:57:12 +07:00
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
|
|
|
|
SUN4I_TCON0_CTL_IF_MASK,
|
|
|
|
SUN4I_TCON0_CTL_IF_8080);
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
|
|
|
|
SUN4I_TCON_ECC_FIFO_EN);
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
|
|
|
|
SUN4I_TCON0_CPU_IF_MODE_DSI |
|
|
|
|
SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
|
|
|
|
SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
|
|
|
|
SUN4I_TCON0_CPU_IF_TRI_EN);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This looks suspicious, but it works...
|
|
|
|
*
|
|
|
|
* The datasheet says that this should be set higher than 20 *
|
|
|
|
* pixel cycle, but it's not clear what a pixel cycle is.
|
|
|
|
*/
|
|
|
|
regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
|
|
|
|
tcon_div &= GENMASK(6, 0);
|
|
|
|
block_space = mode->htotal * bpp / (tcon_div * lanes);
|
|
|
|
block_space -= mode->hdisplay + 40;
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
|
|
|
|
SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
|
|
|
|
SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
|
|
|
|
SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
|
|
|
|
|
|
|
|
start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
|
|
|
|
start_delay = start_delay * mode->crtc_htotal * 149;
|
|
|
|
start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
|
|
|
|
SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
|
|
|
|
SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Allwinner BSP has a comment that the period should be
|
|
|
|
* the display clock * 15, but uses an hardcoded 3000...
|
|
|
|
*/
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
|
|
|
|
SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
|
|
|
|
SUN4I_TCON_SAFE_PERIOD_MODE(3));
|
|
|
|
|
|
|
|
/* Enable the output on the pins */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
|
|
|
|
0xe0000000);
|
|
|
|
}
|
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder,
|
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
unsigned int bp;
|
|
|
|
u8 clk_delay;
|
|
|
|
u32 reg, val = 0;
|
|
|
|
|
2018-02-15 03:09:01 +07:00
|
|
|
WARN_ON(!tcon->quirks->has_channel_0);
|
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
tcon->dclk_min_div = 7;
|
|
|
|
tcon->dclk_max_div = 7;
|
|
|
|
sun4i_tcon0_mode_set_common(tcon, mode);
|
|
|
|
|
2018-09-07 11:19:45 +07:00
|
|
|
/* Set dithering if needed */
|
|
|
|
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
|
|
|
|
|
2017-12-21 18:02:33 +07:00
|
|
|
/* Adjust clock delay */
|
|
|
|
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
|
|
|
|
SUN4I_TCON0_CTL_CLK_DELAY_MASK,
|
|
|
|
SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called a backporch in the register documentation,
|
|
|
|
* but it really is the back porch + hsync
|
|
|
|
*/
|
|
|
|
bp = mode->crtc_htotal - mode->crtc_hsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
|
|
|
|
mode->crtc_htotal, bp);
|
|
|
|
|
|
|
|
/* Set horizontal display timings */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
|
|
|
|
SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
|
|
|
|
SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called a backporch in the register documentation,
|
|
|
|
* but it really is the back porch + hsync
|
|
|
|
*/
|
|
|
|
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
|
|
|
|
mode->crtc_vtotal, bp);
|
|
|
|
|
|
|
|
/* Set vertical display timings */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
|
|
|
|
SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
|
|
|
|
SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
|
|
|
|
|
|
|
|
reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
|
|
|
|
SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
|
|
|
|
SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
|
|
|
|
if (sun4i_tcon_get_pixel_depth(encoder) == 24)
|
|
|
|
reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
|
|
|
|
else
|
|
|
|
reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
|
|
|
|
|
|
|
|
/* Setup the polarity of the various signals */
|
|
|
|
if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
|
|
|
|
val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
|
|
|
|
|
|
|
|
if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
|
|
|
|
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
|
|
|
|
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
|
|
|
|
|
|
|
|
/* Map output pins to channel 0 */
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_MASK,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_TCON0);
|
2018-02-22 23:12:17 +07:00
|
|
|
|
|
|
|
/* Enable the output on the pins */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
|
2017-12-21 18:02:33 +07:00
|
|
|
}
|
|
|
|
|
2017-10-17 16:06:14 +07:00
|
|
|
static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
|
2018-11-08 01:18:36 +07:00
|
|
|
const struct drm_encoder *encoder,
|
2017-10-17 16:06:14 +07:00
|
|
|
const struct drm_display_mode *mode)
|
2015-10-29 15:36:23 +07:00
|
|
|
{
|
2018-11-08 01:18:37 +07:00
|
|
|
struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
|
|
|
|
struct drm_display_info display_info = connector->display_info;
|
2015-10-29 15:36:23 +07:00
|
|
|
unsigned int bp, hsync, vsync;
|
|
|
|
u8 clk_delay;
|
|
|
|
u32 val = 0;
|
|
|
|
|
2018-02-15 03:09:01 +07:00
|
|
|
WARN_ON(!tcon->quirks->has_channel_0);
|
|
|
|
|
2017-12-21 18:02:32 +07:00
|
|
|
tcon->dclk_min_div = 6;
|
|
|
|
tcon->dclk_max_div = 127;
|
2017-10-17 16:06:14 +07:00
|
|
|
sun4i_tcon0_mode_set_common(tcon, mode);
|
2017-04-25 22:25:04 +07:00
|
|
|
|
2018-09-07 11:19:45 +07:00
|
|
|
/* Set dithering if needed */
|
2018-11-08 01:18:37 +07:00
|
|
|
sun4i_tcon0_mode_set_dithering(tcon, connector);
|
2018-09-07 11:19:45 +07:00
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
/* Adjust clock delay */
|
|
|
|
clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
|
|
|
|
SUN4I_TCON0_CTL_CLK_DELAY_MASK,
|
|
|
|
SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called a backporch in the register documentation,
|
2017-03-09 17:05:25 +07:00
|
|
|
* but it really is the back porch + hsync
|
2015-10-29 15:36:23 +07:00
|
|
|
*/
|
|
|
|
bp = mode->crtc_htotal - mode->crtc_hsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
|
|
|
|
mode->crtc_htotal, bp);
|
|
|
|
|
|
|
|
/* Set horizontal display timings */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
|
|
|
|
SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
|
|
|
|
SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is called a backporch in the register documentation,
|
2017-03-09 17:05:25 +07:00
|
|
|
* but it really is the back porch + hsync
|
2015-10-29 15:36:23 +07:00
|
|
|
*/
|
|
|
|
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
|
|
|
|
mode->crtc_vtotal, bp);
|
|
|
|
|
|
|
|
/* Set vertical display timings */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
|
2017-05-27 23:09:30 +07:00
|
|
|
SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
|
2015-10-29 15:36:23 +07:00
|
|
|
SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
|
|
|
|
|
|
|
|
/* Set Hsync and Vsync length */
|
|
|
|
hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
|
|
|
|
vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
|
|
|
|
SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
|
|
|
|
SUN4I_TCON0_BASIC3_H_SYNC(hsync));
|
|
|
|
|
|
|
|
/* Setup the polarity of the various signals */
|
2018-02-16 00:54:48 +07:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_PHSYNC)
|
2015-10-29 15:36:23 +07:00
|
|
|
val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
|
|
|
|
|
2018-02-16 00:54:48 +07:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_PVSYNC)
|
2015-10-29 15:36:23 +07:00
|
|
|
val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
|
|
|
|
|
2018-11-08 01:18:38 +07:00
|
|
|
if (display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
|
|
|
|
val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
|
|
|
|
|
2018-07-18 21:23:57 +07:00
|
|
|
/*
|
|
|
|
* On A20 and similar SoCs, the only way to achieve Positive Edge
|
|
|
|
* (Rising Edge), is setting dclk clock phase to 2/3(240°).
|
|
|
|
* By default TCON works in Negative Edge(Falling Edge),
|
|
|
|
* this is why phase is set to 0 in that case.
|
|
|
|
* Unfortunately there's no way to logically invert dclk through
|
|
|
|
* IO_POL register.
|
|
|
|
* The only acceptable way to work, triple checked with scope,
|
|
|
|
* is using clock phase set to 0° for Negative Edge and set to 240°
|
|
|
|
* for Positive Edge.
|
|
|
|
* On A33 and similar SoCs there would be a 90° phase option,
|
|
|
|
* but it divides also dclk by 2.
|
|
|
|
* Following code is a way to avoid quirks all around TCON
|
|
|
|
* and DOTCLOCK drivers.
|
|
|
|
*/
|
2018-09-22 19:02:42 +07:00
|
|
|
if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
|
2018-11-08 01:18:37 +07:00
|
|
|
clk_set_phase(tcon->dclk, 240);
|
2018-07-18 21:23:57 +07:00
|
|
|
|
2018-09-22 19:02:42 +07:00
|
|
|
if (display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
|
2018-11-08 01:18:37 +07:00
|
|
|
clk_set_phase(tcon->dclk, 0);
|
2018-07-18 21:23:57 +07:00
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
|
2018-11-08 01:18:38 +07:00
|
|
|
SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
|
|
|
|
SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
|
|
|
|
SUN4I_TCON0_IO_POL_DE_NEGATIVE,
|
2015-10-29 15:36:23 +07:00
|
|
|
val);
|
|
|
|
|
|
|
|
/* Map output pins to channel 0 */
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_MASK,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_TCON0);
|
|
|
|
|
|
|
|
/* Enable the output on the pins */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
|
|
|
|
}
|
|
|
|
|
2017-10-17 16:06:13 +07:00
|
|
|
static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_display_mode *mode)
|
2015-10-29 15:36:23 +07:00
|
|
|
{
|
2017-05-27 23:09:31 +07:00
|
|
|
unsigned int bp, hsync, vsync, vtotal;
|
2015-10-29 15:36:23 +07:00
|
|
|
u8 clk_delay;
|
|
|
|
u32 val;
|
|
|
|
|
2016-10-20 10:43:39 +07:00
|
|
|
WARN_ON(!tcon->quirks->has_channel_1);
|
2016-01-07 18:32:07 +07:00
|
|
|
|
2017-04-25 22:25:04 +07:00
|
|
|
/* Configure the dot clock */
|
|
|
|
clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
/* Adjust clock delay */
|
|
|
|
clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
|
|
|
|
SUN4I_TCON1_CTL_CLK_DELAY_MASK,
|
|
|
|
SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
|
|
|
|
|
|
|
|
/* Set interlaced mode */
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
|
|
val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
|
|
|
|
else
|
|
|
|
val = 0;
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
|
|
|
|
SUN4I_TCON1_CTL_INTERLACE_ENABLE,
|
|
|
|
val);
|
|
|
|
|
|
|
|
/* Set the input resolution */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
|
|
|
|
SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
|
|
|
|
SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
|
|
|
|
|
|
|
|
/* Set the upscaling resolution */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
|
|
|
|
SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
|
|
|
|
SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
|
|
|
|
|
|
|
|
/* Set the output resolution */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
|
|
|
|
SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
|
|
|
|
SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
|
|
|
|
|
|
|
|
/* Set horizontal display timings */
|
2017-05-27 23:09:29 +07:00
|
|
|
bp = mode->crtc_htotal - mode->crtc_hsync_start;
|
2015-10-29 15:36:23 +07:00
|
|
|
DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
|
|
|
|
mode->htotal, bp);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
|
|
|
|
SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
|
|
|
|
SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
|
|
|
|
|
2017-05-27 23:09:29 +07:00
|
|
|
bp = mode->crtc_vtotal - mode->crtc_vsync_start;
|
2015-10-29 15:36:23 +07:00
|
|
|
DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
|
2017-05-27 23:09:31 +07:00
|
|
|
mode->crtc_vtotal, bp);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The vertical resolution needs to be doubled in all
|
|
|
|
* cases. We could use crtc_vtotal and always multiply by two,
|
|
|
|
* but that leads to a rounding error in interlace when vtotal
|
|
|
|
* is odd.
|
|
|
|
*
|
|
|
|
* This happens with TV's PAL for example, where vtotal will
|
|
|
|
* be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
|
|
|
|
* 624, which apparently confuses the hardware.
|
|
|
|
*
|
|
|
|
* To work around this, we will always use vtotal, and
|
|
|
|
* multiply by two only if we're not in interlace.
|
|
|
|
*/
|
|
|
|
vtotal = mode->vtotal;
|
|
|
|
if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
|
|
|
|
vtotal = vtotal * 2;
|
|
|
|
|
|
|
|
/* Set vertical display timings */
|
2015-10-29 15:36:23 +07:00
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
|
2017-05-27 23:09:31 +07:00
|
|
|
SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
|
2015-10-29 15:36:23 +07:00
|
|
|
SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
|
|
|
|
|
|
|
|
/* Set Hsync and Vsync length */
|
|
|
|
hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
|
|
|
|
vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
|
|
|
|
DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
|
|
|
|
SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
|
|
|
|
SUN4I_TCON1_BASIC5_H_SYNC(hsync));
|
|
|
|
|
|
|
|
/* Map output pins to channel 1 */
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_MASK,
|
|
|
|
SUN4I_TCON_GCTL_IOMAP_TCON1);
|
|
|
|
}
|
2017-10-17 16:06:13 +07:00
|
|
|
|
|
|
|
void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder,
|
|
|
|
const struct drm_display_mode *mode)
|
|
|
|
{
|
|
|
|
switch (encoder->encoder_type) {
|
2018-04-04 16:57:12 +07:00
|
|
|
case DRM_MODE_ENCODER_DSI:
|
2018-09-07 11:19:43 +07:00
|
|
|
/* DSI is tied to special case of CPU interface */
|
|
|
|
sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
|
2018-04-04 16:57:12 +07:00
|
|
|
break;
|
2017-12-21 18:02:33 +07:00
|
|
|
case DRM_MODE_ENCODER_LVDS:
|
|
|
|
sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
|
|
|
|
break;
|
2017-10-17 16:06:13 +07:00
|
|
|
case DRM_MODE_ENCODER_NONE:
|
2018-11-08 01:18:36 +07:00
|
|
|
sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
|
2017-10-17 16:06:13 +07:00
|
|
|
sun4i_tcon_set_mux(tcon, 0, encoder);
|
|
|
|
break;
|
|
|
|
case DRM_MODE_ENCODER_TVDAC:
|
|
|
|
case DRM_MODE_ENCODER_TMDS:
|
|
|
|
sun4i_tcon1_mode_set(tcon, mode);
|
|
|
|
sun4i_tcon_set_mux(tcon, 1, encoder);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(sun4i_tcon_mode_set);
|
2015-10-29 15:36:23 +07:00
|
|
|
|
|
|
|
static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
|
|
|
|
struct sun4i_crtc *scrtc)
|
|
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
if (scrtc->event) {
|
|
|
|
drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
|
|
|
|
drm_crtc_vblank_put(&scrtc->crtc);
|
|
|
|
scrtc->event = NULL;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t sun4i_tcon_handler(int irq, void *private)
|
|
|
|
{
|
|
|
|
struct sun4i_tcon *tcon = private;
|
|
|
|
struct drm_device *drm = tcon->drm;
|
drm/sun4i: Initialize crtc from tcon bind function
The tcon provides part of the functionality of the crtc, and also
provides the device node for the output port of the crtc. To be able
to use drm_of_find_possible_crtcs(), all crtc must be initialized before
any downstream encoders. The other part of the crtc is the display
backend.
The Rockchip DRM driver does this by first binding all vops, which is
their crtc, and this step also creates the crtc objects. Then all
remaining hardware components are bound. With the Allwinner display
pipeline, we have multiple components comprising the crtc, and varying
depths of the display pipeline. Since components are added with a depth
first search of the of_graph, we can initialize the crtc object within
the tcon bind function. Since the backend precedes the tcon, and the
backends cannot be muxed or switched around, we can be sure that the
associated backend is already initialized.
This patch also moves the crtc pointer from the main drm_device data to
the tcon device data. Besides the crtc callbacks, the crtc structure is
only used within the tcon driver to signal vblank events from its
interrupt handler.
As the crtc and layer bits are now called from the tcon bits, we must
move them from the sun4i-drm module to the sun4i-tcon module to avoid
circular dependencies between the two modules. This is because sun4i-drm
also calls into sun4i-tcon.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-23 15:05:37 +07:00
|
|
|
struct sun4i_crtc *scrtc = tcon->crtc;
|
2018-01-22 16:25:20 +07:00
|
|
|
struct sunxi_engine *engine = scrtc->engine;
|
2015-10-29 15:36:23 +07:00
|
|
|
unsigned int status;
|
|
|
|
|
|
|
|
regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
|
|
|
|
|
|
|
|
if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
|
2018-04-04 16:57:09 +07:00
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(1) |
|
|
|
|
SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
|
2015-10-29 15:36:23 +07:00
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
|
|
drm_crtc_handle_vblank(&scrtc->crtc);
|
|
|
|
sun4i_tcon_finish_page_flip(drm, scrtc);
|
|
|
|
|
|
|
|
/* Acknowledge the interrupt */
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
|
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(0) |
|
2018-04-04 16:57:09 +07:00
|
|
|
SUN4I_TCON_GINT0_VBLANK_INT(1) |
|
|
|
|
SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
|
2015-10-29 15:36:23 +07:00
|
|
|
0);
|
|
|
|
|
2018-01-22 16:25:20 +07:00
|
|
|
if (engine->ops->vblank_quirk)
|
|
|
|
engine->ops->vblank_quirk(engine);
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_clocks(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
tcon->clk = devm_clk_get(dev, "ahb");
|
|
|
|
if (IS_ERR(tcon->clk)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON bus clock\n");
|
|
|
|
return PTR_ERR(tcon->clk);
|
|
|
|
}
|
|
|
|
clk_prepare_enable(tcon->clk);
|
|
|
|
|
2018-02-15 03:09:01 +07:00
|
|
|
if (tcon->quirks->has_channel_0) {
|
|
|
|
tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
|
|
|
|
if (IS_ERR(tcon->sclk0)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
|
|
|
|
return PTR_ERR(tcon->sclk0);
|
|
|
|
}
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
2019-01-31 20:25:50 +07:00
|
|
|
clk_prepare_enable(tcon->sclk0);
|
2015-10-29 15:36:23 +07:00
|
|
|
|
2016-10-20 10:43:39 +07:00
|
|
|
if (tcon->quirks->has_channel_1) {
|
2016-01-07 18:32:07 +07:00
|
|
|
tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
|
|
|
|
if (IS_ERR(tcon->sclk1)) {
|
|
|
|
dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
|
|
|
|
return PTR_ERR(tcon->sclk1);
|
|
|
|
}
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
2017-03-09 17:05:24 +07:00
|
|
|
return 0;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
|
|
|
|
{
|
2019-01-31 20:25:50 +07:00
|
|
|
clk_disable_unprepare(tcon->sclk0);
|
2015-10-29 15:36:23 +07:00
|
|
|
clk_disable_unprepare(tcon->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_irq(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
int irq, ret;
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
|
|
|
|
return irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
|
|
|
|
dev_name(dev), tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't request the IRQ\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct regmap_config sun4i_tcon_regmap_config = {
|
|
|
|
.reg_bits = 32,
|
|
|
|
.val_bits = 32,
|
|
|
|
.reg_stride = 4,
|
|
|
|
.max_register = 0x800,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int sun4i_tcon_init_regmap(struct device *dev,
|
|
|
|
struct sun4i_tcon *tcon)
|
|
|
|
{
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct resource *res;
|
|
|
|
void __iomem *regs;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
regs = devm_ioremap_resource(dev, res);
|
2016-08-26 21:25:25 +07:00
|
|
|
if (IS_ERR(regs))
|
2015-10-29 15:36:23 +07:00
|
|
|
return PTR_ERR(regs);
|
|
|
|
|
|
|
|
tcon->regs = devm_regmap_init_mmio(dev, regs,
|
|
|
|
&sun4i_tcon_regmap_config);
|
|
|
|
if (IS_ERR(tcon->regs)) {
|
|
|
|
dev_err(dev, "Couldn't create the TCON regmap\n");
|
|
|
|
return PTR_ERR(tcon->regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Make sure the TCON is disabled and all IRQs are off */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
|
|
|
|
|
|
|
|
/* Disable IO lines and set them to tristate */
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
|
|
|
|
regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-21 15:38:54 +07:00
|
|
|
/*
|
|
|
|
* On SoCs with the old display pipeline design (Display Engine 1.0),
|
|
|
|
* the TCON is always tied to just one backend. Hence we can traverse
|
|
|
|
* the of_graph upwards to find the backend our tcon is connected to,
|
|
|
|
* and take its ID as our own.
|
|
|
|
*
|
|
|
|
* We can either identify backends from their compatible strings, which
|
|
|
|
* means maintaining a large list of them. Or, since the backend is
|
|
|
|
* registered and binded before the TCON, we can just go through the
|
|
|
|
* list of registered backends and compare the device node.
|
2017-05-17 21:47:17 +07:00
|
|
|
*
|
|
|
|
* As the structures now store engines instead of backends, here this
|
|
|
|
* function in fact searches the corresponding engine, and the ID is
|
|
|
|
* requested via the get_id function of the engine.
|
2017-04-21 15:38:54 +07:00
|
|
|
*/
|
drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID
The device tree binding for sun4i-drm says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.
We should be able to get the TCON's ID directly from any of the remote
endpoints from its input port. With the ID, we can then go through the
list of registered engines and find a matching one by ID.
However the A31 device tree is incorrect. We assumed that there were no
cross pipeline connections between the backends and TCONs. As a result,
in all the endpoints between the backends and TCONs of the second
display pipeline, the endpoint IDs were incorrectly set to 0, when in
fact they should've been set to 1.
To maintain compatibility with this incorrect device tree, we first
check if the TCON's input port has 1 or many endpoints. If there are
more than 1, then it is likely a fixed version, and we can proceed
with the new method. If there is only 1 endpoint, then it is possibly
an incorrect version, or it could be the SoC only has one pipeline.
In either case we fall back to using the old method of traversing
the input connections to find a matching engine, and then get its
ID.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908075016.18657-5-wens@csie.org
2017-09-08 14:50:12 +07:00
|
|
|
static struct sunxi_engine *
|
|
|
|
sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
|
2018-06-25 19:02:50 +07:00
|
|
|
struct device_node *node,
|
|
|
|
u32 port_id)
|
2017-04-21 15:38:54 +07:00
|
|
|
{
|
|
|
|
struct device_node *port, *ep, *remote;
|
2017-09-08 14:50:13 +07:00
|
|
|
struct sunxi_engine *engine = ERR_PTR(-EINVAL);
|
2018-06-25 19:02:50 +07:00
|
|
|
u32 reg = 0;
|
2017-04-21 15:38:54 +07:00
|
|
|
|
2018-06-25 19:02:50 +07:00
|
|
|
port = of_graph_get_port_by_id(node, port_id);
|
2017-04-21 15:38:54 +07:00
|
|
|
if (!port)
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
2017-09-08 14:50:11 +07:00
|
|
|
/*
|
|
|
|
* This only works if there is only one path from the TCON
|
|
|
|
* to any display engine. Otherwise the probe order of the
|
|
|
|
* TCONs and display engines is not guaranteed. They may
|
|
|
|
* either bind to the wrong one, or worse, bind to the same
|
|
|
|
* one if additional checks are not done.
|
|
|
|
*
|
|
|
|
* Bail out if there are multiple input connections.
|
|
|
|
*/
|
2017-09-08 14:50:13 +07:00
|
|
|
if (of_get_available_child_count(port) != 1)
|
|
|
|
goto out_put_port;
|
|
|
|
|
|
|
|
/* Get the first connection without specifying an ID */
|
|
|
|
ep = of_get_next_available_child(port, NULL);
|
|
|
|
if (!ep)
|
|
|
|
goto out_put_port;
|
|
|
|
|
|
|
|
remote = of_graph_get_remote_port_parent(ep);
|
|
|
|
if (!remote)
|
|
|
|
goto out_put_ep;
|
|
|
|
|
|
|
|
/* does this node match any registered engines? */
|
|
|
|
list_for_each_entry(engine, &drv->engine_list, list)
|
|
|
|
if (remote == engine->node)
|
|
|
|
goto out_put_remote;
|
|
|
|
|
2018-06-25 19:02:50 +07:00
|
|
|
/*
|
|
|
|
* According to device tree binding input ports have even id
|
|
|
|
* number and output ports have odd id. Since component with
|
|
|
|
* more than one input and one output (TCON TOP) exits, correct
|
|
|
|
* remote input id has to be calculated by subtracting 1 from
|
|
|
|
* remote output id. If this for some reason can't be done, 0
|
|
|
|
* is used as input port id.
|
|
|
|
*/
|
2018-07-11 03:34:58 +07:00
|
|
|
of_node_put(port);
|
2018-06-25 19:02:50 +07:00
|
|
|
port = of_graph_get_remote_port(ep);
|
|
|
|
if (!of_property_read_u32(port, "reg", ®) && reg > 0)
|
|
|
|
reg -= 1;
|
|
|
|
|
2017-09-08 14:50:13 +07:00
|
|
|
/* keep looking through upstream ports */
|
2018-06-25 19:02:50 +07:00
|
|
|
engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
|
2017-09-08 14:50:13 +07:00
|
|
|
|
|
|
|
out_put_remote:
|
|
|
|
of_node_put(remote);
|
|
|
|
out_put_ep:
|
|
|
|
of_node_put(ep);
|
|
|
|
out_put_port:
|
|
|
|
of_node_put(port);
|
|
|
|
|
|
|
|
return engine;
|
2017-04-21 15:38:54 +07:00
|
|
|
}
|
|
|
|
|
drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID
The device tree binding for sun4i-drm says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.
We should be able to get the TCON's ID directly from any of the remote
endpoints from its input port. With the ID, we can then go through the
list of registered engines and find a matching one by ID.
However the A31 device tree is incorrect. We assumed that there were no
cross pipeline connections between the backends and TCONs. As a result,
in all the endpoints between the backends and TCONs of the second
display pipeline, the endpoint IDs were incorrectly set to 0, when in
fact they should've been set to 1.
To maintain compatibility with this incorrect device tree, we first
check if the TCON's input port has 1 or many endpoints. If there are
more than 1, then it is likely a fixed version, and we can proceed
with the new method. If there is only 1 endpoint, then it is possibly
an incorrect version, or it could be the SoC only has one pipeline.
In either case we fall back to using the old method of traversing
the input connections to find a matching engine, and then get its
ID.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908075016.18657-5-wens@csie.org
2017-09-08 14:50:12 +07:00
|
|
|
/*
|
|
|
|
* The device tree binding says that the remote endpoint ID of any
|
|
|
|
* connection between components, up to and including the TCON, of
|
|
|
|
* the display pipeline should be equal to the actual ID of the local
|
|
|
|
* component. Thus we can look at any one of the input connections of
|
|
|
|
* the TCONs, and use that connection's remote endpoint ID as our own.
|
|
|
|
*
|
|
|
|
* Since the user of this function already finds the input port,
|
|
|
|
* the port is passed in directly without further checks.
|
|
|
|
*/
|
|
|
|
static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
|
|
|
|
{
|
|
|
|
struct device_node *ep;
|
|
|
|
int ret = -EINVAL;
|
|
|
|
|
|
|
|
/* try finding an upstream endpoint */
|
|
|
|
for_each_available_child_of_node(port, ep) {
|
|
|
|
struct device_node *remote;
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
remote = of_graph_get_remote_endpoint(ep);
|
|
|
|
if (!remote)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(remote, "reg", ®);
|
|
|
|
if (ret)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
ret = reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Once we know the TCON's id, we can look through the list of
|
|
|
|
* engines to find a matching one. We assume all engines have
|
|
|
|
* been probed and added to the list.
|
|
|
|
*/
|
|
|
|
static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
|
|
|
|
int id)
|
|
|
|
{
|
|
|
|
struct sunxi_engine *engine;
|
|
|
|
|
|
|
|
list_for_each_entry(engine, &drv->engine_list, list)
|
|
|
|
if (engine->id == id)
|
|
|
|
return engine;
|
|
|
|
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
2018-07-11 03:35:05 +07:00
|
|
|
static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
|
|
|
|
{
|
|
|
|
struct device_node *remote;
|
|
|
|
bool ret = false;
|
|
|
|
|
|
|
|
remote = of_graph_get_remote_node(node, 0, -1);
|
|
|
|
if (remote) {
|
2018-09-11 18:33:25 +07:00
|
|
|
ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
|
|
|
|
of_match_node(sun8i_tcon_top_of_table, remote));
|
2018-07-11 03:35:05 +07:00
|
|
|
of_node_put(remote);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_get_index(struct sun4i_drv *drv)
|
|
|
|
{
|
|
|
|
struct list_head *pos;
|
|
|
|
int size = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Because TCON is added to the list at the end of the probe
|
|
|
|
* (after this function is called), index of the current TCON
|
|
|
|
* will be same as current TCON list size.
|
|
|
|
*/
|
|
|
|
list_for_each(pos, &drv->tcon_list)
|
|
|
|
++size;
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID
The device tree binding for sun4i-drm says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.
We should be able to get the TCON's ID directly from any of the remote
endpoints from its input port. With the ID, we can then go through the
list of registered engines and find a matching one by ID.
However the A31 device tree is incorrect. We assumed that there were no
cross pipeline connections between the backends and TCONs. As a result,
in all the endpoints between the backends and TCONs of the second
display pipeline, the endpoint IDs were incorrectly set to 0, when in
fact they should've been set to 1.
To maintain compatibility with this incorrect device tree, we first
check if the TCON's input port has 1 or many endpoints. If there are
more than 1, then it is likely a fixed version, and we can proceed
with the new method. If there is only 1 endpoint, then it is possibly
an incorrect version, or it could be the SoC only has one pipeline.
In either case we fall back to using the old method of traversing
the input connections to find a matching engine, and then get its
ID.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908075016.18657-5-wens@csie.org
2017-09-08 14:50:12 +07:00
|
|
|
/*
|
|
|
|
* On SoCs with the old display pipeline design (Display Engine 1.0),
|
|
|
|
* we assumed the TCON was always tied to just one backend. However
|
|
|
|
* this proved not to be the case. On the A31, the TCON can select
|
|
|
|
* either backend as its source. On the A20 (and likely on the A10),
|
|
|
|
* the backend can choose which TCON to output to.
|
|
|
|
*
|
|
|
|
* The device tree binding says that the remote endpoint ID of any
|
|
|
|
* connection between components, up to and including the TCON, of
|
|
|
|
* the display pipeline should be equal to the actual ID of the local
|
|
|
|
* component. Thus we should be able to look at any one of the input
|
|
|
|
* connections of the TCONs, and use that connection's remote endpoint
|
|
|
|
* ID as our own.
|
|
|
|
*
|
|
|
|
* However the connections between the backend and TCON were assumed
|
|
|
|
* to be always singular, and their endpoit IDs were all incorrectly
|
|
|
|
* set to 0. This means for these old device trees, we cannot just look
|
|
|
|
* up the remote endpoint ID of a TCON input endpoint. TCON1 would be
|
|
|
|
* incorrectly identified as TCON0.
|
|
|
|
*
|
|
|
|
* This function first checks if the TCON node has 2 input endpoints.
|
|
|
|
* If so, then the device tree is a corrected version, and it will use
|
|
|
|
* sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
|
|
|
|
* to fetch the ID and engine directly. If not, then it is likely an
|
|
|
|
* old device trees, where the endpoint IDs were incorrect, but did not
|
|
|
|
* have endpoint connections between the backend and TCON across
|
|
|
|
* different display pipelines. It will fall back to the old method of
|
|
|
|
* traversing the of_graph to try and find a matching engine by device
|
|
|
|
* node.
|
|
|
|
*
|
|
|
|
* In the case of single display pipeline device trees, either method
|
|
|
|
* works.
|
|
|
|
*/
|
|
|
|
static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
|
|
|
|
struct device_node *node)
|
|
|
|
{
|
|
|
|
struct device_node *port;
|
|
|
|
struct sunxi_engine *engine;
|
|
|
|
|
|
|
|
port = of_graph_get_port_by_id(node, 0);
|
|
|
|
if (!port)
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Is this a corrected device tree with cross pipeline
|
|
|
|
* connections between the backend and TCON?
|
|
|
|
*/
|
|
|
|
if (of_get_child_count(port) > 1) {
|
2018-07-11 03:35:05 +07:00
|
|
|
int id;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* When pipeline has the same number of TCONs and engines which
|
|
|
|
* are represented by frontends/backends (DE1) or mixers (DE2),
|
|
|
|
* we match them by their respective IDs. However, if pipeline
|
|
|
|
* contains TCON TOP, chances are that there are either more
|
|
|
|
* TCONs than engines (R40) or TCONs with non-consecutive ids.
|
|
|
|
* (H6). In that case it's easier just use TCON index in list
|
|
|
|
* as an id. That means that on R40, any 2 TCONs can be enabled
|
|
|
|
* in DT out of 4 (there are 2 mixers). Due to the design of
|
|
|
|
* TCON TOP, remaining 2 TCONs can't be connected to anything
|
|
|
|
* anyway.
|
|
|
|
*/
|
|
|
|
if (sun4i_tcon_connected_to_tcon_top(node))
|
|
|
|
id = sun4i_tcon_get_index(drv);
|
|
|
|
else
|
|
|
|
id = sun4i_tcon_of_get_id_from_port(port);
|
drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID
The device tree binding for sun4i-drm says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.
We should be able to get the TCON's ID directly from any of the remote
endpoints from its input port. With the ID, we can then go through the
list of registered engines and find a matching one by ID.
However the A31 device tree is incorrect. We assumed that there were no
cross pipeline connections between the backends and TCONs. As a result,
in all the endpoints between the backends and TCONs of the second
display pipeline, the endpoint IDs were incorrectly set to 0, when in
fact they should've been set to 1.
To maintain compatibility with this incorrect device tree, we first
check if the TCON's input port has 1 or many endpoints. If there are
more than 1, then it is likely a fixed version, and we can proceed
with the new method. If there is only 1 endpoint, then it is possibly
an incorrect version, or it could be the SoC only has one pipeline.
In either case we fall back to using the old method of traversing
the input connections to find a matching engine, and then get its
ID.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908075016.18657-5-wens@csie.org
2017-09-08 14:50:12 +07:00
|
|
|
|
|
|
|
/* Get our engine by matching our ID */
|
|
|
|
engine = sun4i_tcon_get_engine_by_id(drv, id);
|
|
|
|
|
|
|
|
of_node_put(port);
|
|
|
|
return engine;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Fallback to old method by traversing input endpoints */
|
|
|
|
of_node_put(port);
|
2018-06-25 19:02:50 +07:00
|
|
|
return sun4i_tcon_find_engine_traverse(drv, node, 0);
|
drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID
The device tree binding for sun4i-drm says:
For all connections between components up to the TCONs in the display
pipeline, when there are multiple components of the same type at the
same depth, the local endpoint ID must be the same as the remote
component's index. For example, if the remote endpoint is Frontend 1,
then the local endpoint ID must be 1.
We should be able to get the TCON's ID directly from any of the remote
endpoints from its input port. With the ID, we can then go through the
list of registered engines and find a matching one by ID.
However the A31 device tree is incorrect. We assumed that there were no
cross pipeline connections between the backends and TCONs. As a result,
in all the endpoints between the backends and TCONs of the second
display pipeline, the endpoint IDs were incorrectly set to 0, when in
fact they should've been set to 1.
To maintain compatibility with this incorrect device tree, we first
check if the TCON's input port has 1 or many endpoints. If there are
more than 1, then it is likely a fixed version, and we can proceed
with the new method. If there is only 1 endpoint, then it is possibly
an incorrect version, or it could be the SoC only has one pipeline.
In either case we fall back to using the old method of traversing
the input connections to find a matching engine, and then get its
ID.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170908075016.18657-5-wens@csie.org
2017-09-08 14:50:12 +07:00
|
|
|
}
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
static int sun4i_tcon_bind(struct device *dev, struct device *master,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct drm_device *drm = data;
|
|
|
|
struct sun4i_drv *drv = drm->dev_private;
|
2017-05-17 21:47:17 +07:00
|
|
|
struct sunxi_engine *engine;
|
2017-12-21 18:02:33 +07:00
|
|
|
struct device_node *remote;
|
2015-10-29 15:36:23 +07:00
|
|
|
struct sun4i_tcon *tcon;
|
2018-03-15 18:41:31 +07:00
|
|
|
struct reset_control *edp_rstc;
|
2017-12-21 18:02:33 +07:00
|
|
|
bool has_lvds_rst, has_lvds_alt, can_lvds;
|
2015-10-29 15:36:23 +07:00
|
|
|
int ret;
|
|
|
|
|
2017-05-17 21:47:17 +07:00
|
|
|
engine = sun4i_tcon_find_engine(drv, dev->of_node);
|
|
|
|
if (IS_ERR(engine)) {
|
|
|
|
dev_err(dev, "Couldn't find matching engine\n");
|
2017-04-21 15:38:50 +07:00
|
|
|
return -EPROBE_DEFER;
|
2017-04-21 15:38:54 +07:00
|
|
|
}
|
2017-04-21 15:38:50 +07:00
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
|
|
|
|
if (!tcon)
|
|
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, tcon);
|
|
|
|
tcon->drm = drm;
|
2016-07-19 20:17:27 +07:00
|
|
|
tcon->dev = dev;
|
2017-05-17 21:47:17 +07:00
|
|
|
tcon->id = engine->id;
|
2016-10-20 10:43:39 +07:00
|
|
|
tcon->quirks = of_device_get_match_data(dev);
|
2015-10-29 15:36:23 +07:00
|
|
|
|
|
|
|
tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
|
|
|
|
if (IS_ERR(tcon->lcd_rst)) {
|
|
|
|
dev_err(dev, "Couldn't get our reset line\n");
|
|
|
|
return PTR_ERR(tcon->lcd_rst);
|
|
|
|
}
|
|
|
|
|
2018-03-15 18:41:31 +07:00
|
|
|
if (tcon->quirks->needs_edp_reset) {
|
|
|
|
edp_rstc = devm_reset_control_get_shared(dev, "edp");
|
|
|
|
if (IS_ERR(edp_rstc)) {
|
|
|
|
dev_err(dev, "Couldn't get edp reset line\n");
|
|
|
|
return PTR_ERR(edp_rstc);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = reset_control_deassert(edp_rstc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't deassert edp reset line\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
/* Make sure our TCON is reset */
|
2017-09-08 16:00:16 +07:00
|
|
|
ret = reset_control_reset(tcon->lcd_rst);
|
2015-10-29 15:36:23 +07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't deassert our reset line\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-02-21 19:57:01 +07:00
|
|
|
if (tcon->quirks->supports_lvds) {
|
|
|
|
/*
|
|
|
|
* This can only be made optional since we've had DT
|
|
|
|
* nodes without the LVDS reset properties.
|
|
|
|
*
|
|
|
|
* If the property is missing, just disable LVDS, and
|
|
|
|
* print a warning.
|
|
|
|
*/
|
|
|
|
tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
|
|
|
|
if (IS_ERR(tcon->lvds_rst)) {
|
|
|
|
dev_err(dev, "Couldn't get our reset line\n");
|
|
|
|
return PTR_ERR(tcon->lvds_rst);
|
|
|
|
} else if (tcon->lvds_rst) {
|
|
|
|
has_lvds_rst = true;
|
|
|
|
reset_control_reset(tcon->lvds_rst);
|
|
|
|
} else {
|
|
|
|
has_lvds_rst = false;
|
|
|
|
}
|
2017-12-21 18:02:33 +07:00
|
|
|
|
2018-02-21 19:57:01 +07:00
|
|
|
/*
|
|
|
|
* This can only be made optional since we've had DT
|
|
|
|
* nodes without the LVDS reset properties.
|
|
|
|
*
|
|
|
|
* If the property is missing, just disable LVDS, and
|
|
|
|
* print a warning.
|
|
|
|
*/
|
|
|
|
if (tcon->quirks->has_lvds_alt) {
|
|
|
|
tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
|
|
|
|
if (IS_ERR(tcon->lvds_pll)) {
|
|
|
|
if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
|
|
|
|
has_lvds_alt = false;
|
|
|
|
} else {
|
|
|
|
dev_err(dev, "Couldn't get the LVDS PLL\n");
|
|
|
|
return PTR_ERR(tcon->lvds_pll);
|
|
|
|
}
|
2017-12-21 18:02:33 +07:00
|
|
|
} else {
|
2018-02-21 19:57:01 +07:00
|
|
|
has_lvds_alt = true;
|
2017-12-21 18:02:33 +07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-02-21 19:57:01 +07:00
|
|
|
if (!has_lvds_rst ||
|
|
|
|
(tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
|
|
|
|
dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
|
|
|
|
dev_warn(dev, "LVDS output disabled\n");
|
|
|
|
can_lvds = false;
|
|
|
|
} else {
|
|
|
|
can_lvds = true;
|
|
|
|
}
|
2017-12-21 18:02:33 +07:00
|
|
|
} else {
|
2018-02-21 19:57:01 +07:00
|
|
|
can_lvds = false;
|
2017-12-21 18:02:33 +07:00
|
|
|
}
|
|
|
|
|
2017-03-09 17:05:24 +07:00
|
|
|
ret = sun4i_tcon_init_clocks(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON clocks\n");
|
|
|
|
goto err_assert_reset;
|
|
|
|
}
|
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
ret = sun4i_tcon_init_regmap(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON regmap\n");
|
2017-03-09 17:05:24 +07:00
|
|
|
goto err_free_clocks;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
2018-02-15 03:09:01 +07:00
|
|
|
if (tcon->quirks->has_channel_0) {
|
|
|
|
ret = sun4i_dclk_create(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't create our TCON dot clock\n");
|
|
|
|
goto err_free_clocks;
|
|
|
|
}
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
ret = sun4i_tcon_init_irq(dev, tcon);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "Couldn't init our TCON interrupts\n");
|
2017-03-09 17:05:24 +07:00
|
|
|
goto err_free_dotclock;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
2017-05-17 21:47:17 +07:00
|
|
|
tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
|
drm/sun4i: Initialize crtc from tcon bind function
The tcon provides part of the functionality of the crtc, and also
provides the device node for the output port of the crtc. To be able
to use drm_of_find_possible_crtcs(), all crtc must be initialized before
any downstream encoders. The other part of the crtc is the display
backend.
The Rockchip DRM driver does this by first binding all vops, which is
their crtc, and this step also creates the crtc objects. Then all
remaining hardware components are bound. With the Allwinner display
pipeline, we have multiple components comprising the crtc, and varying
depths of the display pipeline. Since components are added with a depth
first search of the of_graph, we can initialize the crtc object within
the tcon bind function. Since the backend precedes the tcon, and the
backends cannot be muxed or switched around, we can be sure that the
associated backend is already initialized.
This patch also moves the crtc pointer from the main drm_device data to
the tcon device data. Besides the crtc callbacks, the crtc structure is
only used within the tcon driver to signal vblank events from its
interrupt handler.
As the crtc and layer bits are now called from the tcon bits, we must
move them from the sun4i-drm module to the sun4i-tcon module to avoid
circular dependencies between the two modules. This is because sun4i-drm
also calls into sun4i-tcon.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-02-23 15:05:37 +07:00
|
|
|
if (IS_ERR(tcon->crtc)) {
|
|
|
|
dev_err(dev, "Couldn't create our CRTC\n");
|
|
|
|
ret = PTR_ERR(tcon->crtc);
|
2017-12-07 22:58:50 +07:00
|
|
|
goto err_free_dotclock;
|
2015-10-29 15:36:23 +07:00
|
|
|
}
|
|
|
|
|
2018-06-25 19:02:51 +07:00
|
|
|
if (tcon->quirks->has_channel_0) {
|
|
|
|
/*
|
|
|
|
* If we have an LVDS panel connected to the TCON, we should
|
|
|
|
* just probe the LVDS connector. Otherwise, just probe RGB as
|
|
|
|
* we used to.
|
|
|
|
*/
|
|
|
|
remote = of_graph_get_remote_node(dev->of_node, 1, 0);
|
|
|
|
if (of_device_is_compatible(remote, "panel-lvds"))
|
|
|
|
if (can_lvds)
|
|
|
|
ret = sun4i_lvds_init(drm, tcon);
|
|
|
|
else
|
|
|
|
ret = -EINVAL;
|
2017-12-21 18:02:33 +07:00
|
|
|
else
|
2018-06-25 19:02:51 +07:00
|
|
|
ret = sun4i_rgb_init(drm, tcon);
|
|
|
|
of_node_put(remote);
|
2017-12-21 18:02:33 +07:00
|
|
|
|
2018-06-25 19:02:51 +07:00
|
|
|
if (ret < 0)
|
|
|
|
goto err_free_dotclock;
|
|
|
|
}
|
2016-05-17 22:56:06 +07:00
|
|
|
|
2017-09-08 14:50:14 +07:00
|
|
|
if (tcon->quirks->needs_de_be_mux) {
|
|
|
|
/*
|
|
|
|
* We assume there is no dynamic muxing of backends
|
|
|
|
* and TCONs, so we select the backend with same ID.
|
|
|
|
*
|
|
|
|
* While dynamic selection might be interesting, since
|
|
|
|
* the CRTC is tied to the TCON, while the layers are
|
|
|
|
* tied to the backends, this means, we will need to
|
|
|
|
* switch between groups of layers. There might not be
|
|
|
|
* a way to represent this constraint in DRM.
|
|
|
|
*/
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
|
|
|
|
SUN4I_TCON0_CTL_SRC_SEL_MASK,
|
|
|
|
tcon->id);
|
|
|
|
regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
|
|
|
|
SUN4I_TCON1_CTL_SRC_SEL_MASK,
|
|
|
|
tcon->id);
|
|
|
|
}
|
|
|
|
|
2017-04-21 15:38:50 +07:00
|
|
|
list_add_tail(&tcon->list, &drv->tcon_list);
|
|
|
|
|
2016-05-17 22:56:06 +07:00
|
|
|
return 0;
|
2015-10-29 15:36:23 +07:00
|
|
|
|
2017-03-09 17:05:24 +07:00
|
|
|
err_free_dotclock:
|
2018-02-15 03:09:01 +07:00
|
|
|
if (tcon->quirks->has_channel_0)
|
|
|
|
sun4i_dclk_free(tcon);
|
2015-10-29 15:36:23 +07:00
|
|
|
err_free_clocks:
|
|
|
|
sun4i_tcon_free_clocks(tcon);
|
|
|
|
err_assert_reset:
|
|
|
|
reset_control_assert(tcon->lcd_rst);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sun4i_tcon_unbind(struct device *dev, struct device *master,
|
|
|
|
void *data)
|
|
|
|
{
|
|
|
|
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
|
|
|
|
|
2017-04-21 15:38:50 +07:00
|
|
|
list_del(&tcon->list);
|
2018-02-15 03:09:01 +07:00
|
|
|
if (tcon->quirks->has_channel_0)
|
|
|
|
sun4i_dclk_free(tcon);
|
2015-10-29 15:36:23 +07:00
|
|
|
sun4i_tcon_free_clocks(tcon);
|
|
|
|
}
|
|
|
|
|
2016-11-13 00:19:58 +07:00
|
|
|
static const struct component_ops sun4i_tcon_ops = {
|
2015-10-29 15:36:23 +07:00
|
|
|
.bind = sun4i_tcon_bind,
|
|
|
|
.unbind = sun4i_tcon_unbind,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int sun4i_tcon_probe(struct platform_device *pdev)
|
|
|
|
{
|
2015-10-29 15:37:32 +07:00
|
|
|
struct device_node *node = pdev->dev.of_node;
|
2018-06-25 19:02:52 +07:00
|
|
|
const struct sun4i_tcon_quirks *quirks;
|
2016-04-11 17:16:33 +07:00
|
|
|
struct drm_bridge *bridge;
|
2015-10-29 15:37:32 +07:00
|
|
|
struct drm_panel *panel;
|
2017-03-30 01:55:46 +07:00
|
|
|
int ret;
|
2015-10-29 15:37:32 +07:00
|
|
|
|
2018-06-25 19:02:52 +07:00
|
|
|
quirks = of_device_get_match_data(&pdev->dev);
|
|
|
|
|
|
|
|
/* panels and bridges are present only on TCONs with channel 0 */
|
|
|
|
if (quirks->has_channel_0) {
|
|
|
|
ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
return ret;
|
|
|
|
}
|
2015-10-29 15:37:32 +07:00
|
|
|
|
2015-10-29 15:36:23 +07:00
|
|
|
return component_add(&pdev->dev, &sun4i_tcon_ops);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sun4i_tcon_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
component_del(&pdev->dev, &sun4i_tcon_ops);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-10 10:19:58 +07:00
|
|
|
/* platform specific TCON muxing callbacks */
|
2017-10-17 19:17:59 +07:00
|
|
|
static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
|
|
|
|
u32 shift;
|
|
|
|
|
|
|
|
if (!tcon0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (encoder->encoder_type) {
|
|
|
|
case DRM_MODE_ENCODER_TMDS:
|
|
|
|
/* HDMI */
|
|
|
|
shift = 8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
|
|
|
|
0x3 << shift, tcon->id << shift);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-10-10 10:19:58 +07:00
|
|
|
static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
|
2017-10-17 16:06:10 +07:00
|
|
|
const struct drm_encoder *encoder)
|
2017-10-10 10:19:58 +07:00
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
|
|
|
|
val = 1;
|
|
|
|
else
|
|
|
|
val = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: Undocumented bits
|
|
|
|
*/
|
|
|
|
return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
|
|
|
|
}
|
|
|
|
|
2017-10-10 10:19:59 +07:00
|
|
|
static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
|
2017-10-17 16:06:10 +07:00
|
|
|
const struct drm_encoder *encoder)
|
2017-10-10 10:19:59 +07:00
|
|
|
{
|
|
|
|
struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
|
|
|
|
u32 shift;
|
|
|
|
|
|
|
|
if (!tcon0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
switch (encoder->encoder_type) {
|
|
|
|
case DRM_MODE_ENCODER_TMDS:
|
|
|
|
/* HDMI */
|
|
|
|
shift = 8;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* TODO A31 has MIPI DSI but A31s does not */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
|
|
|
|
0x3 << shift, tcon->id << shift);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-07-11 03:35:06 +07:00
|
|
|
static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
|
|
|
|
const struct drm_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct device_node *port, *remote;
|
|
|
|
struct platform_device *pdev;
|
|
|
|
int id, ret;
|
|
|
|
|
|
|
|
/* find TCON TOP platform device and TCON id */
|
|
|
|
|
|
|
|
port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
|
|
|
|
if (!port)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
id = sun4i_tcon_of_get_id_from_port(port);
|
|
|
|
of_node_put(port);
|
|
|
|
|
|
|
|
remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
|
|
|
|
if (!remote)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pdev = of_find_device_by_node(remote);
|
|
|
|
of_node_put(remote);
|
|
|
|
if (!pdev)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2018-09-11 18:33:25 +07:00
|
|
|
if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
|
|
|
|
encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
|
2018-07-11 03:35:06 +07:00
|
|
|
ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-09-11 18:33:25 +07:00
|
|
|
if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
|
|
|
|
ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2018-07-11 03:35:06 +07:00
|
|
|
}
|
|
|
|
|
2017-10-17 19:17:59 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-10-17 19:17:59 +07:00
|
|
|
.has_channel_1 = true,
|
|
|
|
.set_mux = sun4i_a10_tcon_set_mux,
|
|
|
|
};
|
|
|
|
|
2016-10-20 10:43:39 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-10-10 10:19:58 +07:00
|
|
|
.has_channel_1 = true,
|
|
|
|
.set_mux = sun5i_a13_tcon_set_mux,
|
2016-10-20 10:43:39 +07:00
|
|
|
};
|
|
|
|
|
2016-10-20 10:43:40 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-09-08 14:50:14 +07:00
|
|
|
.has_channel_1 = true,
|
2017-12-21 18:02:33 +07:00
|
|
|
.has_lvds_alt = true,
|
2017-09-08 14:50:14 +07:00
|
|
|
.needs_de_be_mux = true,
|
2017-10-10 10:19:59 +07:00
|
|
|
.set_mux = sun6i_tcon_set_mux,
|
2016-10-20 10:43:40 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-09-08 14:50:14 +07:00
|
|
|
.has_channel_1 = true,
|
|
|
|
.needs_de_be_mux = true,
|
2016-10-20 10:43:40 +07:00
|
|
|
};
|
|
|
|
|
2017-10-17 19:18:02 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-10-17 19:18:02 +07:00
|
|
|
.has_channel_1 = true,
|
|
|
|
/* Same display pipeline structure as A10 */
|
|
|
|
.set_mux = sun4i_a10_tcon_set_mux,
|
|
|
|
};
|
|
|
|
|
2016-10-20 10:43:39 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-12-21 18:02:33 +07:00
|
|
|
.has_lvds_alt = true,
|
2016-10-20 10:43:39 +07:00
|
|
|
};
|
|
|
|
|
2017-12-21 18:02:34 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
|
2018-02-21 19:57:01 +07:00
|
|
|
.supports_lvds = true,
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-12-21 18:02:34 +07:00
|
|
|
};
|
|
|
|
|
2018-02-15 03:09:02 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
|
|
|
|
.has_channel_1 = true,
|
|
|
|
};
|
|
|
|
|
2018-07-11 03:35:06 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
|
|
|
|
.has_channel_1 = true,
|
|
|
|
.set_mux = sun8i_r40_tcon_tv_set_mux,
|
|
|
|
};
|
|
|
|
|
2017-05-17 21:47:22 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
|
2018-02-15 03:09:01 +07:00
|
|
|
.has_channel_0 = true,
|
2017-05-17 21:47:22 +07:00
|
|
|
};
|
|
|
|
|
2018-03-15 18:41:31 +07:00
|
|
|
static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
|
|
|
|
.has_channel_0 = true,
|
|
|
|
.needs_edp_reset = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
|
|
|
|
.has_channel_1 = true,
|
|
|
|
.needs_edp_reset = true,
|
|
|
|
};
|
|
|
|
|
2017-11-27 15:46:32 +07:00
|
|
|
/* sun4i_drv uses this list to check if a device node is a TCON */
|
|
|
|
const struct of_device_id sun4i_tcon_of_table[] = {
|
2017-10-17 19:17:59 +07:00
|
|
|
{ .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
|
2016-10-20 10:43:39 +07:00
|
|
|
{ .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
|
2016-10-20 10:43:40 +07:00
|
|
|
{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
|
|
|
|
{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
|
2017-10-17 19:18:02 +07:00
|
|
|
{ .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
|
2019-01-25 10:23:09 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
|
2016-10-20 10:43:39 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
|
2017-12-21 18:02:34 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
|
2018-02-15 03:09:02 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
|
2018-07-11 03:35:06 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
|
2017-05-17 21:47:22 +07:00
|
|
|
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
|
2018-03-15 18:41:31 +07:00
|
|
|
{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
|
|
|
|
{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
|
2015-10-29 15:36:23 +07:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
|
2017-11-27 15:46:32 +07:00
|
|
|
EXPORT_SYMBOL(sun4i_tcon_of_table);
|
2015-10-29 15:36:23 +07:00
|
|
|
|
|
|
|
static struct platform_driver sun4i_tcon_platform_driver = {
|
|
|
|
.probe = sun4i_tcon_probe,
|
|
|
|
.remove = sun4i_tcon_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "sun4i-tcon",
|
|
|
|
.of_match_table = sun4i_tcon_of_table,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(sun4i_tcon_platform_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
|
|
MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|