2016-05-24 05:44:26 +07:00
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/*
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* GXBB clock tree IDs
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*/
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#ifndef __GXBB_CLKC_H
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#define __GXBB_CLKC_H
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#define CLKID_CPUCLK 1
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2016-08-22 19:49:37 +07:00
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#define CLKID_HDMI_PLL 2
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2016-08-03 04:40:11 +07:00
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#define CLKID_FCLK_DIV2 4
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2016-08-22 19:49:37 +07:00
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#define CLKID_FCLK_DIV3 5
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#define CLKID_FCLK_DIV4 6
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2017-03-22 17:32:26 +07:00
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#define CLKID_GP0_PLL 9
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2016-05-24 05:44:26 +07:00
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#define CLKID_CLK81 12
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2016-09-07 04:38:44 +07:00
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#define CLKID_MPLL2 15
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2016-09-14 17:06:05 +07:00
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#define CLKID_I2C 22
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2017-01-19 21:58:20 +07:00
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#define CLKID_SAR_ADC 23
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2017-02-22 13:55:24 +07:00
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#define CLKID_RNG0 25
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#define CLKID_SPI 34
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2016-05-24 05:44:26 +07:00
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#define CLKID_ETH 36
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2017-03-09 17:41:54 +07:00
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#define CLKID_AIU_GLUE 38
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#define CLKID_I2S_OUT 40
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#define CLKID_MIXER_IFACE 44
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#define CLKID_AIU 47
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2016-09-05 04:31:46 +07:00
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#define CLKID_USB0 50
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#define CLKID_USB1 51
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#define CLKID_USB 55
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2017-01-17 19:08:48 +07:00
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#define CLKID_HDMI_PCLK 63
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2016-09-05 04:31:46 +07:00
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#define CLKID_USB1_DDR_BRIDGE 64
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#define CLKID_USB0_DDR_BRIDGE 65
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2017-01-19 21:58:20 +07:00
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#define CLKID_SANA 69
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2017-01-17 19:08:48 +07:00
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#define CLKID_GCLK_VENCI_INT0 77
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2017-03-09 17:41:54 +07:00
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#define CLKID_AOCLK_GATE 80
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2016-09-14 17:06:05 +07:00
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#define CLKID_AO_I2C 93
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2016-08-03 04:40:11 +07:00
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#define CLKID_SD_EMMC_A 94
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#define CLKID_SD_EMMC_B 95
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#define CLKID_SD_EMMC_C 96
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2017-01-19 21:58:20 +07:00
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#define CLKID_SAR_ADC_CLK 97
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#define CLKID_SAR_ADC_SEL 98
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2017-03-22 17:18:53 +07:00
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#define CLKID_MALI_0_SEL 100
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#define CLKID_MALI_0 102
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#define CLKID_MALI_1_SEL 103
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#define CLKID_MALI_1 105
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#define CLKID_MALI 106
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2016-05-24 05:44:26 +07:00
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#endif /* __GXBB_CLKC_H */
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