2013-06-25 18:15:10 +07:00
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
|
|
|
|
|
* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
|
* publishhed by the Free Software Foundation.
|
|
|
|
|
*/
|
|
|
|
|
#include "st-pincfg.h"
|
2014-01-08 19:49:57 +07:00
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
2013-06-25 18:15:10 +07:00
|
|
|
/ {
|
|
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
|
gpio0 = &PIO0;
|
|
|
|
|
gpio1 = &PIO1;
|
|
|
|
|
gpio2 = &PIO2;
|
|
|
|
|
gpio3 = &PIO3;
|
|
|
|
|
gpio4 = &PIO4;
|
|
|
|
|
gpio5 = &PIO5;
|
|
|
|
|
gpio6 = &PIO6;
|
|
|
|
|
gpio7 = &PIO7;
|
|
|
|
|
gpio8 = &PIO8;
|
|
|
|
|
gpio9 = &PIO9;
|
|
|
|
|
gpio10 = &PIO10;
|
|
|
|
|
gpio11 = &PIO11;
|
|
|
|
|
gpio12 = &PIO12;
|
|
|
|
|
gpio13 = &PIO13;
|
|
|
|
|
gpio14 = &PIO14;
|
|
|
|
|
gpio15 = &PIO15;
|
|
|
|
|
gpio16 = &PIO16;
|
|
|
|
|
gpio17 = &PIO17;
|
|
|
|
|
gpio18 = &PIO18;
|
|
|
|
|
gpio19 = &PIO100;
|
|
|
|
|
gpio20 = &PIO101;
|
|
|
|
|
gpio21 = &PIO102;
|
|
|
|
|
gpio22 = &PIO103;
|
|
|
|
|
gpio23 = &PIO104;
|
|
|
|
|
gpio24 = &PIO105;
|
|
|
|
|
gpio25 = &PIO106;
|
|
|
|
|
gpio26 = &PIO107;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
soc {
|
|
|
|
|
pin-controller-sbc {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stih415-sbc-pinctrl";
|
|
|
|
|
st,syscfg = <&syscfg_sbc>;
|
2014-01-08 19:49:57 +07:00
|
|
|
reg = <0xfe61f080 0x4>;
|
|
|
|
|
reg-names = "irqmux";
|
|
|
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupts-names = "irqmux";
|
2013-06-25 18:15:10 +07:00
|
|
|
ranges = <0 0xfe610000 0x5000>;
|
|
|
|
|
|
|
|
|
|
PIO0: gpio@fe610000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0 0x100>;
|
|
|
|
|
st,bank-name = "PIO0";
|
|
|
|
|
};
|
|
|
|
|
PIO1: gpio@fe611000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
st,bank-name = "PIO1";
|
|
|
|
|
};
|
|
|
|
|
PIO2: gpio@fe612000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x2000 0x100>;
|
|
|
|
|
st,bank-name = "PIO2";
|
|
|
|
|
};
|
|
|
|
|
PIO3: gpio@fe613000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x3000 0x100>;
|
|
|
|
|
st,bank-name = "PIO3";
|
|
|
|
|
};
|
|
|
|
|
PIO4: gpio@fe614000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x4000 0x100>;
|
|
|
|
|
st,bank-name = "PIO4";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sbc_serial1 {
|
|
|
|
|
pinctrl_sbc_serial1:sbc_serial1 {
|
|
|
|
|
st,pins {
|
|
|
|
|
tx = <&PIO2 6 ALT3 OUT>;
|
|
|
|
|
rx = <&PIO2 7 ALT3 IN>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-11-06 15:25:14 +07:00
|
|
|
|
|
|
|
|
sbc_i2c0 {
|
|
|
|
|
pinctrl_sbc_i2c0_default: sbc_i2c0-default {
|
|
|
|
|
st,pins {
|
|
|
|
|
sda = <&PIO4 6 ALT1 BIDIR>;
|
|
|
|
|
scl = <&PIO4 5 ALT1 BIDIR>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sbc_i2c1 {
|
|
|
|
|
pinctrl_sbc_i2c1_default: sbc_i2c1-default {
|
|
|
|
|
st,pins {
|
|
|
|
|
sda = <&PIO3 2 ALT2 BIDIR>;
|
|
|
|
|
scl = <&PIO3 1 ALT2 BIDIR>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-01-29 23:19:44 +07:00
|
|
|
|
2013-11-11 20:19:18 +07:00
|
|
|
rc{
|
|
|
|
|
pinctrl_ir: ir0 {
|
|
|
|
|
st,pins {
|
|
|
|
|
ir = <&PIO4 0 ALT2 IN>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-01-29 23:19:44 +07:00
|
|
|
gmac1 {
|
|
|
|
|
pinctrl_mii1: mii1 {
|
|
|
|
|
st,pins {
|
|
|
|
|
txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
|
|
|
|
|
col = <&PIO0 7 ALT1 IN BYPASS 1000>;
|
|
|
|
|
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
|
|
|
|
|
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
|
|
|
|
|
crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
|
|
|
|
|
mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
|
|
|
|
|
rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
|
|
|
|
|
phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_rgmii1: rgmii1-0 {
|
|
|
|
|
st,pins {
|
|
|
|
|
txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>;
|
|
|
|
|
txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>;
|
|
|
|
|
txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>;
|
|
|
|
|
txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>;
|
|
|
|
|
txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
|
|
|
|
|
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
|
|
|
|
|
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
|
|
|
|
|
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
|
|
|
|
|
rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>;
|
|
|
|
|
rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>;
|
|
|
|
|
rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>;
|
|
|
|
|
rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>;
|
|
|
|
|
|
|
|
|
|
rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
|
|
|
|
|
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
|
|
|
|
|
phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
|
|
|
|
|
|
|
|
|
|
clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-06-25 18:15:10 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pin-controller-front {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stih415-front-pinctrl";
|
|
|
|
|
st,syscfg = <&syscfg_front>;
|
2014-01-08 19:49:57 +07:00
|
|
|
reg = <0xfee0f080 0x4>;
|
|
|
|
|
reg-names = "irqmux";
|
|
|
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupts-names = "irqmux";
|
2013-06-25 18:15:10 +07:00
|
|
|
ranges = <0 0xfee00000 0x8000>;
|
|
|
|
|
|
|
|
|
|
PIO5: gpio@fee00000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0 0x100>;
|
|
|
|
|
st,bank-name = "PIO5";
|
|
|
|
|
};
|
|
|
|
|
PIO6: gpio@fee01000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
st,bank-name = "PIO6";
|
|
|
|
|
};
|
|
|
|
|
PIO7: gpio@fee02000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x2000 0x100>;
|
|
|
|
|
st,bank-name = "PIO7";
|
|
|
|
|
};
|
|
|
|
|
PIO8: gpio@fee03000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x3000 0x100>;
|
|
|
|
|
st,bank-name = "PIO8";
|
|
|
|
|
};
|
|
|
|
|
PIO9: gpio@fee04000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x4000 0x100>;
|
|
|
|
|
st,bank-name = "PIO9";
|
|
|
|
|
};
|
|
|
|
|
PIO10: gpio@fee05000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x5000 0x100>;
|
|
|
|
|
st,bank-name = "PIO10";
|
|
|
|
|
};
|
|
|
|
|
PIO11: gpio@fee06000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x6000 0x100>;
|
|
|
|
|
st,bank-name = "PIO11";
|
|
|
|
|
};
|
|
|
|
|
PIO12: gpio@fee07000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x7000 0x100>;
|
|
|
|
|
st,bank-name = "PIO12";
|
|
|
|
|
};
|
2013-11-06 15:25:14 +07:00
|
|
|
|
|
|
|
|
i2c0 {
|
|
|
|
|
pinctrl_i2c0_default: i2c0-default {
|
|
|
|
|
st,pins {
|
|
|
|
|
sda = <&PIO9 3 ALT1 BIDIR>;
|
|
|
|
|
scl = <&PIO9 2 ALT1 BIDIR>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1 {
|
|
|
|
|
pinctrl_i2c1_default: i2c1-default {
|
|
|
|
|
st,pins {
|
|
|
|
|
sda = <&PIO12 1 ALT1 BIDIR>;
|
|
|
|
|
scl = <&PIO12 0 ALT1 BIDIR>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-06-25 18:15:10 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pin-controller-rear {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stih415-rear-pinctrl";
|
|
|
|
|
st,syscfg = <&syscfg_rear>;
|
2014-01-08 19:49:57 +07:00
|
|
|
reg = <0xfe82f080 0x4>;
|
|
|
|
|
reg-names = "irqmux";
|
|
|
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupts-names = "irqmux";
|
2013-06-25 18:15:10 +07:00
|
|
|
ranges = <0 0xfe820000 0x8000>;
|
|
|
|
|
|
|
|
|
|
PIO13: gpio@fe820000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0 0x100>;
|
|
|
|
|
st,bank-name = "PIO13";
|
|
|
|
|
};
|
|
|
|
|
PIO14: gpio@fe821000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
st,bank-name = "PIO14";
|
|
|
|
|
};
|
|
|
|
|
PIO15: gpio@fe822000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x2000 0x100>;
|
|
|
|
|
st,bank-name = "PIO15";
|
|
|
|
|
};
|
|
|
|
|
PIO16: gpio@fe823000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x3000 0x100>;
|
|
|
|
|
st,bank-name = "PIO16";
|
|
|
|
|
};
|
|
|
|
|
PIO17: gpio@fe824000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x4000 0x100>;
|
|
|
|
|
st,bank-name = "PIO17";
|
|
|
|
|
};
|
|
|
|
|
PIO18: gpio@fe825000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x5000 0x100>;
|
|
|
|
|
st,bank-name = "PIO18";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
serial2 {
|
|
|
|
|
pinctrl_serial2: serial2-0 {
|
|
|
|
|
st,pins {
|
|
|
|
|
tx = <&PIO17 4 ALT2 OUT>;
|
|
|
|
|
rx = <&PIO17 5 ALT2 IN>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-01-29 23:19:44 +07:00
|
|
|
|
|
|
|
|
gmac0{
|
|
|
|
|
pinctrl_mii0: mii0 {
|
|
|
|
|
st,pins {
|
|
|
|
|
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
|
|
|
|
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
|
|
|
|
|
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
|
|
|
|
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
|
|
|
|
|
|
|
|
|
|
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
|
|
|
|
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
|
|
|
|
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
|
|
|
|
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
|
|
|
|
|
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
|
|
|
|
|
|
|
|
|
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
|
|
|
|
|
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
|
|
|
|
phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>;
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_gmii0: gmii0 {
|
|
|
|
|
st,pins {
|
|
|
|
|
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
|
|
|
|
|
mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>;
|
|
|
|
|
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
|
|
|
|
|
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
|
|
|
|
|
|
|
|
|
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
|
|
|
|
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
|
|
|
|
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
|
|
|
|
|
|
|
|
|
|
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
|
|
|
|
|
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
|
|
|
|
|
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
|
|
|
|
|
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
|
|
|
|
|
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
|
|
|
|
|
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
|
|
|
|
|
|
|
|
|
|
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
|
|
|
|
|
clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
|
|
|
|
|
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-06-25 18:15:10 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pin-controller-left {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stih415-left-pinctrl";
|
|
|
|
|
st,syscfg = <&syscfg_left>;
|
2014-01-08 19:49:57 +07:00
|
|
|
reg = <0xfd6bf080 0x4>;
|
|
|
|
|
reg-names = "irqmux";
|
|
|
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupts-names = "irqmux";
|
2013-06-25 18:15:10 +07:00
|
|
|
ranges = <0 0xfd6b0000 0x3000>;
|
|
|
|
|
|
|
|
|
|
PIO100: gpio@fd6b0000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0 0x100>;
|
|
|
|
|
st,bank-name = "PIO100";
|
|
|
|
|
};
|
|
|
|
|
PIO101: gpio@fd6b1000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
st,bank-name = "PIO101";
|
|
|
|
|
};
|
|
|
|
|
PIO102: gpio@fd6b2000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x2000 0x100>;
|
|
|
|
|
st,bank-name = "PIO102";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pin-controller-right {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "st,stih415-right-pinctrl";
|
|
|
|
|
st,syscfg = <&syscfg_right>;
|
2014-01-08 19:49:57 +07:00
|
|
|
reg = <0xfd33f080 0x4>;
|
|
|
|
|
reg-names = "irqmux";
|
|
|
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupts-names = "irqmux";
|
2013-06-25 18:15:10 +07:00
|
|
|
ranges = <0 0xfd330000 0x5000>;
|
|
|
|
|
|
|
|
|
|
PIO103: gpio@fd330000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0 0x100>;
|
|
|
|
|
st,bank-name = "PIO103";
|
|
|
|
|
};
|
|
|
|
|
PIO104: gpio@fd331000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
st,bank-name = "PIO104";
|
|
|
|
|
};
|
|
|
|
|
PIO105: gpio@fd332000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x2000 0x100>;
|
|
|
|
|
st,bank-name = "PIO105";
|
|
|
|
|
};
|
|
|
|
|
PIO106: gpio@fd333000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x3000 0x100>;
|
|
|
|
|
st,bank-name = "PIO106";
|
|
|
|
|
};
|
|
|
|
|
PIO107: gpio@fd334000 {
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <1>;
|
2014-01-08 19:49:57 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
2013-06-25 18:15:10 +07:00
|
|
|
reg = <0x4000 0x100>;
|
|
|
|
|
st,bank-name = "PIO107";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
