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linux_dsm_epyc7002/drivers/gpu/drm/pl111/pl111_vexpress.h

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drm/pl111: Support the Versatile Express The Versatile Express uses a special configuration controller deeply embedded in the system motherboard FPGA to multiplex the two to three (!) display controller instances out to the single SiI9022 bridge. Set up an extra file with the logic to probe to the FPGA mux register on the system controller bus, then parse the device tree to see if there is a CLCD or HDLCD instance on the core tile (also known as the daughterboard) by looking in the root of the device tree for compatible nodes. - If there is a HDLCD on the core tile, and there is a driver for it, we exit probe and deactivate the motherboard CLCD. We do not touch the DVI mux in this case, to make sure we don't break HDLCD. - If there is a CLCD on both the motherboard and the core tile (only the CA9 has this) the core tile CLCD takes precedence and get muxed to the DVI connector. - Only if there is no working graphics on the core tile, the motherboard CLCD is probed and muxed to the DVI connector. Core tile graphics should always take precedence as it can address all memory and is also faster, however the motherboard CLCD is good to have around for diagnostics and testing. It is possible to test the motherboard CLCD by setting the status = "disabled" property on the core tile CLCD or HDLCD. Scale down the Versatile Express to 16BPP so we can support a 1024x768 display despite the bus bandwidth restrictions on this platform. (The motherboard CLCD supports slightly lower resolution.) Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Eric Anholt <eric@anholt.net> Tested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180502134719.8388-1-linus.walleij@linaro.org
2018-05-02 20:47:18 +07:00
// SPDX-License-Identifier: GPL-2.0
struct device;
struct pl111_drm_dev_private;
struct regmap;
#ifdef CONFIG_ARCH_VEXPRESS
int pl111_vexpress_clcd_init(struct device *dev,
struct pl111_drm_dev_private *priv,
struct regmap *map);
drm/pl111: Fix module probe bug Commit a30933c27602 ("drm/pl111: Support the Versatile Express") Added a second module using the builtin_platform_driver() call, which works fine as long as you do not try to build the PL111 driver as a module, because a module can only have one initcall and cause the following build bug: (...) multiple definition of `init_module' (...) Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Eric Anholt <eric@anholt.net> Cc: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Fixes: a30933c27602 ("drm/pl111: Support the Versatile Express") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180503140431.5798-1-linus.walleij@linaro.org
2018-05-03 21:04:31 +07:00
int vexpress_muxfpga_init(void);
drm/pl111: Support the Versatile Express The Versatile Express uses a special configuration controller deeply embedded in the system motherboard FPGA to multiplex the two to three (!) display controller instances out to the single SiI9022 bridge. Set up an extra file with the logic to probe to the FPGA mux register on the system controller bus, then parse the device tree to see if there is a CLCD or HDLCD instance on the core tile (also known as the daughterboard) by looking in the root of the device tree for compatible nodes. - If there is a HDLCD on the core tile, and there is a driver for it, we exit probe and deactivate the motherboard CLCD. We do not touch the DVI mux in this case, to make sure we don't break HDLCD. - If there is a CLCD on both the motherboard and the core tile (only the CA9 has this) the core tile CLCD takes precedence and get muxed to the DVI connector. - Only if there is no working graphics on the core tile, the motherboard CLCD is probed and muxed to the DVI connector. Core tile graphics should always take precedence as it can address all memory and is also faster, however the motherboard CLCD is good to have around for diagnostics and testing. It is possible to test the motherboard CLCD by setting the status = "disabled" property on the core tile CLCD or HDLCD. Scale down the Versatile Express to 16BPP so we can support a 1024x768 display despite the bus bandwidth restrictions on this platform. (The motherboard CLCD supports slightly lower resolution.) Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Eric Anholt <eric@anholt.net> Tested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180502134719.8388-1-linus.walleij@linaro.org
2018-05-02 20:47:18 +07:00
#else
static inline int pl111_vexpress_clcd_init(struct device *dev,
struct pl111_drm_dev_private *priv,
struct regmap *map)
{
return -ENODEV;
}
drm/pl111: Fix module probe bug Commit a30933c27602 ("drm/pl111: Support the Versatile Express") Added a second module using the builtin_platform_driver() call, which works fine as long as you do not try to build the PL111 driver as a module, because a module can only have one initcall and cause the following build bug: (...) multiple definition of `init_module' (...) Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Eric Anholt <eric@anholt.net> Cc: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Fixes: a30933c27602 ("drm/pl111: Support the Versatile Express") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180503140431.5798-1-linus.walleij@linaro.org
2018-05-03 21:04:31 +07:00
static inline int vexpress_muxfpga_init(void)
{
return 0;
}
drm/pl111: Support the Versatile Express The Versatile Express uses a special configuration controller deeply embedded in the system motherboard FPGA to multiplex the two to three (!) display controller instances out to the single SiI9022 bridge. Set up an extra file with the logic to probe to the FPGA mux register on the system controller bus, then parse the device tree to see if there is a CLCD or HDLCD instance on the core tile (also known as the daughterboard) by looking in the root of the device tree for compatible nodes. - If there is a HDLCD on the core tile, and there is a driver for it, we exit probe and deactivate the motherboard CLCD. We do not touch the DVI mux in this case, to make sure we don't break HDLCD. - If there is a CLCD on both the motherboard and the core tile (only the CA9 has this) the core tile CLCD takes precedence and get muxed to the DVI connector. - Only if there is no working graphics on the core tile, the motherboard CLCD is probed and muxed to the DVI connector. Core tile graphics should always take precedence as it can address all memory and is also faster, however the motherboard CLCD is good to have around for diagnostics and testing. It is possible to test the motherboard CLCD by setting the status = "disabled" property on the core tile CLCD or HDLCD. Scale down the Versatile Express to 16BPP so we can support a 1024x768 display despite the bus bandwidth restrictions on this platform. (The motherboard CLCD supports slightly lower resolution.) Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Acked-by: Eric Anholt <eric@anholt.net> Tested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180502134719.8388-1-linus.walleij@linaro.org
2018-05-02 20:47:18 +07:00
#endif
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