2015-10-03 20:46:41 +07:00
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/*
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* Copyright (c) 2011-2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _NVME_H
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#define _NVME_H
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#include <linux/nvme.h>
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#include <linux/pci.h>
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#include <linux/kref.h>
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#include <linux/blk-mq.h>
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2016-09-16 19:25:07 +07:00
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#include <linux/lightnvm.h>
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2017-02-04 02:50:32 +07:00
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#include <linux/sed-opal.h>
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2015-10-03 20:46:41 +07:00
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extern unsigned char nvme_io_timeout;
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#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
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2015-11-26 15:08:36 +07:00
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extern unsigned char admin_timeout;
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#define ADMIN_TIMEOUT (admin_timeout * HZ)
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2015-11-28 21:03:49 +07:00
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extern unsigned char shutdown_timeout;
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#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
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2016-06-13 21:45:28 +07:00
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#define NVME_DEFAULT_KATO 5
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#define NVME_KATO_GRACE 10
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2015-10-29 15:57:29 +07:00
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enum {
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NVME_NS_LBA = 0,
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NVME_NS_LIGHTNVM = 1,
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};
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2015-10-03 20:46:41 +07:00
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/*
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2015-11-26 16:07:41 +07:00
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* List of workarounds for devices that required behavior not specified in
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* the standard.
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2015-10-03 20:46:41 +07:00
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*/
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2015-11-26 16:07:41 +07:00
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enum nvme_quirks {
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/*
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* Prefers I/O aligned to a stripe size specified in a vendor
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* specific Identify field.
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*/
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NVME_QUIRK_STRIPE_SIZE = (1 << 0),
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2015-10-23 04:45:06 +07:00
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/*
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* The controller doesn't handle Identify value others than 0 or 1
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* correctly.
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*/
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NVME_QUIRK_IDENTIFY_CNS = (1 << 1),
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2016-03-05 03:15:17 +07:00
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/*
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2017-04-06 00:21:13 +07:00
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* The controller deterministically returns O's on reads to
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* logical blocks that deallocate was called on.
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2016-03-05 03:15:17 +07:00
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*/
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2017-04-06 00:21:13 +07:00
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NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2),
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2016-06-15 04:22:41 +07:00
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/*
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* The controller needs a delay before starts checking the device
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* readiness, which is done by reading the NVME_CSTS_RDY bit.
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*/
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3),
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nvme: Enable autonomous power state transitions
NVMe devices can advertise multiple power states. These states can
be either "operational" (the device is fully functional but possibly
slow) or "non-operational" (the device is asleep until woken up).
Some devices can automatically enter a non-operational state when
idle for a specified amount of time and then automatically wake back
up when needed.
The hardware configuration is a table. For each state, an entry in
the table indicates the next deeper non-operational state, if any,
to autonomously transition to and the idle time required before
transitioning.
This patch teaches the driver to program APST so that each successive
non-operational state will be entered after an idle time equal to 100%
of the total latency (entry plus exit) associated with that state.
The maximum acceptable latency is controlled using dev_pm_qos
(e.g. power/pm_qos_latency_tolerance_us in sysfs); non-operational
states with total latency greater than this value will not be used.
As a special case, setting the latency tolerance to 0 will disable
APST entirely. On hardware without APST support, the sysfs file will
not be exposed.
The latency tolerance for newly-probed devices is set by the module
parameter nvme_core.default_ps_max_latency_us.
In theory, the device can expose "default" APST table, but this
doesn't seem to function correctly on my device (Samsung 950), nor
does it seem particularly useful. There is also an optional
mechanism by which a configuration can be "saved" so it will be
automatically loaded on reset. This can be configured from
userspace, but it doesn't seem useful to support in the driver.
On my laptop, enabling APST seems to save nearly 1W.
The hardware tables can be decoded in userspace with nvme-cli.
'nvme id-ctrl /dev/nvmeN' will show the power state table and
'nvme get-feature -f 0x0c -H /dev/nvme0' will show the current APST
configuration.
This feature is quirked off on a known-buggy Samsung device.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Jens Axboe <axboe@fb.com>
2017-02-08 01:08:45 +07:00
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/*
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* APST should not be used.
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*/
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NVME_QUIRK_NO_APST = (1 << 4),
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2017-04-21 03:37:55 +07:00
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/*
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* The deepest sleep state should not be used.
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*/
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NVME_QUIRK_NO_DEEPEST_PS = (1 << 5),
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2015-11-26 16:07:41 +07:00
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};
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2016-11-10 22:32:33 +07:00
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/*
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* Common request structure for NVMe passthrough. All drivers must have
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* this structure as the first member of their request-private data.
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*/
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struct nvme_request {
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struct nvme_command *cmd;
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union nvme_result result;
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2017-04-06 00:18:11 +07:00
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u8 retries;
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2017-04-20 21:02:57 +07:00
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u8 flags;
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u16 status;
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};
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enum {
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NVME_REQ_CANCELLED = (1 << 0),
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2016-11-10 22:32:33 +07:00
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};
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static inline struct nvme_request *nvme_req(struct request *req)
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{
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return blk_mq_rq_to_pdu(req);
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}
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2016-06-15 04:22:41 +07:00
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/* The below value is the specific amount of delay needed before checking
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* readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the
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* NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was
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* found empirically.
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*/
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#define NVME_QUIRK_DELAY_AMOUNT 2000
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2016-04-26 18:51:57 +07:00
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enum nvme_ctrl_state {
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NVME_CTRL_NEW,
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NVME_CTRL_LIVE,
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NVME_CTRL_RESETTING,
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2016-07-06 19:55:49 +07:00
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NVME_CTRL_RECONNECTING,
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2016-04-26 18:51:57 +07:00
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NVME_CTRL_DELETING,
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2016-05-12 21:37:14 +07:00
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NVME_CTRL_DEAD,
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2016-04-26 18:51:57 +07:00
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};
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2015-11-26 16:06:56 +07:00
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struct nvme_ctrl {
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2016-04-26 18:51:57 +07:00
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enum nvme_ctrl_state state;
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2017-02-23 03:32:36 +07:00
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bool identified;
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2016-04-26 18:51:57 +07:00
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spinlock_t lock;
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2015-11-26 16:06:56 +07:00
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const struct nvme_ctrl_ops *ops;
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2015-10-03 20:46:41 +07:00
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struct request_queue *admin_q;
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2016-06-13 21:45:26 +07:00
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struct request_queue *connect_q;
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2015-10-03 20:46:41 +07:00
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struct device *dev;
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2015-11-26 16:54:19 +07:00
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struct kref kref;
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2015-10-03 20:46:41 +07:00
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int instance;
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2015-11-28 21:39:07 +07:00
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struct blk_mq_tag_set *tagset;
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2015-10-03 20:46:41 +07:00
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struct list_head namespaces;
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2015-12-24 21:27:00 +07:00
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struct mutex namespaces_mutex;
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2015-11-28 21:39:07 +07:00
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struct device *device; /* char device */
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2015-11-28 21:40:19 +07:00
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struct list_head node;
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2016-02-24 23:15:53 +07:00
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struct ida ns_ida;
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2015-11-26 16:06:56 +07:00
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2017-02-17 19:59:39 +07:00
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struct opal_dev *opal_dev;
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2017-02-04 02:50:32 +07:00
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2015-10-03 20:46:41 +07:00
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char name[12];
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char serial[20];
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char model[40];
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char firmware_rev[8];
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2016-04-17 01:57:58 +07:00
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u16 cntlid;
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2015-11-28 21:03:49 +07:00
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u32 ctrl_config;
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u32 page_size;
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2015-10-03 20:46:41 +07:00
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u32 max_hw_sectors;
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u16 oncs;
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2016-02-18 23:57:48 +07:00
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u16 vid;
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2017-02-17 19:59:40 +07:00
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u16 oacs;
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2015-11-20 15:36:44 +07:00
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atomic_t abort_limit;
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2015-10-03 20:46:41 +07:00
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u8 event_limit;
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u8 vwc;
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2015-11-28 21:40:19 +07:00
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u32 vs;
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2016-06-13 21:45:26 +07:00
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u32 sgls;
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2016-06-13 21:45:28 +07:00
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u16 kas;
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nvme: Enable autonomous power state transitions
NVMe devices can advertise multiple power states. These states can
be either "operational" (the device is fully functional but possibly
slow) or "non-operational" (the device is asleep until woken up).
Some devices can automatically enter a non-operational state when
idle for a specified amount of time and then automatically wake back
up when needed.
The hardware configuration is a table. For each state, an entry in
the table indicates the next deeper non-operational state, if any,
to autonomously transition to and the idle time required before
transitioning.
This patch teaches the driver to program APST so that each successive
non-operational state will be entered after an idle time equal to 100%
of the total latency (entry plus exit) associated with that state.
The maximum acceptable latency is controlled using dev_pm_qos
(e.g. power/pm_qos_latency_tolerance_us in sysfs); non-operational
states with total latency greater than this value will not be used.
As a special case, setting the latency tolerance to 0 will disable
APST entirely. On hardware without APST support, the sysfs file will
not be exposed.
The latency tolerance for newly-probed devices is set by the module
parameter nvme_core.default_ps_max_latency_us.
In theory, the device can expose "default" APST table, but this
doesn't seem to function correctly on my device (Samsung 950), nor
does it seem particularly useful. There is also an optional
mechanism by which a configuration can be "saved" so it will be
automatically loaded on reset. This can be configured from
userspace, but it doesn't seem useful to support in the driver.
On my laptop, enabling APST seems to save nearly 1W.
The hardware tables can be decoded in userspace with nvme-cli.
'nvme id-ctrl /dev/nvmeN' will show the power state table and
'nvme get-feature -f 0x0c -H /dev/nvme0' will show the current APST
configuration.
This feature is quirked off on a known-buggy Samsung device.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Jens Axboe <axboe@fb.com>
2017-02-08 01:08:45 +07:00
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u8 npss;
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u8 apsta;
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2016-06-13 21:45:28 +07:00
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unsigned int kato;
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2015-11-28 21:40:19 +07:00
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bool subsystem;
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2015-11-26 16:07:41 +07:00
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unsigned long quirks;
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nvme: Enable autonomous power state transitions
NVMe devices can advertise multiple power states. These states can
be either "operational" (the device is fully functional but possibly
slow) or "non-operational" (the device is asleep until woken up).
Some devices can automatically enter a non-operational state when
idle for a specified amount of time and then automatically wake back
up when needed.
The hardware configuration is a table. For each state, an entry in
the table indicates the next deeper non-operational state, if any,
to autonomously transition to and the idle time required before
transitioning.
This patch teaches the driver to program APST so that each successive
non-operational state will be entered after an idle time equal to 100%
of the total latency (entry plus exit) associated with that state.
The maximum acceptable latency is controlled using dev_pm_qos
(e.g. power/pm_qos_latency_tolerance_us in sysfs); non-operational
states with total latency greater than this value will not be used.
As a special case, setting the latency tolerance to 0 will disable
APST entirely. On hardware without APST support, the sysfs file will
not be exposed.
The latency tolerance for newly-probed devices is set by the module
parameter nvme_core.default_ps_max_latency_us.
In theory, the device can expose "default" APST table, but this
doesn't seem to function correctly on my device (Samsung 950), nor
does it seem particularly useful. There is also an optional
mechanism by which a configuration can be "saved" so it will be
automatically loaded on reset. This can be configured from
userspace, but it doesn't seem useful to support in the driver.
On my laptop, enabling APST seems to save nearly 1W.
The hardware tables can be decoded in userspace with nvme-cli.
'nvme id-ctrl /dev/nvmeN' will show the power state table and
'nvme get-feature -f 0x0c -H /dev/nvme0' will show the current APST
configuration.
This feature is quirked off on a known-buggy Samsung device.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Jens Axboe <axboe@fb.com>
2017-02-08 01:08:45 +07:00
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struct nvme_id_power_state psd[32];
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2016-04-26 18:51:59 +07:00
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struct work_struct scan_work;
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2016-04-26 18:52:00 +07:00
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struct work_struct async_event_work;
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2016-06-13 21:45:28 +07:00
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struct delayed_work ka_work;
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2016-06-13 21:45:26 +07:00
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nvme: Enable autonomous power state transitions
NVMe devices can advertise multiple power states. These states can
be either "operational" (the device is fully functional but possibly
slow) or "non-operational" (the device is asleep until woken up).
Some devices can automatically enter a non-operational state when
idle for a specified amount of time and then automatically wake back
up when needed.
The hardware configuration is a table. For each state, an entry in
the table indicates the next deeper non-operational state, if any,
to autonomously transition to and the idle time required before
transitioning.
This patch teaches the driver to program APST so that each successive
non-operational state will be entered after an idle time equal to 100%
of the total latency (entry plus exit) associated with that state.
The maximum acceptable latency is controlled using dev_pm_qos
(e.g. power/pm_qos_latency_tolerance_us in sysfs); non-operational
states with total latency greater than this value will not be used.
As a special case, setting the latency tolerance to 0 will disable
APST entirely. On hardware without APST support, the sysfs file will
not be exposed.
The latency tolerance for newly-probed devices is set by the module
parameter nvme_core.default_ps_max_latency_us.
In theory, the device can expose "default" APST table, but this
doesn't seem to function correctly on my device (Samsung 950), nor
does it seem particularly useful. There is also an optional
mechanism by which a configuration can be "saved" so it will be
automatically loaded on reset. This can be configured from
userspace, but it doesn't seem useful to support in the driver.
On my laptop, enabling APST seems to save nearly 1W.
The hardware tables can be decoded in userspace with nvme-cli.
'nvme id-ctrl /dev/nvmeN' will show the power state table and
'nvme get-feature -f 0x0c -H /dev/nvme0' will show the current APST
configuration.
This feature is quirked off on a known-buggy Samsung device.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Sagi Grimberg <sagi@grimberg.me>
Signed-off-by: Jens Axboe <axboe@fb.com>
2017-02-08 01:08:45 +07:00
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/* Power saving configuration */
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u64 ps_max_latency_us;
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2016-06-13 21:45:26 +07:00
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/* Fabrics only */
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u16 sqsize;
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u32 ioccsz;
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u32 iorcsz;
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u16 icdoff;
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u16 maxcmd;
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struct nvmf_ctrl_options *opts;
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2015-10-03 20:46:41 +07:00
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};
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/*
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* An NVM Express namespace is equivalent to a SCSI LUN
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*/
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struct nvme_ns {
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struct list_head list;
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2015-11-26 16:06:56 +07:00
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struct nvme_ctrl *ctrl;
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2015-10-03 20:46:41 +07:00
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struct request_queue *queue;
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struct gendisk *disk;
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2016-09-16 19:25:07 +07:00
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struct nvm_dev *ndev;
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2015-10-03 20:46:41 +07:00
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struct kref kref;
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2016-02-24 23:15:53 +07:00
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int instance;
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2015-10-03 20:46:41 +07:00
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2015-12-23 00:10:45 +07:00
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u8 eui[8];
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u8 uuid[16];
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2015-10-03 20:46:41 +07:00
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unsigned ns_id;
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int lba_shift;
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u16 ms;
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bool ext;
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u8 pi_type;
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2016-02-24 23:15:54 +07:00
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unsigned long flags;
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#define NVME_NS_REMOVING 0
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2016-02-24 23:15:56 +07:00
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#define NVME_NS_DEAD 1
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2016-02-24 23:15:54 +07:00
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2015-10-03 20:46:41 +07:00
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u64 mode_select_num_blocks;
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u32 mode_select_block_len;
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};
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2015-11-26 16:06:56 +07:00
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struct nvme_ctrl_ops {
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2016-06-13 21:45:24 +07:00
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const char *name;
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2016-02-11 01:03:29 +07:00
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struct module *module;
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2017-05-20 20:14:44 +07:00
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unsigned int flags;
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#define NVME_F_FABRICS (1 << 0)
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2017-05-20 20:14:45 +07:00
|
|
|
#define NVME_F_METADATA_SUPPORTED (1 << 1)
|
2015-11-26 16:06:56 +07:00
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|
int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val);
|
2015-11-28 21:03:49 +07:00
|
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|
int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val);
|
2015-11-28 21:37:52 +07:00
|
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|
int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val);
|
2015-11-28 21:40:19 +07:00
|
|
|
int (*reset_ctrl)(struct nvme_ctrl *ctrl);
|
2015-11-26 16:54:19 +07:00
|
|
|
void (*free_ctrl)(struct nvme_ctrl *ctrl);
|
2016-04-26 18:52:00 +07:00
|
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|
void (*submit_async_event)(struct nvme_ctrl *ctrl, int aer_idx);
|
2016-06-13 21:45:24 +07:00
|
|
|
int (*delete_ctrl)(struct nvme_ctrl *ctrl);
|
|
|
|
const char *(*get_subsysnqn)(struct nvme_ctrl *ctrl);
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|
|
int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size);
|
2015-10-03 20:46:41 +07:00
|
|
|
};
|
|
|
|
|
2015-11-26 16:06:56 +07:00
|
|
|
static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl)
|
|
|
|
{
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val))
|
|
|
|
return false;
|
|
|
|
return val & NVME_CSTS_RDY;
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|
|
|
}
|
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|
2015-11-28 21:40:19 +07:00
|
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|
static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl)
|
|
|
|
{
|
|
|
|
if (!ctrl->subsystem)
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|
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|
return -ENOTTY;
|
|
|
|
return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65);
|
|
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|
}
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|
2015-10-03 20:46:41 +07:00
|
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|
static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
|
|
|
|
{
|
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|
return (sector >> (ns->lba_shift - 9));
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|
|
}
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|
2016-04-26 04:33:20 +07:00
|
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|
static inline void nvme_cleanup_cmd(struct request *req)
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|
|
{
|
2016-12-09 05:20:32 +07:00
|
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|
if (req->rq_flags & RQF_SPECIAL_PAYLOAD) {
|
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|
|
kfree(page_address(req->special_vec.bv_page) +
|
|
|
|
req->special_vec.bv_offset);
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|
}
|
2016-04-26 04:33:20 +07:00
|
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|
}
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|
2017-04-20 21:02:57 +07:00
|
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|
static inline void nvme_end_request(struct request *req, __le16 status,
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|
union nvme_result result)
|
2015-10-16 12:58:39 +07:00
|
|
|
{
|
2017-04-20 21:02:57 +07:00
|
|
|
struct nvme_request *rq = nvme_req(req);
|
2015-10-16 12:58:39 +07:00
|
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|
|
2017-04-20 21:02:57 +07:00
|
|
|
rq->status = le16_to_cpu(status) >> 1;
|
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|
|
rq->result = result;
|
2017-04-20 21:03:09 +07:00
|
|
|
blk_mq_complete_request(req);
|
2015-11-28 21:41:58 +07:00
|
|
|
}
|
|
|
|
|
2017-03-30 18:41:32 +07:00
|
|
|
void nvme_complete_rq(struct request *req);
|
2016-05-19 04:05:02 +07:00
|
|
|
void nvme_cancel_request(struct request *req, void *data, bool reserved);
|
2016-04-26 18:51:57 +07:00
|
|
|
bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
|
|
|
|
enum nvme_ctrl_state new_state);
|
2015-11-28 21:03:49 +07:00
|
|
|
int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
|
|
|
|
int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap);
|
|
|
|
int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl);
|
2015-11-28 21:40:19 +07:00
|
|
|
int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
|
|
|
|
const struct nvme_ctrl_ops *ops, unsigned long quirks);
|
2015-11-28 21:41:02 +07:00
|
|
|
void nvme_uninit_ctrl(struct nvme_ctrl *ctrl);
|
2015-11-26 16:54:19 +07:00
|
|
|
void nvme_put_ctrl(struct nvme_ctrl *ctrl);
|
2015-11-28 21:37:52 +07:00
|
|
|
int nvme_init_identify(struct nvme_ctrl *ctrl);
|
2015-11-28 21:39:07 +07:00
|
|
|
|
2016-04-26 18:51:59 +07:00
|
|
|
void nvme_queue_scan(struct nvme_ctrl *ctrl);
|
2015-11-28 21:39:07 +07:00
|
|
|
void nvme_remove_namespaces(struct nvme_ctrl *ctrl);
|
2015-11-26 16:54:19 +07:00
|
|
|
|
2017-02-17 19:59:39 +07:00
|
|
|
int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
|
|
|
|
bool send);
|
2017-02-04 02:50:32 +07:00
|
|
|
|
2016-04-26 18:52:00 +07:00
|
|
|
#define NVME_NR_AERS 1
|
2016-11-10 22:32:34 +07:00
|
|
|
void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
|
|
|
|
union nvme_result *res);
|
2016-04-26 18:52:00 +07:00
|
|
|
void nvme_queue_async_events(struct nvme_ctrl *ctrl);
|
|
|
|
|
2016-01-04 23:10:57 +07:00
|
|
|
void nvme_stop_queues(struct nvme_ctrl *ctrl);
|
|
|
|
void nvme_start_queues(struct nvme_ctrl *ctrl);
|
2016-02-24 23:15:56 +07:00
|
|
|
void nvme_kill_queues(struct nvme_ctrl *ctrl);
|
2017-03-02 02:22:12 +07:00
|
|
|
void nvme_unfreeze(struct nvme_ctrl *ctrl);
|
|
|
|
void nvme_wait_freeze(struct nvme_ctrl *ctrl);
|
|
|
|
void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout);
|
|
|
|
void nvme_start_freeze(struct nvme_ctrl *ctrl);
|
2015-12-24 21:26:59 +07:00
|
|
|
|
2016-06-13 21:45:23 +07:00
|
|
|
#define NVME_QID_ANY -1
|
2015-11-20 15:00:02 +07:00
|
|
|
struct request *nvme_alloc_request(struct request_queue *q,
|
2016-06-13 21:45:23 +07:00
|
|
|
struct nvme_command *cmd, unsigned int flags, int qid);
|
2016-04-13 02:10:14 +07:00
|
|
|
int nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
|
|
|
|
struct nvme_command *cmd);
|
2015-10-03 20:46:41 +07:00
|
|
|
int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
|
|
|
|
void *buf, unsigned bufflen);
|
|
|
|
int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
|
2016-11-10 22:32:33 +07:00
|
|
|
union nvme_result *result, void *buffer, unsigned bufflen,
|
2016-06-13 21:45:23 +07:00
|
|
|
unsigned timeout, int qid, int at_head, int flags);
|
2015-11-20 15:00:02 +07:00
|
|
|
int nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
|
|
|
|
void __user *ubuffer, unsigned bufflen, u32 *result,
|
|
|
|
unsigned timeout);
|
2015-10-23 22:47:28 +07:00
|
|
|
int __nvme_submit_user_cmd(struct request_queue *q, struct nvme_command *cmd,
|
|
|
|
void __user *ubuffer, unsigned bufflen,
|
|
|
|
void __user *meta_buffer, unsigned meta_len, u32 meta_seed,
|
2015-10-03 20:46:41 +07:00
|
|
|
u32 *result, unsigned timeout);
|
2015-11-26 16:06:56 +07:00
|
|
|
int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id);
|
|
|
|
int nvme_identify_ns(struct nvme_ctrl *dev, unsigned nsid,
|
2015-10-03 20:46:41 +07:00
|
|
|
struct nvme_id_ns **id);
|
2015-11-26 16:06:56 +07:00
|
|
|
int nvme_get_log_page(struct nvme_ctrl *dev, struct nvme_smart_log **log);
|
|
|
|
int nvme_get_features(struct nvme_ctrl *dev, unsigned fid, unsigned nsid,
|
2016-09-17 01:16:10 +07:00
|
|
|
void *buffer, size_t buflen, u32 *result);
|
2015-11-26 16:06:56 +07:00
|
|
|
int nvme_set_features(struct nvme_ctrl *dev, unsigned fid, unsigned dword11,
|
2016-09-17 01:16:10 +07:00
|
|
|
void *buffer, size_t buflen, u32 *result);
|
2015-11-26 17:09:06 +07:00
|
|
|
int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count);
|
2016-06-13 21:45:28 +07:00
|
|
|
void nvme_start_keep_alive(struct nvme_ctrl *ctrl);
|
|
|
|
void nvme_stop_keep_alive(struct nvme_ctrl *ctrl);
|
2015-10-03 20:46:41 +07:00
|
|
|
|
|
|
|
struct sg_io_hdr;
|
|
|
|
|
|
|
|
int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
|
|
|
|
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
|
|
|
|
int nvme_sg_get_version_num(int __user *ip);
|
|
|
|
|
2015-11-28 22:49:22 +07:00
|
|
|
#ifdef CONFIG_NVM
|
2015-10-29 15:57:29 +07:00
|
|
|
int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id);
|
2016-11-29 04:38:53 +07:00
|
|
|
int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node);
|
2016-09-16 19:25:07 +07:00
|
|
|
void nvme_nvm_unregister(struct nvme_ns *ns);
|
2016-11-29 04:38:53 +07:00
|
|
|
int nvme_nvm_register_sysfs(struct nvme_ns *ns);
|
|
|
|
void nvme_nvm_unregister_sysfs(struct nvme_ns *ns);
|
2017-01-31 19:17:16 +07:00
|
|
|
int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg);
|
2015-11-28 22:49:22 +07:00
|
|
|
#else
|
2016-09-16 19:25:07 +07:00
|
|
|
static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name,
|
2016-11-29 04:38:53 +07:00
|
|
|
int node)
|
2015-11-28 22:49:22 +07:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-09-16 19:25:07 +07:00
|
|
|
static inline void nvme_nvm_unregister(struct nvme_ns *ns) {};
|
2016-11-29 04:38:53 +07:00
|
|
|
static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {};
|
2015-11-28 22:49:22 +07:00
|
|
|
static inline int nvme_nvm_ns_supported(struct nvme_ns *ns, struct nvme_id_ns *id)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2017-01-31 19:17:16 +07:00
|
|
|
static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd,
|
|
|
|
unsigned long arg)
|
|
|
|
{
|
|
|
|
return -ENOTTY;
|
|
|
|
}
|
2016-11-29 04:38:53 +07:00
|
|
|
#endif /* CONFIG_NVM */
|
|
|
|
|
2016-09-16 19:25:08 +07:00
|
|
|
static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev)
|
|
|
|
{
|
|
|
|
return dev_to_disk(dev)->private_data;
|
|
|
|
}
|
2015-10-29 15:57:29 +07:00
|
|
|
|
2015-11-28 21:39:07 +07:00
|
|
|
int __init nvme_core_init(void);
|
|
|
|
void nvme_core_exit(void);
|
|
|
|
|
2015-10-03 20:46:41 +07:00
|
|
|
#endif /* _NVME_H */
|