2019-05-29 21:17:56 +07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2010-05-25 07:07:46 +07:00
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/*
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* Copyright (c) 2010 Google, Inc
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2014-07-11 18:19:06 +07:00
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* Copyright (c) 2014 NVIDIA Corporation
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2010-05-25 07:07:46 +07:00
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*/
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2014-07-11 18:19:06 +07:00
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#ifndef __SOC_TEGRA_PMC_H__
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#define __SOC_TEGRA_PMC_H__
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#include <linux/reboot.h>
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#include <soc/tegra/pm.h>
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2010-05-25 07:07:46 +07:00
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2012-10-05 02:50:56 +07:00
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struct clk;
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2013-11-07 05:45:46 +07:00
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struct reset_control;
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2012-10-05 02:50:56 +07:00
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2016-02-12 01:03:22 +07:00
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bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
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int tegra_pmc_cpu_power_on(unsigned int cpuid);
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int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
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2014-07-11 18:19:06 +07:00
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/*
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* powergate and I/O rail APIs
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*/
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2010-05-25 07:07:46 +07:00
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#define TEGRA_POWERGATE_CPU 0
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#define TEGRA_POWERGATE_3D 1
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#define TEGRA_POWERGATE_VENC 2
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#define TEGRA_POWERGATE_PCIE 3
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#define TEGRA_POWERGATE_VDEC 4
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#define TEGRA_POWERGATE_L2 5
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#define TEGRA_POWERGATE_MPE 6
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2012-02-10 06:47:48 +07:00
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#define TEGRA_POWERGATE_HEG 7
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#define TEGRA_POWERGATE_SATA 8
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#define TEGRA_POWERGATE_CPU1 9
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#define TEGRA_POWERGATE_CPU2 10
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#define TEGRA_POWERGATE_CPU3 11
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#define TEGRA_POWERGATE_CELP 12
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#define TEGRA_POWERGATE_3D1 13
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2013-10-17 00:19:02 +07:00
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#define TEGRA_POWERGATE_CPU0 14
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#define TEGRA_POWERGATE_C0NC 15
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#define TEGRA_POWERGATE_C1NC 16
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2013-12-13 23:31:03 +07:00
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#define TEGRA_POWERGATE_SOR 17
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2013-10-17 00:19:02 +07:00
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#define TEGRA_POWERGATE_DIS 18
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#define TEGRA_POWERGATE_DISB 19
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#define TEGRA_POWERGATE_XUSBA 20
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#define TEGRA_POWERGATE_XUSBB 21
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#define TEGRA_POWERGATE_XUSBC 22
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2013-12-13 23:31:03 +07:00
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#define TEGRA_POWERGATE_VIC 23
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#define TEGRA_POWERGATE_IRAM 24
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2015-03-23 17:31:29 +07:00
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#define TEGRA_POWERGATE_NVDEC 25
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#define TEGRA_POWERGATE_NVJPG 26
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#define TEGRA_POWERGATE_AUD 27
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#define TEGRA_POWERGATE_DFD 28
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#define TEGRA_POWERGATE_VE2 29
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2016-03-30 16:15:15 +07:00
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#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
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2012-02-10 06:47:48 +07:00
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#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
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2010-05-25 07:07:46 +07:00
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2016-10-10 20:14:34 +07:00
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/**
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* enum tegra_io_pad - I/O pad group identifier
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*
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* I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
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* can be used to control the common voltage signal level and power state of
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* the pins of the given pad.
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*/
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enum tegra_io_pad {
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TEGRA_IO_PAD_AUDIO,
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TEGRA_IO_PAD_AUDIO_HV,
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TEGRA_IO_PAD_BB,
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TEGRA_IO_PAD_CAM,
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TEGRA_IO_PAD_COMP,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_CONN,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_CSIA,
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TEGRA_IO_PAD_CSIB,
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TEGRA_IO_PAD_CSIC,
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TEGRA_IO_PAD_CSID,
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TEGRA_IO_PAD_CSIE,
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TEGRA_IO_PAD_CSIF,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_CSIG,
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TEGRA_IO_PAD_CSIH,
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TEGRA_IO_PAD_DAP3,
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TEGRA_IO_PAD_DAP5,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_DBG,
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TEGRA_IO_PAD_DEBUG_NONAO,
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TEGRA_IO_PAD_DMIC,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_DMIC_HV,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_DP,
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TEGRA_IO_PAD_DSI,
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TEGRA_IO_PAD_DSIB,
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TEGRA_IO_PAD_DSIC,
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TEGRA_IO_PAD_DSID,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_EDP,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_EMMC,
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TEGRA_IO_PAD_EMMC2,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_EQOS,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_GPIO,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_GP_PWM2,
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TEGRA_IO_PAD_GP_PWM3,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_HDMI,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_HDMI_DP0,
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TEGRA_IO_PAD_HDMI_DP1,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_HDMI_DP2,
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TEGRA_IO_PAD_HDMI_DP3,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_HSIC,
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TEGRA_IO_PAD_HV,
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TEGRA_IO_PAD_LVDS,
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TEGRA_IO_PAD_MIPI_BIAS,
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TEGRA_IO_PAD_NAND,
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TEGRA_IO_PAD_PEX_BIAS,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_PEX_CLK_BIAS,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_PEX_CLK1,
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TEGRA_IO_PAD_PEX_CLK2,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_PEX_CLK3,
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2020-03-10 17:43:56 +07:00
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TEGRA_IO_PAD_PEX_CLK_2_BIAS,
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TEGRA_IO_PAD_PEX_CLK_2,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_PEX_CNTRL,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_PEX_CTL2,
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TEGRA_IO_PAD_PEX_L0_RST_N,
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TEGRA_IO_PAD_PEX_L1_RST_N,
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TEGRA_IO_PAD_PEX_L5_RST_N,
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TEGRA_IO_PAD_PWR_CTL,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_SDMMC1,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_SDMMC1_HV,
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TEGRA_IO_PAD_SDMMC2,
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TEGRA_IO_PAD_SDMMC2_HV,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_SDMMC3,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_SDMMC3_HV,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_SDMMC4,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_SOC_GPIO10,
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TEGRA_IO_PAD_SOC_GPIO12,
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TEGRA_IO_PAD_SOC_GPIO13,
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TEGRA_IO_PAD_SOC_GPIO53,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_SPI,
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TEGRA_IO_PAD_SPI_HV,
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TEGRA_IO_PAD_SYS_DDC,
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TEGRA_IO_PAD_UART,
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2018-01-25 19:43:45 +07:00
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TEGRA_IO_PAD_UART4,
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TEGRA_IO_PAD_UART5,
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2017-08-30 17:42:34 +07:00
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TEGRA_IO_PAD_UFS,
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2016-10-10 20:14:34 +07:00
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TEGRA_IO_PAD_USB0,
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TEGRA_IO_PAD_USB1,
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TEGRA_IO_PAD_USB2,
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TEGRA_IO_PAD_USB3,
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TEGRA_IO_PAD_USB_BIAS,
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2018-08-11 01:08:07 +07:00
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TEGRA_IO_PAD_AO_HV,
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2016-10-10 20:14:34 +07:00
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};
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/* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
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#define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
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#define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
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2017-03-20 16:13:06 +07:00
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#ifdef CONFIG_SOC_TEGRA_PMC
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2016-02-12 01:03:22 +07:00
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int tegra_powergate_power_on(unsigned int id);
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int tegra_powergate_power_off(unsigned int id);
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int tegra_powergate_remove_clamping(unsigned int id);
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2010-05-25 07:07:46 +07:00
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/* Must be called with clk disabled, and returns with clk enabled */
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2016-02-12 01:03:22 +07:00
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int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
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2013-11-07 05:45:46 +07:00
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struct reset_control *rst);
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2013-12-17 03:42:28 +07:00
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2016-10-10 20:14:34 +07:00
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int tegra_io_pad_power_enable(enum tegra_io_pad id);
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int tegra_io_pad_power_disable(enum tegra_io_pad id);
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/* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
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2016-02-12 01:03:22 +07:00
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int tegra_io_rail_power_on(unsigned int id);
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int tegra_io_rail_power_off(unsigned int id);
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2017-03-20 16:13:06 +07:00
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
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void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
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void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
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2013-11-26 01:49:47 +07:00
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#else
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2016-02-12 01:03:22 +07:00
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static inline int tegra_powergate_power_on(unsigned int id)
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2013-11-26 01:49:47 +07:00
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{
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return -ENOSYS;
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}
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2016-02-12 01:03:22 +07:00
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static inline int tegra_powergate_power_off(unsigned int id)
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2013-11-26 01:49:47 +07:00
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{
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return -ENOSYS;
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}
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2016-02-12 01:03:22 +07:00
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static inline int tegra_powergate_remove_clamping(unsigned int id)
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2013-11-26 01:49:47 +07:00
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{
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return -ENOSYS;
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}
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2016-02-12 01:03:22 +07:00
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static inline int tegra_powergate_sequence_power_up(unsigned int id,
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struct clk *clk,
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2014-01-14 05:01:42 +07:00
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struct reset_control *rst)
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2013-11-26 01:49:47 +07:00
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{
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return -ENOSYS;
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}
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2013-12-17 03:42:28 +07:00
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2016-10-10 20:14:34 +07:00
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static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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2016-02-12 01:03:22 +07:00
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static inline int tegra_io_rail_power_on(unsigned int id)
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2013-12-17 03:42:28 +07:00
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{
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return -ENOSYS;
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}
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2016-02-12 01:03:22 +07:00
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static inline int tegra_io_rail_power_off(unsigned int id)
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2013-12-17 03:42:28 +07:00
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{
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return -ENOSYS;
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}
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2017-03-20 16:13:06 +07:00
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static inline enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
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{
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return TEGRA_SUSPEND_NONE;
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}
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static inline void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
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{
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}
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static inline void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
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{
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}
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#endif /* CONFIG_SOC_TEGRA_PMC */
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2010-05-25 07:07:46 +07:00
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2014-07-11 18:19:06 +07:00
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#endif /* __SOC_TEGRA_PMC_H__ */
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