linux_dsm_epyc7002/arch/arm/include/asm/hardware/cache-tauros2.h

/*
 * arch/arm/include/asm/hardware/cache-tauros2.h
 *
 * Copyright (C) 2008 Marvell Semiconductor
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#define CACHE_TAUROS2_PREFETCH_ON	(1 << 0)
#define CACHE_TAUROS2_LINEFILL_BURST8	(1 << 1)

extern void __init tauros2_init(unsigned int features);
ARM: Add Tauros2 L2 cache controller support Support for the Tauros2 L2 cache controller as used with the PJ1 and PJ4 CPUs. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com> 2009-11-25 00:33:52 +07:00			`/*`
			`* arch/arm/include/asm/hardware/cache-tauros2.h`
			`*`
			`* Copyright (C) 2008 Marvell Semiconductor`
			`*`
			`* This file is licensed under the terms of the GNU General Public`
			`* License version 2. This program is licensed "as is" without any`
			`* warranty of any kind, whether express or implied.`
			`*/`

ARM: cache: add extra feature enable for tauros2 The extra feature may be used by SOCs are prefetch, burst8, write buffer coalesce Signed-off-by: Chao Xie <xiechao.mail@gmail.com> Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> 2012-07-31 13:13:12 +07:00			`#define CACHE_TAUROS2_PREFETCH_ON (1 << 0)`
			`#define CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)`

			`extern void __init tauros2_init(unsigned int features);`