2005-11-19 16:17:32 +07:00
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#ifndef _ASM_POWERPC_PGTABLE_H
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|
#define _ASM_POWERPC_PGTABLE_H
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2005-12-17 04:43:46 +07:00
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#ifdef __KERNEL__
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2005-11-19 16:17:32 +07:00
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|
2007-06-13 11:52:56 +07:00
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#ifndef __ASSEMBLY__
|
2013-11-18 16:28:13 +07:00
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#include <linux/mmdebug.h>
|
2014-08-09 06:40:42 +07:00
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#include <linux/mmzone.h>
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2007-06-13 11:52:56 +07:00
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#include <asm/processor.h> /* For TASK_SIZE */
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#include <asm/mmu.h>
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#include <asm/page.h>
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
|
2007-06-13 11:52:56 +07:00
|
|
|
struct mm_struct;
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
|
2007-06-13 11:52:56 +07:00
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|
#endif /* !__ASSEMBLY__ */
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|
2007-04-30 13:30:56 +07:00
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#if defined(CONFIG_PPC64)
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# include <asm/pgtable-ppc64.h>
|
2005-11-19 16:17:32 +07:00
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#else
|
2007-04-30 13:30:56 +07:00
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# include <asm/pgtable-ppc32.h>
|
2005-08-05 16:39:06 +07:00
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#endif
|
2005-04-17 05:20:36 +07:00
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|
2013-04-28 16:37:27 +07:00
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/*
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* We save the slot number & secondary bit in the second half of the
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* PTE page. We use the 8 bytes per each pte entry.
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*/
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#define PTE_PAGE_HIDX_OFFSET (PTRS_PER_PTE * 8)
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|
2005-04-17 05:20:36 +07:00
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|
#ifndef __ASSEMBLY__
|
2008-12-19 02:13:51 +07:00
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2012-09-10 09:52:57 +07:00
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#include <asm/tlbflush.h>
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2009-03-20 02:34:09 +07:00
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/* Generic accessors to PTE bits */
|
2015-01-19 23:04:38 +07:00
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static inline int pte_write(pte_t pte)
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{ return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; }
|
2009-03-20 02:34:09 +07:00
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
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|
2013-11-18 16:28:13 +07:00
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#ifdef CONFIG_NUMA_BALANCING
|
2015-02-13 05:58:19 +07:00
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/*
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* These work without NUMA balancing but the kernel does not care. See the
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* comment in include/asm-generic/pgtable.h . On powerpc, this will only
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* work for user pages and always return true for kernel pages.
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*/
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static inline int pte_protnone(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
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}
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static inline int pmd_protnone(pmd_t pmd)
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{
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return pte_protnone(pmd_pte(pmd));
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}
|
2015-02-13 05:58:32 +07:00
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#endif /* CONFIG_NUMA_BALANCING */
|
2013-11-18 16:28:13 +07:00
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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2009-03-20 02:34:09 +07:00
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot)); }
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static inline unsigned long pte_pfn(pte_t pte) {
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return pte_val(pte) >> PTE_RPN_SHIFT; }
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/* Keep these as a macros to avoid include dependency mess */
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_wrprotect(pte_t pte) {
|
2015-01-19 23:04:38 +07:00
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pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE);
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pte_val(pte) |= _PAGE_RO; return pte; }
|
2009-03-20 02:34:09 +07:00
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static inline pte_t pte_mkclean(pte_t pte) {
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pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
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static inline pte_t pte_mkold(pte_t pte) {
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pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite(pte_t pte) {
|
2015-01-19 23:04:38 +07:00
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pte_val(pte) &= ~_PAGE_RO;
|
2009-03-20 02:34:09 +07:00
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pte_val(pte) |= _PAGE_RW; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte) {
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pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte) {
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pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkspecial(pte_t pte) {
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pte_val(pte) |= _PAGE_SPECIAL; return pte; }
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static inline pte_t pte_mkhuge(pte_t pte) {
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return pte; }
|
|
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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|
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|
|
{
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pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
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return pte;
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}
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|
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|
|
|
|
|
|
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
/* Insert a PTE, top-level function is out of line. It uses an inline
|
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|
* low level function in the respective pgtable-* files
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*/
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|
extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte);
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
|
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* an horrible mess that I'm not going to try to clean up now but
|
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
|
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|
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{
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|
#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
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/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
|
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* helper pte_update() which does an atomic update. We need to do that
|
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|
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* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
|
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|
|
|
* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
|
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|
* the hash bits instead (ie, same as the non-SMP case)
|
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*/
|
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|
|
if (percpu)
|
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|
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|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
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|
else
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pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
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|
2009-08-17 11:36:32 +07:00
|
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|
#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
|
|
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|
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/* Second case is 32-bit with 64-bit PTE. In this case, we
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
* can just store as long as we do the two halves in the right order
|
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* with a barrier in between. This is possible because we take care,
|
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* in the hash code, to pre-invalidate if the PTE was already hashed,
|
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|
* which synchronizes us with any concurrent invalidation.
|
|
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|
* In the percpu case, we also fallback to the simple update preserving
|
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* the hash bits
|
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*/
|
|
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|
|
if (percpu) {
|
|
|
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
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|
return;
|
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|
|
}
|
|
|
|
|
#if _PAGE_HASHPTE != 0
|
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|
|
if (pte_val(*ptep) & _PAGE_HASHPTE)
|
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|
flush_hash_entry(mm, ptep, addr);
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|
|
#endif
|
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|
|
__asm__ __volatile__("\
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|
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|
|
stw%U0%X0 %2,%0\n\
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|
|
eieio\n\
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|
stw%U0%X0 %L2,%1"
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|
: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
|
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|
: "r" (pte) : "memory");
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|
#elif defined(CONFIG_PPC_STD_MMU_32)
|
|
|
|
|
/* Third case is 32-bit hash table in UP mode, we need to preserve
|
|
|
|
|
* the _PAGE_HASHPTE bit since we may not have invalidated the previous
|
|
|
|
|
* translation in the hash yet (done in a subsequent flush_tlb_xxx())
|
|
|
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|
* and see we need to keep track that this PTE needs invalidating
|
|
|
|
|
*/
|
|
|
|
|
*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
|
|
|
|
|
| (pte_val(pte) & ~_PAGE_HASHPTE));
|
|
|
|
|
|
|
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|
#else
|
|
|
|
|
/* Anything else just stores the PTE normally. That covers all 64-bit
|
2009-08-17 11:36:32 +07:00
|
|
|
* cases, and 32-bit non-hash with 32-bit PTEs.
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
*/
|
|
|
|
|
*ptep = pte;
|
2015-07-19 02:24:57 +07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3E_64
|
|
|
|
|
/*
|
|
|
|
|
* With hardware tablewalk, a sync is needed to ensure that
|
|
|
|
|
* subsequent accesses see the PTE we just wrote. Unlike userspace
|
|
|
|
|
* mappings, we can't tolerate spurious faults, so make sure
|
|
|
|
|
* the new PTE will be seen the first time.
|
|
|
|
|
*/
|
|
|
|
|
if (is_kernel_addr(addr))
|
|
|
|
|
mb();
|
|
|
|
|
#endif
|
powerpc/mm: Rework I$/D$ coherency (v3)
This patch reworks the way we do I and D cache coherency on PowerPC.
The "old" way was split in 3 different parts depending on the processor type:
- Hash with per-page exec support (64-bit and >= POWER4 only) does it
at hashing time, by preventing exec on unclean pages and cleaning pages
on exec faults.
- Everything without per-page exec support (32-bit hash, 8xx, and
64-bit < POWER4) does it for all page going to user space in update_mmu_cache().
- Embedded with per-page exec support does it from do_page_fault() on
exec faults, in a way similar to what the hash code does.
That leads to confusion, and bugs. For example, the method using update_mmu_cache()
is racy on SMP where another processor can see the new PTE and hash it in before
we have cleaned the cache, and then blow trying to execute. This is hard to hit but
I think it has bitten us in the past.
Also, it's inefficient for embedded where we always end up having to do at least
one more page fault.
This reworks the whole thing by moving the cache sync into two main call sites,
though we keep different behaviours depending on the HW capability. The call
sites are set_pte_at() which is now made out of line, and ptep_set_access_flags()
which joins the former in pgtable.c
The base idea for Embedded with per-page exec support, is that we now do the
flush at set_pte_at() time when coming from an exec fault, which allows us
to avoid the double fault problem completely (we can even improve the situation
more by implementing TLB preload in update_mmu_cache() but that's for later).
If for some reason we didn't do it there and we try to execute, we'll hit
the page fault, which will do a minor fault, which will hit ptep_set_access_flags()
to do things like update _PAGE_ACCESSED or _PAGE_DIRTY if needed, we just make
this guys also perform the I/D cache sync for exec faults now. This second path
is the catch all for things that weren't cleaned at set_pte_at() time.
For cpus without per-pag exec support, we always do the sync at set_pte_at(),
thus guaranteeing that when the PTE is visible to other processors, the cache
is clean.
For the 64-bit hash with per-page exec support case, we keep the old mechanism
for now. I'll look into changing it later, once I've reworked a bit how we
use _PAGE_EXEC.
This is also a first step for adding _PAGE_EXEC support for embedded platforms
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2009-02-10 23:02:37 +07:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
|
|
|
|
|
extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
|
|
|
|
|
pte_t *ptep, pte_t entry, int dirty);
|
|
|
|
|
|
2008-12-19 02:13:51 +07:00
|
|
|
/*
|
|
|
|
|
* Macro to mark a page protection value as "uncacheable".
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
|
|
|
|
|
_PAGE_WRITETHRU)
|
|
|
|
|
|
|
|
|
|
#define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
|
|
|
|
|
_PAGE_NO_CACHE | _PAGE_GUARDED))
|
|
|
|
|
|
|
|
|
|
#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
|
|
|
|
|
_PAGE_NO_CACHE))
|
|
|
|
|
|
|
|
|
|
#define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
|
|
|
|
|
_PAGE_COHERENT))
|
|
|
|
|
|
|
|
|
|
#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
|
|
|
|
|
_PAGE_COHERENT | _PAGE_WRITETHRU))
|
|
|
|
|
|
2011-10-27 09:58:45 +07:00
|
|
|
#define pgprot_cached_noncoherent(prot) \
|
|
|
|
|
(__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
|
|
|
|
|
|
2011-03-01 03:00:47 +07:00
|
|
|
#define pgprot_writecombine pgprot_noncached_wc
|
2008-12-19 02:13:51 +07:00
|
|
|
|
|
|
|
|
struct file;
|
|
|
|
|
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
|
|
|
|
|
unsigned long size, pgprot_t vma_prot);
|
|
|
|
|
#define __HAVE_PHYS_MEM_ACCESS_PROT
|
|
|
|
|
|
2007-06-13 11:52:56 +07:00
|
|
|
/*
|
|
|
|
|
* ZERO_PAGE is a global shared page that is always zero: used
|
|
|
|
|
* for zero-mapped memory areas etc..
|
|
|
|
|
*/
|
|
|
|
|
extern unsigned long empty_zero_page[];
|
|
|
|
|
#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
|
|
|
|
|
|
|
|
|
|
extern pgd_t swapper_pg_dir[];
|
|
|
|
|
|
2014-08-09 06:40:42 +07:00
|
|
|
void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
|
|
|
|
|
int dma_pfn_limit_to_zone(u64 pfn_limit);
|
2007-06-13 11:52:56 +07:00
|
|
|
extern void paging_init(void);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* kern_addr_valid is intended to indicate whether an address is a valid
|
|
|
|
|
* kernel address. Most 32-bit archs define it as always true (like this)
|
|
|
|
|
* but most 64-bit archs actually perform a test. What should we do here?
|
|
|
|
|
*/
|
|
|
|
|
#define kern_addr_valid(addr) (1)
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
#include <asm-generic/pgtable.h>
|
2008-07-25 13:21:11 +07:00
|
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This gets called at the end of handling a page fault, when
|
|
|
|
|
* the kernel has put a new PTE into the page table for the process.
|
|
|
|
|
* We use it to ensure coherency between the i-cache and d-cache
|
|
|
|
|
* for the page which has just been mapped in.
|
|
|
|
|
* On machines which use an MMU hash table, we use this to put a
|
|
|
|
|
* corresponding HPTE into the hash table ahead of time, instead of
|
|
|
|
|
* waiting for the inevitable extra hash-table miss exception.
|
|
|
|
|
*/
|
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself
On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies. We do this via make_coherent() by making the pages
uncacheable.
This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().
Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():
On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
to construct a pointer to the pte again. Passing a pte_t * is much
more elegant. Maybe we might even replace the pte argument with the
pte_t?
Ben Herrenschmidt would also like the pte pointer for PowerPC:
Passing the ptep in there is exactly what I want. I want that
-instead- of the PTE value, because I have issue on some ppc cases,
for I$/D$ coherency, where set_pte_at() may decide to mask out the
_PAGE_EXEC.
So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.
Includes a fix from Stephen Rothwell:
sparc: fix fallout from update_mmu_cache API change
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-12-18 23:40:18 +07:00
|
|
|
extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
|
2008-07-25 13:21:11 +07:00
|
|
|
|
2013-04-28 16:37:30 +07:00
|
|
|
extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
|
2014-11-05 23:27:41 +07:00
|
|
|
unsigned long end, int write,
|
|
|
|
|
struct page **pages, int *nr);
|
2013-06-20 16:00:15 +07:00
|
|
|
#ifndef CONFIG_TRANSPARENT_HUGEPAGE
|
|
|
|
|
#define pmd_large(pmd) 0
|
|
|
|
|
#define has_transparent_hugepage() 0
|
|
|
|
|
#endif
|
2015-03-30 12:11:03 +07:00
|
|
|
pte_t *__find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
|
2015-10-09 10:02:21 +07:00
|
|
|
bool *is_thp, unsigned *shift);
|
2015-03-30 12:11:03 +07:00
|
|
|
static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
|
2015-10-09 10:02:21 +07:00
|
|
|
bool *is_thp, unsigned *shift)
|
2015-03-30 12:11:03 +07:00
|
|
|
{
|
|
|
|
|
if (!arch_irqs_disabled()) {
|
|
|
|
|
pr_info("%s called with irq enabled\n", __func__);
|
|
|
|
|
dump_stack();
|
|
|
|
|
}
|
2015-10-09 10:02:21 +07:00
|
|
|
return __find_linux_pte_or_hugepte(pgdir, ea, is_thp, shift);
|
2015-03-30 12:11:03 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
|
|
2005-12-17 04:43:46 +07:00
|
|
|
#endif /* __KERNEL__ */
|
2005-11-19 16:17:32 +07:00
|
|
|
#endif /* _ASM_POWERPC_PGTABLE_H */
|