2018-09-28 00:03:47 +07:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2014-05-09 03:49:10 +07:00
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/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* Device Tree binding constants clock controllers of Samsung S3C2410 and later.
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*/
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#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
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#define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H
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/*
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* Let each exported clock get a unique index, which is used on DT-enabled
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* platforms to lookup the clock from a clock specifier. These indices are
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* therefore considered an ABI and so must not be changed. This implies
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* that new clocks should be added either in free spaces between clock groups
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* or at the end.
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*/
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/* Core clocks. */
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/* id 1 is reserved */
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#define MPLL 2
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#define UPLL 3
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#define FCLK 4
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#define HCLK 5
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#define PCLK 6
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#define UCLK 7
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#define ARMCLK 8
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/* pclk-gates */
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#define PCLK_UART0 16
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#define PCLK_UART1 17
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#define PCLK_UART2 18
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#define PCLK_I2C 19
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#define PCLK_SDI 20
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#define PCLK_SPI 21
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#define PCLK_ADC 22
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#define PCLK_AC97 23
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#define PCLK_I2S 24
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#define PCLK_PWM 25
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#define PCLK_RTC 26
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#define PCLK_GPIO 27
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/* hclk-gates */
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#define HCLK_LCD 32
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#define HCLK_USBH 33
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#define HCLK_USBD 34
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#define HCLK_NAND 35
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#define HCLK_CAM 36
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#define CAMIF 40
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/* Total number of clocks. */
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#define NR_CLKS (CAMIF + 1)
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#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */
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