linux_dsm_epyc7002/drivers/gpu/drm/sun4i/sun8i_vi_layer.c

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/*
* Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>
#include <drm/drm_gem_framebuffer_helper.h>
#include <drm/drm_plane_helper.h>
drm: Split out drm_probe_helper.h Having the probe helper stuff (which pretty much everyone needs) in the drm_crtc_helper.h file (which atomic drivers should never need) is confusing. Split them out. To make sure I actually achieved the goal here I went through all drivers. And indeed, all atomic drivers are now free of drm_crtc_helper.h includes. v2: Make it compile. There was so much compile fail on arm drivers that I figured I'll better not include any of the acks on v1. v3: Massive rebase because i915 has lost a lot of drmP.h includes, but not all: Through drm_crtc_helper.h > drm_modeset_helper.h -> drmP.h there was still one, which this patch largely removes. Which means rolling out lots more includes all over. This will also conflict with ongoing drmP.h cleanup by others I expect. v3: Rebase on top of atomic bochs. v4: Review from Laurent for bridge/rcar/omap/shmob/core bits: - (re)move some of the added includes, use the better include files in other places (all suggested from Laurent adopted unchanged). - sort alphabetically v5: Actually try to sort them, and while at it, sort all the ones I touch. v6: Rebase onto i915 changes. v7: Rebase once more. Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com> Acked-by: CK Hu <ck.hu@mediatek.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: virtualization@lists.linux-foundation.org Cc: etnaviv@lists.freedesktop.org Cc: linux-samsung-soc@vger.kernel.org Cc: intel-gfx@lists.freedesktop.org Cc: linux-mediatek@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: spice-devel@lists.freedesktop.org Cc: amd-gfx@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-tegra@vger.kernel.org Cc: xen-devel@lists.xen.org Link: https://patchwork.freedesktop.org/patch/msgid/20190117210334.13234-1-daniel.vetter@ffwll.ch
2019-01-18 04:03:34 +07:00
#include <drm/drm_probe_helper.h>
#include <drm/drmP.h>
#include "sun8i_vi_layer.h"
#include "sun8i_mixer.h"
#include "sun8i_vi_scaler.h"
static void sun8i_vi_layer_enable(struct sun8i_mixer *mixer, int channel,
int overlay, bool enable, unsigned int zpos,
unsigned int old_zpos)
{
u32 val, bld_base, ch_base;
bld_base = sun8i_blender_base(mixer);
ch_base = sun8i_channel_base(mixer, channel);
DRM_DEBUG_DRIVER("%sabling VI channel %d overlay %d\n",
enable ? "En" : "Dis", channel, overlay);
if (enable)
val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN, val);
if (!enable || zpos != old_zpos) {
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos),
0);
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_BLEND_ROUTE(bld_base),
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos),
0);
}
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
if (enable) {
val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
val, val);
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_BLEND_ROUTE(bld_base),
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
val);
}
}
static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
int overlay, struct drm_plane *plane,
unsigned int zpos)
{
struct drm_plane_state *state = plane->state;
const struct drm_format_info *format = state->fb->format;
u32 src_w, src_h, dst_w, dst_h;
u32 bld_base, ch_base;
u32 outsize, insize;
u32 hphase, vphase;
bool subsampled;
DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n",
channel, overlay);
bld_base = sun8i_blender_base(mixer);
ch_base = sun8i_channel_base(mixer, channel);
src_w = drm_rect_width(&state->src) >> 16;
src_h = drm_rect_height(&state->src) >> 16;
dst_w = drm_rect_width(&state->dst);
dst_h = drm_rect_height(&state->dst);
hphase = state->src.x1 & 0xffff;
vphase = state->src.y1 & 0xffff;
/* make coordinates dividable by subsampling factor */
if (format->hsub > 1) {
int mask, remainder;
mask = format->hsub - 1;
remainder = (state->src.x1 >> 16) & mask;
src_w = (src_w + remainder) & ~mask;
hphase += remainder << 16;
}
if (format->vsub > 1) {
int mask, remainder;
mask = format->vsub - 1;
remainder = (state->src.y1 >> 16) & mask;
src_h = (src_h + remainder) & ~mask;
vphase += remainder << 16;
}
insize = SUN8I_MIXER_SIZE(src_w, src_h);
outsize = SUN8I_MIXER_SIZE(dst_w, dst_h);
/* Set height and width */
DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
(state->src.x1 >> 16) & ~(format->hsub - 1),
(state->src.y1 >> 16) & ~(format->vsub - 1));
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, overlay),
insize);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
insize);
/*
* Scaler must be enabled for subsampled formats, so it scales
* chroma to same size as luma.
*/
subsampled = format->hsub > 1 || format->vsub > 1;
if (insize != outsize || subsampled || hphase || vphase) {
u32 hscale, vscale;
DRM_DEBUG_DRIVER("HW scaling is enabled\n");
hscale = state->src_w / state->crtc_w;
vscale = state->src_h / state->crtc_h;
sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
dst_h, hscale, vscale, hphase, vphase,
format);
sun8i_vi_scaler_enable(mixer, channel, true);
} else {
DRM_DEBUG_DRIVER("HW scaling is not needed\n");
sun8i_vi_scaler_enable(mixer, channel, false);
}
/* Set base coordinates */
DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
state->dst.x1, state->dst.y1);
DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
outsize);
return 0;
}
static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
int overlay, struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
const struct de2_fmt_info *fmt_info;
u32 val, ch_base;
ch_base = sun8i_channel_base(mixer, channel);
fmt_info = sun8i_mixer_format_info(state->fb->format->format);
if (!fmt_info) {
DRM_DEBUG_DRIVER("Invalid format\n");
return -EINVAL;
}
val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
sun8i_csc_enable_ccsc(mixer, channel, true);
} else {
sun8i_csc_enable_ccsc(mixer, channel, false);
}
if (fmt_info->rgb)
val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
else
val = 0;
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE, val);
/* It seems that YUV formats use global alpha setting. */
if (mixer->cfg->is_de3)
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base,
overlay),
SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK,
SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(0xff));
return 0;
}
static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
int overlay, struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct drm_framebuffer *fb = state->fb;
const struct drm_format_info *format = fb->format;
struct drm_gem_cma_object *gem;
u32 dx, dy, src_x, src_y;
dma_addr_t paddr;
u32 ch_base;
int i;
ch_base = sun8i_channel_base(mixer, channel);
/* Adjust x and y to be dividable by subsampling factor */
src_x = (state->src.x1 >> 16) & ~(format->hsub - 1);
src_y = (state->src.y1 >> 16) & ~(format->vsub - 1);
for (i = 0; i < format->num_planes; i++) {
/* Get the physical address of the buffer in memory */
gem = drm_fb_cma_get_gem_obj(fb, i);
DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr);
/* Compute the start of the displayed memory */
paddr = gem->paddr + fb->offsets[i];
dx = src_x;
dy = src_y;
if (i > 0) {
dx /= format->hsub;
dy /= format->vsub;
}
/* Fixup framebuffer address for src coordinates */
paddr += dx * format->cpp[i];
paddr += dy * fb->pitches[i];
/* Set the line width */
DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
i + 1, fb->pitches[i]);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
overlay, i),
fb->pitches[i]);
DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
i + 1, &paddr);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
overlay, i),
lower_32_bits(paddr));
}
return 0;
}
static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
struct drm_crtc *crtc = state->crtc;
struct drm_crtc_state *crtc_state;
int min_scale, max_scale;
if (!crtc)
return 0;
crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
if (WARN_ON(!crtc_state))
return -EINVAL;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
max_scale = DRM_PLANE_HELPER_NO_SCALING;
if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) {
min_scale = SUN8I_VI_SCALER_SCALE_MIN;
max_scale = SUN8I_VI_SCALER_SCALE_MAX;
}
drm: Don't pass clip to drm_atomic_helper_check_plane_state() Move the plane clip rectangle handling into drm_atomic_helper_check_plane_state(). Drivers no longer have to worry about such mundane details. v2: Convert armada, rcar, and sun4i as well v3: Resolve simple_kms_helper conflict Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Brian Starkey <brian.starkey@arm.com> Cc: Mali DP Maintainers <malidp@foss.arm.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Gustavo Padovan <gustavo@padovan.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: CK Hu <ck.hu@mediatek.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Rob Clark <robdclark@gmail.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Sandy Huang <hjc@rock-chips.com> Cc: "Heiko Stübner" <heiko@sntech.de> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: Sinclair Yeh <syeh@vmware.com> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Archit Taneja <architt@codeaurora.org> Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-tegra@vger.kernel.org Cc: Russell King <rmk+kernel@armlinux.org.uk> Suggested-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Archit Taneja <architt@codeaurora.org> #msm Link: https://patchwork.freedesktop.org/patch/msgid/20180123170857.13818-5-ville.syrjala@linux.intel.com Acked-by: Liviu Dudau <liviu.dudau@arm.com> #hdlcd,malidp Acked-by: Philipp Zabel <p.zabel@pengutronix.de> #imx,mtk Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> #vmwgfx Acked-by: Neil Armstrong <narmstrong@baylibre.com> #meson Acked-by: Shawn Guo <shawnguo@kernel.org> #zte
2018-01-24 00:08:57 +07:00
return drm_atomic_helper_check_plane_state(state, crtc_state,
min_scale, max_scale,
true, true);
}
static void sun8i_vi_layer_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
unsigned int old_zpos = old_state->normalized_zpos;
struct sun8i_mixer *mixer = layer->mixer;
sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0,
old_zpos);
}
static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane);
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
unsigned int zpos = plane->state->normalized_zpos;
unsigned int old_zpos = old_state->normalized_zpos;
struct sun8i_mixer *mixer = layer->mixer;
if (!plane->state->visible) {
sun8i_vi_layer_enable(mixer, layer->channel,
layer->overlay, false, 0, old_zpos);
return;
}
sun8i_vi_layer_update_coord(mixer, layer->channel,
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
layer->overlay, plane, zpos);
sun8i_vi_layer_update_formats(mixer, layer->channel,
layer->overlay, plane);
sun8i_vi_layer_update_buffer(mixer, layer->channel,
layer->overlay, plane);
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay,
true, zpos, old_zpos);
}
static struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
.prepare_fb = drm_gem_fb_prepare_fb,
.atomic_check = sun8i_vi_layer_atomic_check,
.atomic_disable = sun8i_vi_layer_atomic_disable,
.atomic_update = sun8i_vi_layer_atomic_update,
};
static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.destroy = drm_plane_cleanup,
.disable_plane = drm_atomic_helper_disable_plane,
.reset = drm_atomic_helper_plane_reset,
.update_plane = drm_atomic_helper_update_plane,
};
/*
* While all RGB formats are supported, VI planes don't support
* alpha blending, so there is no point having formats with alpha
* channel if their opaque analog exist.
*/
static const u32 sun8i_vi_layer_formats[] = {
DRM_FORMAT_ABGR1555,
DRM_FORMAT_ABGR4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_ARGB4444,
DRM_FORMAT_BGR565,
DRM_FORMAT_BGR888,
DRM_FORMAT_BGRA5551,
DRM_FORMAT_BGRA4444,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGB888,
DRM_FORMAT_RGBA4444,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_RGBX8888,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_NV16,
DRM_FORMAT_NV12,
DRM_FORMAT_NV21,
DRM_FORMAT_NV61,
DRM_FORMAT_UYVY,
DRM_FORMAT_VYUY,
DRM_FORMAT_YUYV,
DRM_FORMAT_YVYU,
DRM_FORMAT_YUV411,
DRM_FORMAT_YUV420,
DRM_FORMAT_YUV422,
DRM_FORMAT_YUV444,
DRM_FORMAT_YVU411,
DRM_FORMAT_YVU420,
DRM_FORMAT_YVU422,
DRM_FORMAT_YVU444,
};
struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
struct sun8i_mixer *mixer,
int index)
{
struct sun8i_vi_layer *layer;
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
unsigned int plane_cnt;
int ret;
layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL);
if (!layer)
return ERR_PTR(-ENOMEM);
/* possible crtcs are set later */
ret = drm_universal_plane_init(drm, &layer->plane, 0,
&sun8i_vi_layer_funcs,
sun8i_vi_layer_formats,
ARRAY_SIZE(sun8i_vi_layer_formats),
NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
if (ret) {
dev_err(drm->dev, "Couldn't initialize layer\n");
return ERR_PTR(ret);
}
drm/sun4i: Implement zpos for DE2 Initial implementation of DE2 planes only supported fixed zpos. Expand implementation with configurable zpos property. Implementation background: Channel in DE2 driver represents one DRM plane, whereas pipe is just mapped channel to known Z position. Pipe 0 will always be at the bottom, pipe 1 just above pipe 0 and so on. If, for example, channel 1 is mapped at pipe 0 and channel 0 at pipe 1, whatever is on channel 0 will appear on top. Before this commit, channel id was used for addressing channel related registers (prefixed with SUN8I_MIXER_CHAN_UI_ or SUN8I_MIXER_CHAN_VI_) and pipe registers (prefixed with SUN8I_MIXER_BLEND_). Additionally, register SUN8I_MIXER_BLEND_ROUTE, which takes care for mapping channels to pipes had fixed value. It mapped channel 0 to pipe 0, 1 to 1 and so on. Consequence of all that was fixed Z order of planes. With this commit, pipe registers are using zpos property as index and channel related registers still use channel id as index. Pipe mapping register is now set dynamically too and pipe enable register is rebuild every time to make sure only active pipes are enabled. Testing was done to confirm that there is no issues if bottom plane contains pixels with alpha value < 0xff and if it doesn't whole screen. Tested-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180706164732.24166-1-jernej.skrabec@siol.net
2018-07-06 23:47:32 +07:00
plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
ret = drm_plane_create_zpos_property(&layer->plane, index,
0, plane_cnt - 1);
if (ret) {
dev_err(drm->dev, "Couldn't add zpos property\n");
return ERR_PTR(ret);
}
drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
layer->mixer = mixer;
layer->channel = index;
layer->overlay = 0;
return layer;
}