2011-10-14 08:40:52 +07:00
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/*
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* at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
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*
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2012-04-09 18:26:33 +07:00
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* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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2011-10-14 08:40:52 +07:00
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*
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2012-04-09 18:26:33 +07:00
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* Licensed under GPLv2.
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2011-10-14 08:40:52 +07:00
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*/
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2013-05-15 00:21:50 +07:00
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#include "at91sam9260.dtsi"
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2011-10-14 08:40:52 +07:00
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/ {
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model = "Atmel AT91SAM9G20 family SoC";
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compatible = "atmel,at91sam9g20";
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2012-04-03 01:44:20 +07:00
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memory {
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2011-10-14 08:40:52 +07:00
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reg = <0x20000000 0x08000000>;
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};
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2012-05-16 22:37:06 +07:00
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ahb {
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apb {
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2012-09-12 13:42:16 +07:00
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i2c0: i2c@fffac000 {
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compatible = "atmel,at91sam9g20-i2c";
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};
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2014-06-11 17:14:42 +07:00
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ssc0: ssc@fffbc000 {
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compatible = "atmel,at91sam9rl-ssc";
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};
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2012-05-16 22:37:06 +07:00
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adc0: adc@fffe0000 {
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atmel,adc-startup-time = <40>;
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};
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2014-06-17 00:22:40 +07:00
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pmc: pmc@fffffc00 {
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plla: pllack {
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atmel,clk-input-range = <2000000 32000000>;
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atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
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<695000000 750000000 1 0>,
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<645000000 700000000 2 0>,
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<595000000 650000000 3 0>,
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<545000000 600000000 0 1>,
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<495000000 550000000 1 1>,
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<445000000 500000000 2 1>,
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<400000000 450000000 3 1>;
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};
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pllb: pllbck {
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2014-09-02 04:29:46 +07:00
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compatible = "atmel,at91sam9g20-clk-pllb";
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2014-06-17 00:22:40 +07:00
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atmel,clk-input-range = <2000000 32000000>;
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atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
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};
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mck: masterck {
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atmel,clk-output-range = <0 133000000>;
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atmel,clk-divisors = <1 2 4 6>;
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};
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};
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2012-05-16 22:37:06 +07:00
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};
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};
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2011-10-14 08:40:52 +07:00
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};
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