2018-01-17 23:36:44 +07:00
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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2017-03-14 02:02:00 +07:00
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/*
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* Copyright 2014-2016 Freescale Semiconductor Inc.
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* Copyright 2016 NXP
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*
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*/
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#ifndef __FSL_DPAA2_GLOBAL_H
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#define __FSL_DPAA2_GLOBAL_H
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#include <linux/types.h>
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#include <linux/cpumask.h>
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#include "dpaa2-fd.h"
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struct dpaa2_dq {
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union {
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struct common {
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u8 verb;
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u8 reserved[63];
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} common;
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struct dq {
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u8 verb;
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u8 stat;
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__le16 seqnum;
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__le16 oprid;
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u8 reserved;
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u8 tok;
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__le32 fqid;
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u32 reserved2;
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__le32 fq_byte_cnt;
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__le32 fq_frm_cnt;
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__le64 fqd_ctx;
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u8 fd[32];
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} dq;
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struct scn {
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u8 verb;
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u8 stat;
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u8 state;
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u8 reserved;
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__le32 rid_tok;
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__le64 ctx;
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} scn;
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};
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};
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/* Parsing frame dequeue results */
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/* FQ empty */
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#define DPAA2_DQ_STAT_FQEMPTY 0x80
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/* FQ held active */
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#define DPAA2_DQ_STAT_HELDACTIVE 0x40
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/* FQ force eligible */
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#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
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/* valid frame */
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#define DPAA2_DQ_STAT_VALIDFRAME 0x10
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/* FQ ODP enable */
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#define DPAA2_DQ_STAT_ODPVALID 0x04
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/* volatile dequeue */
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#define DPAA2_DQ_STAT_VOLATILE 0x02
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/* volatile dequeue command is expired */
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#define DPAA2_DQ_STAT_EXPIRED 0x01
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#define DQ_FQID_MASK 0x00FFFFFF
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#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
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/**
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* dpaa2_dq_flags() - Get the stat field of dequeue response
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* @dq: the dequeue result.
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*/
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static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
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{
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return dq->dq.stat;
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}
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/**
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* dpaa2_dq_is_pull() - Check whether the dq response is from a pull
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* command.
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* @dq: the dequeue result
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*
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* Return 1 for volatile(pull) dequeue, 0 for static dequeue.
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*/
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static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
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{
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return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
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}
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/**
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* dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
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* @dq: the dequeue result
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*
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* Return boolean.
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*/
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static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
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{
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return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
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}
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/**
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* dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
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* @dq: the dequeue result
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*
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* seqnum is valid only if VALIDFRAME flag is TRUE
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*
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* Return seqnum.
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*/
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static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
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{
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return le16_to_cpu(dq->dq.seqnum);
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}
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/**
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* dpaa2_dq_odpid() - Get the odpid field in dequeue response
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* @dq: the dequeue result
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*
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* odpid is valid only if ODPVALID flag is TRUE.
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*
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* Return odpid.
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*/
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static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
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{
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return le16_to_cpu(dq->dq.oprid);
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}
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/**
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* dpaa2_dq_fqid() - Get the fqid in dequeue response
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* @dq: the dequeue result
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*
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* Return fqid.
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*/
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static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
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{
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return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
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}
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/**
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* dpaa2_dq_byte_count() - Get the byte count in dequeue response
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* @dq: the dequeue result
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*
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* Return the byte count remaining in the FQ.
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*/
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static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
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{
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return le32_to_cpu(dq->dq.fq_byte_cnt);
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}
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/**
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* dpaa2_dq_frame_count() - Get the frame count in dequeue response
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* @dq: the dequeue result
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*
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* Return the frame count remaining in the FQ.
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*/
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static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
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{
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return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
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}
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/**
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* dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
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* @dq: the dequeue result
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*
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* Return the frame queue context.
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*/
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static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
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{
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return le64_to_cpu(dq->dq.fqd_ctx);
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}
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/**
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* dpaa2_dq_fd() - Get the frame descriptor in dequeue response
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* @dq: the dequeue result
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*
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* Return the frame descriptor.
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*/
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static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
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{
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return (const struct dpaa2_fd *)&dq->dq.fd[0];
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}
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2018-09-12 15:59:29 +07:00
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#define DPAA2_CSCN_SIZE sizeof(struct dpaa2_dq)
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#define DPAA2_CSCN_ALIGN 16
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#define DPAA2_CSCN_STATE_CG BIT(0)
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/**
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* dpaa2_cscn_state_congested() - Check congestion state
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* @cscn: congestion SCN (delivered to WQ or memory)
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*
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i * Return true is congested.
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*/
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static inline bool dpaa2_cscn_state_congested(struct dpaa2_dq *cscn)
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{
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return !!(cscn->scn.state & DPAA2_CSCN_STATE_CG);
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}
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2017-03-14 02:02:00 +07:00
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#endif /* __FSL_DPAA2_GLOBAL_H */
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