2018-09-07 08:52:28 +07:00
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/* SPDX-License-Identifier: GPL-2.0+
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2016-10-28 03:42:51 +07:00
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*
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2018-09-07 08:52:28 +07:00
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* Copyright (C) 2016 Cogent Embedded Inc.
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2016-10-28 03:42:51 +07:00
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a7745 CPG Core Clocks */
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#define R8A7745_CLK_Z2 0
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#define R8A7745_CLK_ZG 1
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#define R8A7745_CLK_ZTR 2
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#define R8A7745_CLK_ZTRD2 3
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#define R8A7745_CLK_ZT 4
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#define R8A7745_CLK_ZX 5
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#define R8A7745_CLK_ZS 6
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#define R8A7745_CLK_HP 7
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#define R8A7745_CLK_B 9
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#define R8A7745_CLK_LB 10
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#define R8A7745_CLK_P 11
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#define R8A7745_CLK_CL 12
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#define R8A7745_CLK_CP 13
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#define R8A7745_CLK_M2 14
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#define R8A7745_CLK_ZB3 16
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#define R8A7745_CLK_ZB3D2 17
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#define R8A7745_CLK_DDR 18
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#define R8A7745_CLK_SDH 19
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#define R8A7745_CLK_SD0 20
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#define R8A7745_CLK_SD2 21
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#define R8A7745_CLK_SD3 22
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#define R8A7745_CLK_MMC0 23
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#define R8A7745_CLK_MP 24
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#define R8A7745_CLK_QSPI 25
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#define R8A7745_CLK_CPEX 26
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#define R8A7745_CLK_RCAN 27
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#define R8A7745_CLK_R 28
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#define R8A7745_CLK_OSC 29
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#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */
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