linux_dsm_epyc7002/arch/blackfin/mach-common/irqpanic.c

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blackfin architecture This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Aubrey Li <aubrey.li@analog.com> Signed-off-by: Jie Zhang <jie.zhang@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 04:50:22 +07:00
/*
* File: arch/blackfin/mach-common/irqpanic.c
* Based on:
* Author:
*
* Created: ?
* Description: panic kernel with dump information
*
* Modified: rgetz - added cache checking code 14Feb06
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <asm/traps.h>
#include <asm/blackfin.h>
#ifdef CONFIG_DEBUG_ICACHE_CHECK
#define L1_ICACHE_START 0xffa10000
#define L1_ICACHE_END 0xffa13fff
void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text));
#endif
/*
* irq_panic - calls panic with string setup
*/
asmlinkage void irq_panic(int reason, struct pt_regs *regs)
{
#ifdef CONFIG_DEBUG_ICACHE_CHECK
unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
unsigned short i, j, die;
unsigned int bad[10][6];
/* check entire cache for coherency
* Since printk is in cacheable memory,
* don't call it until you have checked everything
*/
die = 0;
i = 0;
/* check icache */
for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
/* Grab various address bits for the itest_cmd fields */
cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
0); /* Access Tag, Read access */
SSYNC();
bfin_write_ITEST_COMMAND(cmd);
SSYNC();
tag = bfin_read_ITEST_DATA0();
SSYNC();
/* if tag is marked as valid, check it */
if (tag & 1) {
/* The icache is arranged in 4 groups of 64-bits */
for (j = 0; j < 32; j += 8) {
cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
(((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
(((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
4); /* Access Data, Read access */
SSYNC();
bfin_write_ITEST_COMMAND(cmd);
SSYNC();
cache_hi = bfin_read_ITEST_DATA1();
cache_lo = bfin_read_ITEST_DATA0();
pa = ((unsigned int *)((tag & 0xffffcc00) |
((ca + j) & ~(0xffffcc00))));
/*
* Debugging this, enable
*
* printk("addr: %08x %08x%08x | %08x%08x\n",
* ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
* cache_hi, cache_lo, *(pa+1), *pa);
*/
if (cache_hi != *(pa + 1) || cache_lo != *pa) {
/* Since icache is not working, stay out of it, by not printing */
die = 1;
bad[i][0] = (ca + j);
bad[i][1] = cache_hi;
bad[i][2] = cache_lo;
bad[i][3] = ((tag & 0xffffcc00) |
((ca + j) & ~(0xffffcc00)));
bad[i][4] = *(pa + 1);
bad[i][5] = *(pa);
i++;
}
}
}
}
if (die) {
printk(KERN_EMERG "icache coherency error\n");
for (j = 0; j <= i; j++) {
printk(KERN_EMERG
"cache address : %08x cache value : %08x%08x\n",
bad[j][0], bad[j][1], bad[j][2]);
printk(KERN_EMERG
"physical address: %08x SDRAM value : %08x%08x\n",
bad[j][3], bad[j][4], bad[j][5]);
}
panic("icache coherency error");
} else {
printk(KERN_EMERG "icache checked, and OK\n");
}
#endif
}