2009-01-30 15:32:28 +07:00
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/*
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* Copyright (C) 2002 Motorola GSG-China
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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* USA.
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*
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* Author:
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* Darius Augulis, Teltonika Inc.
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*
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* Desc.:
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* Implementation of I2C Adapter/Algorithm Driver
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* for I2C Bus integrated in Freescale i.MX/MXC processors
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*
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* Derived from Motorola GSG China I2C example driver
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*
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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2013-08-07 16:05:36 +07:00
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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2009-01-30 15:32:28 +07:00
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*/
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/** Includes *******************************************************************
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*******************************************************************************/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/slab.h>
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2011-09-08 14:09:35 +07:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_i2c.h>
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2012-08-24 20:14:29 +07:00
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#include <linux/platform_data/i2c-imx.h>
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2009-01-30 15:32:28 +07:00
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/** Defines ********************************************************************
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*******************************************************************************/
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/* This will be the driver name the kernel reports */
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#define DRIVER_NAME "imx-i2c"
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/* Default value */
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#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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2013-08-07 16:05:40 +07:00
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/* IMX I2C registers:
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* the I2C register offset is different between SoCs,
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* to provid support for all these chips, split the
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* register offset into a fixed base address and a
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* variable shift value, then the full register offset
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* will be calculated by
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* reg_off = ( reg_base_addr << reg_shift)
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*/
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2009-01-30 15:32:28 +07:00
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#define IMX_I2C_IADR 0x00 /* i2c slave address */
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2013-08-07 16:05:40 +07:00
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#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
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#define IMX_I2C_I2CR 0x02 /* i2c control */
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#define IMX_I2C_I2SR 0x03 /* i2c status */
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#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
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#define IMX_I2C_REGSHIFT 2
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2009-01-30 15:32:28 +07:00
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/* Bits of IMX I2C registers */
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#define I2SR_RXAK 0x01
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#define I2SR_IIF 0x02
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#define I2SR_SRW 0x04
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#define I2SR_IAL 0x10
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#define I2SR_IBB 0x20
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#define I2SR_IAAS 0x40
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#define I2SR_ICF 0x80
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#define I2CR_RSTA 0x04
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#define I2CR_TXAK 0x08
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#define I2CR_MTX 0x10
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#define I2CR_MSTA 0x20
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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2013-08-07 16:05:41 +07:00
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/* register bits different operating codes definition:
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* 1) I2SR: Interrupt flags clear operation differ between SoCs:
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* - write zero to clear(w0c) INT flag on i.MX,
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* - but write one to clear(w1c) INT flag on Vybrid.
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* 2) I2CR: I2C module enable operation also differ between SoCs:
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* - set I2CR_IEN bit enable the module on i.MX,
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* - but clear I2CR_IEN bit enable the module on Vybrid.
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*/
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#define I2SR_CLR_OPCODE_W0C 0x0
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#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
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#define I2CR_IEN_OPCODE_0 0x0
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#define I2CR_IEN_OPCODE_1 I2CR_IEN
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#define IMX_I2SR_CLR_OPCODE I2SR_CLR_OPCODE_W0C
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#define IMX_I2CR_IEN_OPCODE I2CR_IEN_OPCODE_1
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2009-01-30 15:32:28 +07:00
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/** Variables ******************************************************************
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*******************************************************************************/
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/*
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* sorted list of clock divider, register value pairs
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* taken from table 26-5, p.26-9, Freescale i.MX
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* Integrated Portable System Processor Reference Manual
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* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
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*
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* Duplicated divider values removed from list
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*/
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2013-08-07 16:05:36 +07:00
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struct imx_i2c_clk_pair {
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u16 div;
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u16 val;
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};
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2009-01-30 15:32:28 +07:00
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2013-08-07 16:05:36 +07:00
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static struct imx_i2c_clk_pair __initdata i2c_clk_div[] = {
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2009-01-30 15:32:28 +07:00
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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2012-09-14 14:19:00 +07:00
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enum imx_i2c_type {
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IMX1_I2C,
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IMX21_I2C,
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};
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2009-01-30 15:32:28 +07:00
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struct imx_i2c_struct {
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struct i2c_adapter adapter;
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struct clk *clk;
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void __iomem *base;
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wait_queue_head_t queue;
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unsigned long i2csr;
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2009-04-06 21:27:45 +07:00
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unsigned int disable_delay;
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2009-10-17 16:46:22 +07:00
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int stopped;
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2009-10-17 16:46:24 +07:00
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unsigned int ifdr; /* IMX_I2C_IFDR */
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2012-09-14 14:19:00 +07:00
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enum imx_i2c_type devtype;
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};
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static struct platform_device_id imx_i2c_devtype[] = {
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{
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.name = "imx1-i2c",
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.driver_data = IMX1_I2C,
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}, {
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.name = "imx21-i2c",
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.driver_data = IMX21_I2C,
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}, {
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/* sentinel */
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}
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2009-01-30 15:32:28 +07:00
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};
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2012-09-14 14:19:00 +07:00
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MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
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2009-01-30 15:32:28 +07:00
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2011-09-08 14:09:35 +07:00
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static const struct of_device_id i2c_imx_dt_ids[] = {
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2012-09-14 14:19:00 +07:00
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{ .compatible = "fsl,imx1-i2c", .data = &imx_i2c_devtype[IMX1_I2C], },
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{ .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], },
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2011-09-08 14:09:35 +07:00
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{ /* sentinel */ }
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};
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2013-06-21 04:07:06 +07:00
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MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
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2011-09-08 14:09:35 +07:00
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2012-09-14 14:19:00 +07:00
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static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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{
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return i2c_imx->devtype == IMX1_I2C;
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}
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2013-08-07 16:05:39 +07:00
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static inline void imx_i2c_write_reg(unsigned int val,
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struct imx_i2c_struct *i2c_imx, unsigned int reg)
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{
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2013-08-07 16:05:40 +07:00
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writeb(val, i2c_imx->base + (reg << IMX_I2C_REGSHIFT));
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2013-08-07 16:05:39 +07:00
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}
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static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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unsigned int reg)
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{
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2013-08-07 16:05:40 +07:00
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return readb(i2c_imx->base + (reg << IMX_I2C_REGSHIFT));
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2013-08-07 16:05:39 +07:00
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}
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2009-01-30 15:32:28 +07:00
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/** Functions for IMX I2C adapter driver ***************************************
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*******************************************************************************/
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2009-10-17 16:46:22 +07:00
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
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2009-01-30 15:32:28 +07:00
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{
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unsigned long orig_jiffies = jiffies;
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2009-10-17 16:46:22 +07:00
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unsigned int temp;
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2009-01-30 15:32:28 +07:00
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dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
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2009-10-17 16:46:22 +07:00
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while (1) {
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2013-08-07 16:05:39 +07:00
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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2009-10-17 16:46:22 +07:00
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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break;
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2010-03-23 23:28:28 +07:00
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if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
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2009-01-30 15:32:28 +07:00
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dev_dbg(&i2c_imx->adapter.dev,
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"<%s> I2C bus is busy\n", __func__);
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2010-03-23 23:28:28 +07:00
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return -ETIMEDOUT;
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2009-01-30 15:32:28 +07:00
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}
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schedule();
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}
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return 0;
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}
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static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
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{
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2010-06-21 14:27:05 +07:00
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wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
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2009-01-30 15:32:28 +07:00
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2010-06-21 14:27:05 +07:00
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if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
|
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
|
}
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
|
|
|
|
|
i2c_imx->i2csr = 0;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
|
|
|
|
|
{
|
2013-08-07 16:05:39 +07:00
|
|
|
if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
|
|
|
|
|
return -EIO; /* No ACK */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-17 16:46:22 +07:00
|
|
|
static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
|
2009-01-30 15:32:28 +07:00
|
|
|
{
|
|
|
|
|
unsigned int temp = 0;
|
2009-10-17 16:46:22 +07:00
|
|
|
int result;
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
|
|
|
|
|
2011-11-15 13:48:08 +07:00
|
|
|
clk_prepare_enable(i2c_imx->clk);
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Enable I2C controller */
|
2013-08-07 16:05:41 +07:00
|
|
|
imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR);
|
|
|
|
|
imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
|
|
|
|
|
/* Wait controller to be stable */
|
|
|
|
|
udelay(50);
|
|
|
|
|
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Start I2C transaction */
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
temp |= I2CR_MSTA;
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
result = i2c_imx_bus_busy(i2c_imx, 1);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
i2c_imx->stopped = 0;
|
|
|
|
|
|
2009-01-30 15:32:28 +07:00
|
|
|
temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
return result;
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
|
|
|
|
|
{
|
|
|
|
|
unsigned int temp = 0;
|
|
|
|
|
|
2009-10-17 16:46:22 +07:00
|
|
|
if (!i2c_imx->stopped) {
|
|
|
|
|
/* Stop I2C transaction */
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
}
|
2012-09-14 14:19:00 +07:00
|
|
|
if (is_imx1_i2c(i2c_imx)) {
|
2009-10-17 16:46:23 +07:00
|
|
|
/*
|
|
|
|
|
* This delay caused by an i.MXL hardware bug.
|
|
|
|
|
* If no (or too short) delay, no "STOP" bit will be generated.
|
|
|
|
|
*/
|
|
|
|
|
udelay(i2c_imx->disable_delay);
|
|
|
|
|
}
|
2009-10-17 16:46:22 +07:00
|
|
|
|
2010-01-22 00:55:32 +07:00
|
|
|
if (!i2c_imx->stopped) {
|
2009-10-17 16:46:22 +07:00
|
|
|
i2c_imx_bus_busy(i2c_imx, 0);
|
2010-01-22 00:55:32 +07:00
|
|
|
i2c_imx->stopped = 1;
|
|
|
|
|
}
|
2009-10-17 16:46:22 +07:00
|
|
|
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Disable I2C controller */
|
2013-08-07 16:05:41 +07:00
|
|
|
imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR);
|
2011-11-15 13:48:08 +07:00
|
|
|
clk_disable_unprepare(i2c_imx->clk);
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
|
|
|
|
|
unsigned int rate)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i2c_clk_rate;
|
|
|
|
|
unsigned int div;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* Divider value calculation */
|
|
|
|
|
i2c_clk_rate = clk_get_rate(i2c_imx->clk);
|
|
|
|
|
div = (i2c_clk_rate + rate - 1) / rate;
|
2013-08-07 16:05:36 +07:00
|
|
|
if (div < i2c_clk_div[0].div)
|
2009-01-30 15:32:28 +07:00
|
|
|
i = 0;
|
2013-08-07 16:05:36 +07:00
|
|
|
else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1].div)
|
2009-01-30 15:32:28 +07:00
|
|
|
i = ARRAY_SIZE(i2c_clk_div) - 1;
|
|
|
|
|
else
|
2013-08-07 16:05:36 +07:00
|
|
|
for (i = 0; i2c_clk_div[i].div < div; i++);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
2009-10-17 16:46:24 +07:00
|
|
|
/* Store divider value */
|
2013-08-07 16:05:36 +07:00
|
|
|
i2c_imx->ifdr = i2c_clk_div[i].val;
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* There dummy delay is calculated.
|
|
|
|
|
* It should be about one I2C clock period long.
|
|
|
|
|
* This delay is used in I2C bus disable function
|
|
|
|
|
* to fix chip hardware bug.
|
|
|
|
|
*/
|
2013-08-07 16:05:36 +07:00
|
|
|
i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
|
2009-01-30 15:32:28 +07:00
|
|
|
+ (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
|
|
|
|
|
|
|
|
|
|
/* dev_dbg() can't be used, because adapter is not yet registered */
|
|
|
|
|
#ifdef CONFIG_I2C_DEBUG_BUS
|
2012-08-02 03:38:15 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
|
2009-01-30 15:32:28 +07:00
|
|
|
__func__, i2c_clk_rate, div);
|
2012-08-02 03:38:15 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
|
2013-08-07 16:05:36 +07:00
|
|
|
__func__, i2c_clk_div[i].val, i2c_clk_div[i].div);
|
2009-01-30 15:32:28 +07:00
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
|
|
|
|
|
{
|
|
|
|
|
struct imx_i2c_struct *i2c_imx = dev_id;
|
|
|
|
|
unsigned int temp;
|
|
|
|
|
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
2009-01-30 15:32:28 +07:00
|
|
|
if (temp & I2SR_IIF) {
|
|
|
|
|
/* save status register */
|
|
|
|
|
i2c_imx->i2csr = temp;
|
|
|
|
|
temp &= ~I2SR_IIF;
|
2013-08-07 16:05:41 +07:00
|
|
|
temp |= (IMX_I2SR_CLR_OPCODE & I2SR_IIF);
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
|
2010-06-21 14:27:05 +07:00
|
|
|
wake_up(&i2c_imx->queue);
|
2009-01-30 15:32:28 +07:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return IRQ_NONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
|
|
|
|
|
{
|
|
|
|
|
int i, result;
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
|
|
|
|
|
__func__, msgs->addr << 1);
|
|
|
|
|
|
|
|
|
|
/* write slave address */
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
|
2009-01-30 15:32:28 +07:00
|
|
|
result = i2c_imx_trx_complete(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
result = i2c_imx_acked(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
|
|
|
|
|
|
|
|
|
|
/* write data */
|
|
|
|
|
for (i = 0; i < msgs->len; i++) {
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> write byte: B%d=0x%X\n",
|
|
|
|
|
__func__, i, msgs->buf[i]);
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
|
2009-01-30 15:32:28 +07:00
|
|
|
result = i2c_imx_trx_complete(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
result = i2c_imx_acked(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
|
|
|
|
|
{
|
|
|
|
|
int i, result;
|
|
|
|
|
unsigned int temp;
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> write slave address: addr=0x%x\n",
|
|
|
|
|
__func__, (msgs->addr << 1) | 0x01);
|
|
|
|
|
|
|
|
|
|
/* write slave address */
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
|
2009-01-30 15:32:28 +07:00
|
|
|
result = i2c_imx_trx_complete(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
result = i2c_imx_acked(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
|
|
|
|
|
|
|
|
|
|
/* setup bus to read data */
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
temp &= ~I2CR_MTX;
|
|
|
|
|
if (msgs->len - 1)
|
|
|
|
|
temp &= ~I2CR_TXAK;
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
|
|
|
|
imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
|
|
|
|
|
|
|
|
|
|
/* read data */
|
|
|
|
|
for (i = 0; i < msgs->len; i++) {
|
|
|
|
|
result = i2c_imx_trx_complete(i2c_imx);
|
|
|
|
|
if (result)
|
|
|
|
|
return result;
|
|
|
|
|
if (i == (msgs->len - 1)) {
|
2009-10-17 16:46:22 +07:00
|
|
|
/* It must generate STOP before read I2DR to prevent
|
|
|
|
|
controller from generating another clock cycle */
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> clear MSTA\n", __func__);
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
i2c_imx_bus_busy(i2c_imx, 0);
|
|
|
|
|
i2c_imx->stopped = 1;
|
2009-01-30 15:32:28 +07:00
|
|
|
} else if (i == (msgs->len - 2)) {
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> set TXAK\n", __func__);
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
temp |= I2CR_TXAK;
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
2013-08-07 16:05:39 +07:00
|
|
|
msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> read byte: B%d=0x%X\n",
|
|
|
|
|
__func__, i, msgs->buf[i]);
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
|
|
|
|
struct i2c_msg *msgs, int num)
|
|
|
|
|
{
|
|
|
|
|
unsigned int i, temp;
|
|
|
|
|
int result;
|
|
|
|
|
struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
|
|
|
|
|
2009-10-17 16:46:22 +07:00
|
|
|
/* Start I2C transfer */
|
|
|
|
|
result = i2c_imx_start(i2c_imx);
|
2009-01-30 15:32:28 +07:00
|
|
|
if (result)
|
|
|
|
|
goto fail0;
|
|
|
|
|
|
|
|
|
|
/* read/write data */
|
|
|
|
|
for (i = 0; i < num; i++) {
|
|
|
|
|
if (i) {
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> repeated start\n", __func__);
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
temp |= I2CR_RSTA;
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
2009-10-17 16:46:22 +07:00
|
|
|
result = i2c_imx_bus_busy(i2c_imx, 1);
|
|
|
|
|
if (result)
|
|
|
|
|
goto fail0;
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> transfer message: %d\n", __func__, i);
|
|
|
|
|
/* write/read data */
|
|
|
|
|
#ifdef CONFIG_I2C_DEBUG_BUS
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
|
|
|
|
|
"MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
|
|
|
|
|
(temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
|
|
|
|
|
(temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
|
|
|
|
|
(temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
|
2013-08-07 16:05:39 +07:00
|
|
|
temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev,
|
|
|
|
|
"<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
|
|
|
|
|
"IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
|
|
|
|
|
(temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
|
|
|
|
|
(temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
|
|
|
|
|
(temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
|
|
|
|
|
(temp & I2SR_RXAK ? 1 : 0));
|
|
|
|
|
#endif
|
|
|
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
|
|
|
result = i2c_imx_read(i2c_imx, &msgs[i]);
|
|
|
|
|
else
|
|
|
|
|
result = i2c_imx_write(i2c_imx, &msgs[i]);
|
2010-03-23 23:28:28 +07:00
|
|
|
if (result)
|
|
|
|
|
goto fail0;
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
fail0:
|
|
|
|
|
/* Stop I2C transfer */
|
|
|
|
|
i2c_imx_stop(i2c_imx);
|
|
|
|
|
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
|
|
|
|
|
(result < 0) ? "error" : "success msg",
|
|
|
|
|
(result < 0) ? result : num);
|
|
|
|
|
return (result < 0) ? result : num;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 i2c_imx_func(struct i2c_adapter *adapter)
|
|
|
|
|
{
|
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct i2c_algorithm i2c_imx_algo = {
|
|
|
|
|
.master_xfer = i2c_imx_xfer,
|
|
|
|
|
.functionality = i2c_imx_func,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init i2c_imx_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
2012-09-14 14:19:00 +07:00
|
|
|
const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
|
|
|
|
|
&pdev->dev);
|
2009-01-30 15:32:28 +07:00
|
|
|
struct imx_i2c_struct *i2c_imx;
|
|
|
|
|
struct resource *res;
|
2011-09-08 14:09:34 +07:00
|
|
|
struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
|
2013-08-07 16:05:38 +07:00
|
|
|
const struct platform_device_id *imx_id;
|
2009-01-30 15:32:28 +07:00
|
|
|
void __iomem *base;
|
2012-07-08 18:11:43 +07:00
|
|
|
int irq, ret;
|
|
|
|
|
u32 bitrate;
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
dev_dbg(&pdev->dev, "<%s>\n", __func__);
|
|
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
|
if (irq < 0) {
|
|
|
|
|
dev_err(&pdev->dev, "can't get irq number\n");
|
|
|
|
|
return -ENOENT;
|
|
|
|
|
}
|
|
|
|
|
|
2013-05-10 15:16:54 +07:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-01-21 17:09:03 +07:00
|
|
|
base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
|
if (IS_ERR(base))
|
|
|
|
|
return PTR_ERR(base);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
2012-06-04 18:04:25 +07:00
|
|
|
i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
|
|
|
|
|
GFP_KERNEL);
|
2009-01-30 15:32:28 +07:00
|
|
|
if (!i2c_imx) {
|
|
|
|
|
dev_err(&pdev->dev, "can't allocate interface\n");
|
2012-06-04 18:04:25 +07:00
|
|
|
return -ENOMEM;
|
2009-03-31 18:52:54 +07:00
|
|
|
}
|
|
|
|
|
|
2012-09-14 14:19:00 +07:00
|
|
|
if (of_id)
|
2013-08-07 16:05:38 +07:00
|
|
|
imx_id = of_id->data;
|
|
|
|
|
else
|
|
|
|
|
imx_id = platform_get_device_id(pdev);
|
|
|
|
|
|
|
|
|
|
i2c_imx->devtype = imx_id->driver_data;
|
2012-09-14 14:19:00 +07:00
|
|
|
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Setup i2c_imx driver structure */
|
2012-04-19 22:31:01 +07:00
|
|
|
strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
|
2009-01-30 15:32:28 +07:00
|
|
|
i2c_imx->adapter.owner = THIS_MODULE;
|
|
|
|
|
i2c_imx->adapter.algo = &i2c_imx_algo;
|
|
|
|
|
i2c_imx->adapter.dev.parent = &pdev->dev;
|
|
|
|
|
i2c_imx->adapter.nr = pdev->id;
|
2011-09-08 14:09:35 +07:00
|
|
|
i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
|
2009-01-30 15:32:28 +07:00
|
|
|
i2c_imx->base = base;
|
|
|
|
|
|
|
|
|
|
/* Get I2C clock */
|
2012-07-07 01:31:32 +07:00
|
|
|
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
|
2009-01-30 15:32:28 +07:00
|
|
|
if (IS_ERR(i2c_imx->clk)) {
|
|
|
|
|
dev_err(&pdev->dev, "can't get I2C clock\n");
|
2012-06-04 18:04:25 +07:00
|
|
|
return PTR_ERR(i2c_imx->clk);
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
2013-08-07 16:05:37 +07:00
|
|
|
ret = clk_prepare_enable(i2c_imx->clk);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&pdev->dev, "can't enable I2C clock\n");
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Request IRQ */
|
2012-06-04 18:04:25 +07:00
|
|
|
ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
|
|
|
|
|
pdev->name, i2c_imx);
|
2009-01-30 15:32:28 +07:00
|
|
|
if (ret) {
|
2012-06-04 18:04:25 +07:00
|
|
|
dev_err(&pdev->dev, "can't claim irq %d\n", irq);
|
|
|
|
|
return ret;
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Init queue */
|
|
|
|
|
init_waitqueue_head(&i2c_imx->queue);
|
|
|
|
|
|
|
|
|
|
/* Set up adapter data */
|
|
|
|
|
i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
|
|
|
|
|
|
|
|
|
|
/* Set up clock divider */
|
2011-09-08 14:09:35 +07:00
|
|
|
bitrate = IMX_I2C_BIT_RATE;
|
|
|
|
|
ret = of_property_read_u32(pdev->dev.of_node,
|
|
|
|
|
"clock-frequency", &bitrate);
|
|
|
|
|
if (ret < 0 && pdata && pdata->bitrate)
|
|
|
|
|
bitrate = pdata->bitrate;
|
|
|
|
|
i2c_imx_set_clk(i2c_imx, bitrate);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
/* Set up chip registers to defaults */
|
2013-08-07 16:05:41 +07:00
|
|
|
imx_i2c_write_reg(IMX_I2CR_IEN_OPCODE ^ I2CR_IEN, i2c_imx, IMX_I2C_I2CR);
|
|
|
|
|
imx_i2c_write_reg(IMX_I2SR_CLR_OPCODE, i2c_imx, IMX_I2C_I2SR);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
/* Add I2C adapter */
|
|
|
|
|
ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
|
|
|
|
|
if (ret < 0) {
|
|
|
|
|
dev_err(&pdev->dev, "registration failed\n");
|
2012-06-04 18:04:25 +07:00
|
|
|
return ret;
|
2009-01-30 15:32:28 +07:00
|
|
|
}
|
|
|
|
|
|
2011-09-08 14:09:35 +07:00
|
|
|
of_i2c_register_devices(&i2c_imx->adapter);
|
|
|
|
|
|
2009-01-30 15:32:28 +07:00
|
|
|
/* Set up platform driver data */
|
|
|
|
|
platform_set_drvdata(pdev, i2c_imx);
|
2013-08-07 16:05:37 +07:00
|
|
|
clk_disable_unprepare(i2c_imx->clk);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
2012-06-04 18:04:25 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
|
2012-06-04 18:04:25 +07:00
|
|
|
res->start, res->end);
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
|
|
|
|
|
resource_size(res), res->start);
|
2009-01-30 15:32:28 +07:00
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
|
|
|
|
|
i2c_imx->adapter.name);
|
2012-08-02 03:38:14 +07:00
|
|
|
dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
return 0; /* Return OK */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int __exit i2c_imx_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
|
|
/* remove adapter */
|
|
|
|
|
dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
|
|
|
|
|
i2c_del_adapter(&i2c_imx->adapter);
|
|
|
|
|
|
|
|
|
|
/* setup chip registers to defaults */
|
2013-08-07 16:05:39 +07:00
|
|
|
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
|
|
|
|
|
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
|
|
|
|
|
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
|
|
|
|
|
imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver i2c_imx_driver = {
|
|
|
|
|
.remove = __exit_p(i2c_imx_remove),
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = DRIVER_NAME,
|
|
|
|
|
.owner = THIS_MODULE,
|
2011-09-08 14:09:35 +07:00
|
|
|
.of_match_table = i2c_imx_dt_ids,
|
2012-09-14 14:19:00 +07:00
|
|
|
},
|
|
|
|
|
.id_table = imx_i2c_devtype,
|
2009-01-30 15:32:28 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init i2c_adap_imx_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
|
|
|
|
|
}
|
2009-09-19 14:09:50 +07:00
|
|
|
subsys_initcall(i2c_adap_imx_init);
|
2009-01-30 15:32:28 +07:00
|
|
|
|
|
|
|
|
static void __exit i2c_adap_imx_exit(void)
|
|
|
|
|
{
|
|
|
|
|
platform_driver_unregister(&i2c_imx_driver);
|
|
|
|
|
}
|
|
|
|
|
module_exit(i2c_adap_imx_exit);
|
|
|
|
|
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_AUTHOR("Darius Augulis");
|
|
|
|
|
MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
|
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|