License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2013-10-08 11:50:06 +07:00
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/dts-v1/;
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2013-12-19 23:06:19 +07:00
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#include <dt-bindings/input/input.h>
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2013-10-08 11:50:06 +07:00
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#include "tegra124.dtsi"
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/ {
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model = "NVIDIA Tegra124 Venice2";
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compatible = "nvidia,venice2", "nvidia,tegra124";
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2013-12-20 01:32:15 +07:00
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aliases {
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2016-06-30 05:21:37 +07:00
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rtc0 = "/i2c@7000d000/pmic@40";
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rtc1 = "/rtc@7000e000";
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2014-11-12 03:49:30 +07:00
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serial0 = &uarta;
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2013-12-20 01:32:15 +07:00
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};
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2016-02-09 20:51:59 +07:00
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chosen {
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stdout-path = "serial0:115200n8";
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};
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2013-10-08 11:50:06 +07:00
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memory {
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2014-03-04 04:51:15 +07:00
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reg = <0x0 0x80000000 0x0 0x80000000>;
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2013-10-08 11:50:06 +07:00
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};
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2016-06-30 05:21:37 +07:00
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host1x@50000000 {
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hdmi@54280000 {
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2014-04-25 22:44:46 +07:00
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status = "okay";
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vdd-supply = <&vdd_3v3_hdmi>;
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pll-supply = <&vdd_hdmi_pll>;
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hdmi-supply = <&vdd_5v0_hdmi>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio =
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<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
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};
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2016-06-30 05:21:37 +07:00
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sor@54540000 {
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2014-02-28 23:40:24 +07:00
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status = "okay";
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nvidia,dpaux = <&dpaux>;
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nvidia,panel = <&panel>;
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};
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2016-06-30 05:21:37 +07:00
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dpaux@545c0000 {
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2014-02-28 23:40:24 +07:00
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vdd-supply = <&vdd_3v3_panel>;
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status = "okay";
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};
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};
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2015-07-01 16:13:46 +07:00
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gpu@0,57000000 {
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/*
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* Node left disabled on purpose - the bootloader will enable
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* it after having set the VPR up
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*/
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vdd-supply = <&vdd_gpu>;
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};
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2016-06-30 05:21:37 +07:00
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pinmux: pinmux@70000868 {
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ARM: tegra: rely on bootloader pinmux programming on Tegra124
The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:
- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.
Other methods such as:
- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
possible conflicting settings.
... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.
While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.
While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.
Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...
The following U-Boot commits fully initialize the pinmux:
Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.
Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-03 22:42:06 +07:00
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pinctrl-names = "boot";
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pinctrl-0 = <&pinmux_boot>;
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2013-12-09 17:33:51 +07:00
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ARM: tegra: rely on bootloader pinmux programming on Tegra124
The defined mechanism for programming the Tegra pinmux is to perform all
of the following at once in order, before using any I/O controller that
is affected by the pinmux:
- Set the CLAMP_INPUTS_WHEN_TRISTATED PMC register bit.
- Set up any GPIO pins to their "initial" state.
- Program all pinmux settings in one go.
Other methods such as:
- Not setting CLAMP_INPUTS_WHEN_TRISTATED.
- Not setting GPIOs to their "initial" state before programming the
pinmux settings of the related pin, in particular the mux function.
- Not programming the entire pinmux at once, in order to avoid
possible conflicting settings.
... are not qualified or supported by NVIDIA ASIC/syseng. They could
cause glitches or undesired output levels on some pins, or controller
malfunction.
While we've been getting away with doing something different on many
Tegra boards without issue, I believe we've just been getting lucky.
I'd like to switch all Tegra124 systems to the correct scheme now so
they provide the right example to follow, and require that any new
boards we support upstream work in the same fashion.
While it would be nice to update boards containing older SoCs for
consistency, I don't anticipate doing so. It's too much churn to change
at this time. At least with all Tegra124 boards converted, the most
recent boards provide the correct example.
Since the bootloader needs to reprogram the pinmux to access certain
peripherals, it must program the entire pinmux due to the supported
rules above. As such, there is no need to program any part of the pinmux
from the kernel, unless dynamic pinmuxing is used. Given this, we couuld
simply remove the pinmux "default" state from the DT entirely. However,
some bootloaders parse the DT to perform their initial pinmux setup, so
it's useful to keep the pinmux data in DT. To allow this while avoiding
redundant work in the kernel, rename the "default" state to "boot". The
kernel won't apply this, but bootloaders can still look for this state
name and apply it. Note however that the DT provides zero information
about the required initial GPIO setup, so bootloaders using this approach
are not likely to operate correctly without an additional GPIO
initialization table somewhere. Previous discussions on the DT mailing
list have rejected adding such a table to DT...
The following U-Boot commits fully initialize the pinmux:
Jetson TK1: 4ff213b8e478 ARM: tegra: clamp inputs on Jetson TK1
Venice2: 3365479ce78a ARM: tegra: Venice2 pinmux spreadsheet updates
Both are part of U-Boot v2014.07 and later.
Without those commits, the only fallout I see from this change is that
HDMI on Venice2 no longer works. Given the very small user-base of this
platform, I feel that requiring a bootloader update is reasonable.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-09-03 22:42:06 +07:00
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pinmux_boot: common {
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2013-12-09 17:33:51 +07:00
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dap_mclk1_pw4 {
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nvidia,pins = "dap_mclk1_pw4";
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nvidia,function = "extperiph1";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dap1_din_pn1 {
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2013-12-18 19:52:58 +07:00
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nvidia,pins = "dap1_din_pn1";
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nvidia,function = "i2s0";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap1_dout_pn2 {
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nvidia,pins = "dap1_dout_pn2",
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2013-12-09 17:33:51 +07:00
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"dap1_fs_pn0",
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"dap1_sclk_pn3";
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nvidia,function = "i2s0";
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2013-12-18 19:52:58 +07:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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2013-12-09 17:33:51 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap2_din_pa4 {
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2013-12-18 19:52:58 +07:00
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nvidia,pins = "dap2_din_pa4";
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2013-12-09 17:33:51 +07:00
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nvidia,function = "i2s1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2013-12-13 04:40:30 +07:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
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};
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2013-12-18 19:52:58 +07:00
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dap2_dout_pa5 {
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nvidia,pins = "dap2_dout_pa5",
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"dap2_fs_pa2",
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"dap2_sclk_pa3";
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nvidia,function = "i2s1";
|
2013-12-09 17:33:51 +07:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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2013-12-18 19:52:58 +07:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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2013-12-09 17:33:51 +07:00
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};
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2013-12-18 19:52:58 +07:00
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dvfs_pwm_px0 {
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nvidia,pins = "dvfs_pwm_px0",
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"dvfs_clk_px2";
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2013-12-09 17:33:51 +07:00
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nvidia,function = "cldvfs";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_clk_py0 {
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nvidia,pins = "ulpi_clk_py0",
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"ulpi_nxt_py2",
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"ulpi_stp_py3";
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nvidia,function = "spi1";
|
2013-12-18 19:52:58 +07:00
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_dir_py1 {
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nvidia,pins = "ulpi_dir_py1";
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nvidia,function = "spi1";
|
2013-12-09 17:33:51 +07:00
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-18 19:52:58 +07:00
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2013-12-09 17:33:51 +07:00
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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cam_i2c_scl_pbb1 {
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nvidia,pins = "cam_i2c_scl_pbb1",
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"cam_i2c_sda_pbb2";
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nvidia,function = "i2c3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gen2_i2c_scl_pt5 {
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nvidia,pins = "gen2_i2c_scl_pt5",
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"gen2_i2c_sda_pt6";
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nvidia,function = "i2c2";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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pg4 {
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nvidia,pins = "pg4",
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"pg5",
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"pg6",
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"pi3";
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nvidia,function = "spi4";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
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};
|
2013-12-18 19:52:58 +07:00
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pg7 {
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nvidia,pins = "pg7";
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nvidia,function = "spi4";
|
2013-12-09 17:33:51 +07:00
|
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
|
|
|
|
ph1 {
|
|
|
|
|
nvidia,pins = "ph1";
|
|
|
|
|
nvidia,function = "pwm1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
pk0 {
|
|
|
|
|
nvidia,pins = "pk0",
|
|
|
|
|
"kb_row15_ps7",
|
|
|
|
|
"clk_32k_out_pa0";
|
|
|
|
|
nvidia,function = "soc";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
2013-12-13 23:25:04 +07:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-13 23:25:04 +07:00
|
|
|
};
|
2013-12-09 17:33:51 +07:00
|
|
|
sdmmc1_clk_pz0 {
|
2014-03-21 07:06:01 +07:00
|
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,function = "sdmmc1";
|
2014-03-21 07:06:01 +07:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
sdmmc1_cmd_pz1 {
|
|
|
|
|
nvidia,pins = "sdmmc1_cmd_pz1",
|
|
|
|
|
"sdmmc1_dat0_py7",
|
|
|
|
|
"sdmmc1_dat1_py6",
|
|
|
|
|
"sdmmc1_dat2_py5",
|
|
|
|
|
"sdmmc1_dat3_py4";
|
|
|
|
|
nvidia,function = "sdmmc1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-09 17:33:51 +07:00
|
|
|
sdmmc3_clk_pa6 {
|
|
|
|
|
nvidia,pins = "sdmmc3_clk_pa6";
|
|
|
|
|
nvidia,function = "sdmmc3";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc3_cmd_pa7 {
|
|
|
|
|
nvidia,pins = "sdmmc3_cmd_pa7",
|
|
|
|
|
"sdmmc3_dat0_pb7",
|
|
|
|
|
"sdmmc3_dat1_pb6",
|
|
|
|
|
"sdmmc3_dat2_pb5",
|
|
|
|
|
"sdmmc3_dat3_pb4",
|
|
|
|
|
"sdmmc3_clk_lb_out_pee4",
|
|
|
|
|
"sdmmc3_clk_lb_in_pee5";
|
|
|
|
|
nvidia,function = "sdmmc3";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc4_clk_pcc4 {
|
|
|
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
sdmmc4_cmd_pt7 {
|
|
|
|
|
nvidia,pins = "sdmmc4_cmd_pt7",
|
|
|
|
|
"sdmmc4_dat0_paa0",
|
|
|
|
|
"sdmmc4_dat1_paa1",
|
|
|
|
|
"sdmmc4_dat2_paa2",
|
|
|
|
|
"sdmmc4_dat3_paa3",
|
|
|
|
|
"sdmmc4_dat4_paa4",
|
|
|
|
|
"sdmmc4_dat5_paa5",
|
|
|
|
|
"sdmmc4_dat6_paa6",
|
|
|
|
|
"sdmmc4_dat7_paa7";
|
|
|
|
|
nvidia,function = "sdmmc4";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pwr_i2c_scl_pz6 {
|
|
|
|
|
nvidia,pins = "pwr_i2c_scl_pz6",
|
|
|
|
|
"pwr_i2c_sda_pz7";
|
|
|
|
|
nvidia,function = "i2cpwr";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
jtag_rtck {
|
|
|
|
|
nvidia,pins = "jtag_rtck";
|
|
|
|
|
nvidia,function = "rtck";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk_32k_in {
|
|
|
|
|
nvidia,pins = "clk_32k_in";
|
|
|
|
|
nvidia,function = "clk";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
core_pwr_req {
|
|
|
|
|
nvidia,pins = "core_pwr_req";
|
|
|
|
|
nvidia,function = "pwron";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
cpu_pwr_req {
|
|
|
|
|
nvidia,pins = "cpu_pwr_req";
|
|
|
|
|
nvidia,function = "cpu";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pwr_int_n {
|
|
|
|
|
nvidia,pins = "pwr_int_n";
|
|
|
|
|
nvidia,function = "pmi";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
reset_out_n {
|
|
|
|
|
nvidia,pins = "reset_out_n";
|
|
|
|
|
nvidia,function = "reset_out_n";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
clk3_out_pee0 {
|
|
|
|
|
nvidia,pins = "clk3_out_pee0";
|
|
|
|
|
nvidia,function = "extperiph3";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
dap4_din_pp5 {
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,pins = "dap4_din_pp5";
|
|
|
|
|
nvidia,function = "i2s3";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
dap4_dout_pp6 {
|
|
|
|
|
nvidia,pins = "dap4_dout_pp6",
|
2013-12-09 17:33:51 +07:00
|
|
|
"dap4_fs_pp4",
|
|
|
|
|
"dap4_sclk_pp7";
|
|
|
|
|
nvidia,function = "i2s3";
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
gen1_i2c_sda_pc5 {
|
|
|
|
|
nvidia,pins = "gen1_i2c_sda_pc5",
|
|
|
|
|
"gen1_i2c_scl_pc4";
|
|
|
|
|
nvidia,function = "i2c1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
uart2_cts_n_pj5 {
|
|
|
|
|
nvidia,pins = "uart2_cts_n_pj5";
|
|
|
|
|
nvidia,function = "uartb";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-13 04:40:30 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
uart2_rts_n_pj6 {
|
|
|
|
|
nvidia,pins = "uart2_rts_n_pj6";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,function = "uartb";
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
uart2_rxd_pc3 {
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,pins = "uart2_rxd_pc3";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,function = "irda";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
uart2_txd_pc2 {
|
|
|
|
|
nvidia,pins = "uart2_txd_pc2";
|
|
|
|
|
nvidia,function = "irda";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-09 17:33:51 +07:00
|
|
|
uart3_cts_n_pa1 {
|
|
|
|
|
nvidia,pins = "uart3_cts_n_pa1",
|
2013-12-18 19:52:58 +07:00
|
|
|
"uart3_rxd_pw7";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,function = "uartc";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
uart3_rts_n_pc0 {
|
|
|
|
|
nvidia,pins = "uart3_rts_n_pc0",
|
|
|
|
|
"uart3_txd_pw6";
|
|
|
|
|
nvidia,function = "uartc";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
2013-12-09 17:33:51 +07:00
|
|
|
hdmi_cec_pee3 {
|
|
|
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
|
|
|
nvidia,function = "cec";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
hdmi_int_pn7 {
|
|
|
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
|
|
|
nvidia,function = "rsvd1";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
|
|
|
|
ddc_scl_pv4 {
|
|
|
|
|
nvidia,pins = "ddc_scl_pv4",
|
|
|
|
|
"ddc_sda_pv5";
|
|
|
|
|
nvidia,function = "i2c4";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
pj7 {
|
|
|
|
|
nvidia,pins = "pj7",
|
|
|
|
|
"pk7";
|
|
|
|
|
nvidia,function = "uartd";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
pb0 {
|
|
|
|
|
nvidia,pins = "pb0",
|
|
|
|
|
"pb1";
|
|
|
|
|
nvidia,function = "uartd";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ph0 {
|
|
|
|
|
nvidia,pins = "ph0";
|
|
|
|
|
nvidia,function = "pwm0";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row10_ps2 {
|
|
|
|
|
nvidia,pins = "kb_row10_ps2";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row9_ps1 {
|
|
|
|
|
nvidia,pins = "kb_row9_ps1";
|
|
|
|
|
nvidia,function = "uarta";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_row6_pr6 {
|
|
|
|
|
nvidia,pins = "kb_row6_pr6";
|
|
|
|
|
nvidia,function = "displaya_alt";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
|
|
|
|
usb_vbus_en0_pn4 {
|
2014-02-25 22:45:04 +07:00
|
|
|
nvidia,pins = "usb_vbus_en0_pn4",
|
|
|
|
|
"usb_vbus_en1_pn5";
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,function = "usb";
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
2014-02-25 22:45:04 +07:00
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
2013-12-18 19:52:58 +07:00
|
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
|
|
|
|
drive_sdio1 {
|
|
|
|
|
nvidia,pins = "drive_sdio1";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull-down-strength = <32>;
|
|
|
|
|
nvidia,pull-up-strength = <42>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
};
|
|
|
|
|
drive_sdio3 {
|
|
|
|
|
nvidia,pins = "drive_sdio3";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,pull-down-strength = <20>;
|
|
|
|
|
nvidia,pull-up-strength = <36>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
};
|
|
|
|
|
drive_gma {
|
|
|
|
|
nvidia,pins = "drive_gma";
|
|
|
|
|
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
|
|
|
|
nvidia,pull-down-strength = <1>;
|
|
|
|
|
nvidia,pull-up-strength = <2>;
|
|
|
|
|
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
|
|
|
|
nvidia,drive-type = <1>;
|
|
|
|
|
};
|
2013-12-18 19:52:58 +07:00
|
|
|
als_irq_l {
|
|
|
|
|
nvidia,pins = "gpio_x3_aud_px3";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
codec_irq_l {
|
|
|
|
|
nvidia,pins = "ph4";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
lcd_bl_en {
|
|
|
|
|
nvidia,pins = "ph2";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
touch_irq_l {
|
|
|
|
|
nvidia,pins = "gpio_w3_aud_pw3";
|
|
|
|
|
nvidia,function = "spi6";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
tpm_davint_l {
|
|
|
|
|
nvidia,pins = "ph6";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_irq_l {
|
|
|
|
|
nvidia,pins = "pk2";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_reset_l {
|
|
|
|
|
nvidia,pins = "pk4";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ts_shdn_l {
|
|
|
|
|
nvidia,pins = "pk1";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ph7 {
|
|
|
|
|
nvidia,pins = "ph7";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
kb_col0_ap {
|
|
|
|
|
nvidia,pins = "kb_col0_pq0";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
lid_open {
|
|
|
|
|
nvidia,pins = "kb_row4_pr4";
|
|
|
|
|
nvidia,function = "rsvd3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
en_vdd_sd {
|
|
|
|
|
nvidia,pins = "kb_row0_pr0";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
ac_ok {
|
|
|
|
|
nvidia,pins = "pj0";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
sensor_irq_l {
|
|
|
|
|
nvidia,pins = "pi6";
|
|
|
|
|
nvidia,function = "gmi";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
wifi_en {
|
|
|
|
|
nvidia,pins = "gpio_x7_aud_px7";
|
|
|
|
|
nvidia,function = "rsvd4";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
};
|
|
|
|
|
wifi_rst_l {
|
|
|
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
|
|
|
nvidia,function = "dap";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
|
|
|
|
hp_det_l {
|
|
|
|
|
nvidia,pins = "ulpi_data1_po2";
|
|
|
|
|
nvidia,function = "spi3";
|
|
|
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
|
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
|
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
|
|
|
};
|
2013-12-09 17:33:51 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
serial@70006000 {
|
2013-10-08 11:50:06 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
pwm@7000a000 {
|
2013-11-18 23:00:35 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
i2c@7000c000 {
|
2013-12-04 06:44:35 +07:00
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
2013-12-04 07:26:12 +07:00
|
|
|
|
|
|
|
|
acodec: audio-codec@10 {
|
|
|
|
|
compatible = "maxim,max98090";
|
|
|
|
|
reg = <0x10>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
2018-02-10 08:33:23 +07:00
|
|
|
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
|
2013-12-04 07:26:12 +07:00
|
|
|
};
|
2013-12-04 06:44:35 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
i2c@7000c400 {
|
2013-12-04 06:44:35 +07:00
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
2014-09-02 22:57:09 +07:00
|
|
|
|
|
|
|
|
trackpad@4b {
|
|
|
|
|
compatible = "atmel,maxtouch";
|
|
|
|
|
reg = <0x4b>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
|
linux,gpio-keymap = <0 0 0 BTN_LEFT>;
|
|
|
|
|
};
|
2013-12-04 06:44:35 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
i2c@7000c500 {
|
2013-12-04 06:44:35 +07:00
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
hdmi_ddc: i2c@7000c700 {
|
2013-12-04 06:44:35 +07:00
|
|
|
status = "okay";
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
i2c@7000d000 {
|
2013-12-04 06:44:35 +07:00
|
|
|
status = "okay";
|
2013-12-18 19:52:59 +07:00
|
|
|
clock-frequency = <400000>;
|
|
|
|
|
|
2014-02-28 23:40:28 +07:00
|
|
|
pmic: pmic@40 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "ams,as3722";
|
|
|
|
|
reg = <0x40>;
|
|
|
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
|
2014-01-09 18:01:48 +07:00
|
|
|
ams,system-power-controller;
|
|
|
|
|
|
2013-12-18 19:52:59 +07:00
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&as3722_default>;
|
|
|
|
|
|
|
|
|
|
as3722_default: pinmux {
|
|
|
|
|
gpio0 {
|
|
|
|
|
pins = "gpio0";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
bias-pull-down;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1_2_4_7 {
|
|
|
|
|
pins = "gpio1", "gpio2", "gpio4", "gpio7";
|
|
|
|
|
function = "gpio";
|
|
|
|
|
bias-pull-up;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3_6 {
|
|
|
|
|
pins = "gpio3", "gpio6";
|
|
|
|
|
bias-high-impedance;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5 {
|
|
|
|
|
pins = "gpio5";
|
|
|
|
|
function = "clk32k-out";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
regulators {
|
2014-02-28 23:40:20 +07:00
|
|
|
vsup-sd2-supply = <&vdd_5v0_sys>;
|
|
|
|
|
vsup-sd3-supply = <&vdd_5v0_sys>;
|
|
|
|
|
vsup-sd4-supply = <&vdd_5v0_sys>;
|
|
|
|
|
vsup-sd5-supply = <&vdd_5v0_sys>;
|
|
|
|
|
vin-ldo0-supply = <&vdd_1v35_lp0>;
|
|
|
|
|
vin-ldo1-6-supply = <&vdd_3v3_run>;
|
|
|
|
|
vin-ldo2-5-7-supply = <&vddio_1v8>;
|
|
|
|
|
vin-ldo3-4-supply = <&vdd_3v3_sys>;
|
|
|
|
|
vin-ldo9-10-supply = <&vdd_5v0_sys>;
|
|
|
|
|
vin-ldo11-supply = <&vdd_3v3_run>;
|
2013-12-18 19:52:59 +07:00
|
|
|
|
|
|
|
|
sd0 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDD_CPU_AP";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <700000>;
|
|
|
|
|
regulator-max-microvolt = <1400000>;
|
|
|
|
|
regulator-min-microamp = <3500000>;
|
|
|
|
|
regulator-max-microamp = <3500000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2014-07-10 01:53:17 +07:00
|
|
|
ams,ext-control = <2>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd1 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDD_CORE";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <700000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-min-microamp = <2500000>;
|
|
|
|
|
regulator-max-microamp = <2500000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2014-07-10 01:53:17 +07:00
|
|
|
ams,ext-control = <1>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_1v35_lp0: sd2 {
|
|
|
|
|
regulator-name = "+1.35V_LP0(sd2)";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1350000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sd3 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.35V_LP0(sd3)";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1350000>;
|
|
|
|
|
regulator-max-microvolt = <1350000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
2014-04-25 22:44:46 +07:00
|
|
|
vdd_1v05_run: sd4 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.05V_RUN";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vddio_1v8: sd5 {
|
|
|
|
|
regulator-name = "+1.8V_VDDIO";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-01 16:13:46 +07:00
|
|
|
vdd_gpu: sd6 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDD_GPU_AP";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <650000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
regulator-min-microamp = <3500000>;
|
|
|
|
|
regulator-max-microamp = <3500000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
2016-02-04 22:54:30 +07:00
|
|
|
avdd_1v05_run: ldo0 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.05V_RUN_AVDD";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
2014-07-10 01:53:17 +07:00
|
|
|
ams,ext-control = <1>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo1 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.8V_RUN_CAM";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo2 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.2V_GEN_AVDD";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo3 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.00V_LP0_VDD_RTC";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1000000>;
|
|
|
|
|
regulator-max-microvolt = <1000000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
ams,enable-tracking;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:26 +07:00
|
|
|
vdd_run_cam: ldo4 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+3.3V_RUN_CAM";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo5 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.2V_RUN_CAM_FRONT";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1200000>;
|
|
|
|
|
regulator-max-microvolt = <1200000>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:21 +07:00
|
|
|
vddio_sdmmc3: ldo6 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDDIO_SDMMC3";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo7 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.05V_RUN_CAM_REAR";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo9 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+2.8V_RUN_TOUCH";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo10 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+2.8V_RUN_CAM_AF";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
|
regulator-max-microvolt = <2800000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo11 {
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+1.8V_RUN_VPP_FUSE";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-04 06:44:35 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
spi@7000d400 {
|
2013-12-19 23:06:19 +07:00
|
|
|
status = "okay";
|
|
|
|
|
|
2014-06-05 05:20:19 +07:00
|
|
|
cros_ec: cros-ec@0 {
|
2013-12-19 23:06:19 +07:00
|
|
|
compatible = "google,cros-ec-spi";
|
|
|
|
|
spi-max-frequency = <4000000>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
|
reg = <0>;
|
|
|
|
|
|
|
|
|
|
google,cros-ec-spi-msg-delay = <2000>;
|
2014-05-01 00:44:10 +07:00
|
|
|
|
|
|
|
|
i2c-tunnel {
|
|
|
|
|
compatible = "google,cros-ec-i2c-tunnel";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
google,remote-bus = <0>;
|
|
|
|
|
|
|
|
|
|
charger: bq24735@9 {
|
|
|
|
|
compatible = "ti,bq24735";
|
|
|
|
|
reg = <0x9>;
|
|
|
|
|
interrupt-parent = <&gpio>;
|
|
|
|
|
interrupts = <TEGRA_GPIO(J, 0)
|
2018-02-10 08:33:23 +07:00
|
|
|
IRQ_TYPE_EDGE_BOTH>;
|
2014-05-01 00:44:10 +07:00
|
|
|
ti,ac-detect-gpios = <&gpio
|
|
|
|
|
TEGRA_GPIO(J, 0)
|
|
|
|
|
GPIO_ACTIVE_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
battery: sbs-battery@b {
|
|
|
|
|
compatible = "sbs,sbs-battery";
|
|
|
|
|
reg = <0xb>;
|
|
|
|
|
sbs,i2c-retry-count = <2>;
|
|
|
|
|
sbs,poll-retry-count = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-19 23:06:19 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
spi@7000da00 {
|
2014-02-19 05:03:21 +07:00
|
|
|
status = "okay";
|
|
|
|
|
spi-max-frequency = <25000000>;
|
|
|
|
|
spi-flash@0 {
|
|
|
|
|
compatible = "winbond,w25q32dw";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
spi-max-frequency = <20000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
pmc@7000e400 {
|
2013-10-08 11:50:06 +07:00
|
|
|
nvidia,invert-interrupt;
|
2013-10-11 16:58:39 +07:00
|
|
|
nvidia,suspend-mode = <1>;
|
|
|
|
|
nvidia,cpu-pwr-good-time = <500>;
|
|
|
|
|
nvidia,cpu-pwr-off-time = <300>;
|
|
|
|
|
nvidia,core-pwr-good-time = <641 3845>;
|
|
|
|
|
nvidia,core-pwr-off-time = <61036>;
|
|
|
|
|
nvidia,core-power-req-active-high;
|
|
|
|
|
nvidia,sys-clock-req-active-high;
|
2013-10-08 11:50:06 +07:00
|
|
|
};
|
2013-10-08 14:47:40 +07:00
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
hda@70030000 {
|
2014-05-20 09:35:46 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb@70090000 {
|
|
|
|
|
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
|
|
|
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
|
|
|
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
|
|
|
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
|
|
|
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
|
2016-02-04 22:54:30 +07:00
|
|
|
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
|
|
|
|
|
|
|
|
|
|
avddio-pex-supply = <&vdd_1v05_run>;
|
|
|
|
|
dvddio-pex-supply = <&vdd_1v05_run>;
|
|
|
|
|
avdd-usb-supply = <&vdd_3v3_lp0>;
|
|
|
|
|
avdd-pll-utmip-supply = <&vddio_1v8>;
|
|
|
|
|
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
|
|
|
|
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
|
|
|
|
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
|
|
|
|
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
padctl@7009f000 {
|
2016-02-04 22:54:30 +07:00
|
|
|
pads {
|
|
|
|
|
usb2 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
lanes {
|
|
|
|
|
usb2-0 {
|
|
|
|
|
nvidia,function = "xusb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb2-1 {
|
|
|
|
|
nvidia,function = "xusb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb2-2 {
|
|
|
|
|
nvidia,function = "xusb";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie {
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
lanes {
|
|
|
|
|
pcie-0 {
|
|
|
|
|
nvidia,function = "usb3-ss";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie-1 {
|
|
|
|
|
nvidia,function = "usb3-ss";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ports {
|
|
|
|
|
usb2-0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
mode = "otg";
|
|
|
|
|
|
|
|
|
|
vbus-supply = <&vdd_usb1_vbus>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb2-1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
mode = "host";
|
|
|
|
|
|
|
|
|
|
vbus-supply = <&vdd_run_cam>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb2-2 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
mode = "host";
|
|
|
|
|
|
|
|
|
|
vbus-supply = <&vdd_usb3_vbus>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3-0 {
|
|
|
|
|
nvidia,usb2-companion = <0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3-1 {
|
|
|
|
|
nvidia,usb2-companion = <2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
sdhci@700b0400 {
|
2013-11-01 06:23:05 +07:00
|
|
|
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
|
2014-04-29 01:10:26 +07:00
|
|
|
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
|
2013-11-01 06:23:05 +07:00
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <4>;
|
2014-04-17 06:08:39 +07:00
|
|
|
vqmmc-supply = <&vddio_sdmmc3>;
|
2013-11-01 06:23:05 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
sdhci@700b0600 {
|
2013-11-01 06:23:05 +07:00
|
|
|
status = "okay";
|
|
|
|
|
bus-width = <8>;
|
2014-07-18 17:11:19 +07:00
|
|
|
non-removable;
|
2013-11-01 06:23:05 +07:00
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
ahub@70300000 {
|
|
|
|
|
i2s@70301100 {
|
2013-12-04 07:26:12 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb@7d000000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb-phy@7d000000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vdd_usb1_vbus>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb@7d004000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb-phy@7d004000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vdd_run_cam>;
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb@7d008000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-30 05:21:37 +07:00
|
|
|
usb-phy@7d008000 {
|
2014-02-28 23:40:26 +07:00
|
|
|
status = "okay";
|
|
|
|
|
vbus-supply = <&vdd_usb3_vbus>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:24 +07:00
|
|
|
backlight: backlight {
|
|
|
|
|
compatible = "pwm-backlight";
|
|
|
|
|
|
|
|
|
|
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
power-supply = <&vdd_led>;
|
|
|
|
|
pwms = <&pwm 1 1000000>;
|
|
|
|
|
|
|
|
|
|
brightness-levels = <0 4 8 16 32 64 128 255>;
|
|
|
|
|
default-brightness-level = <6>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-08 14:47:40 +07:00
|
|
|
clocks {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
clk32k_in: clock@0 {
|
|
|
|
|
compatible = "fixed-clock";
|
2014-02-28 23:40:27 +07:00
|
|
|
reg = <0>;
|
2013-10-08 14:47:40 +07:00
|
|
|
#clock-cells = <0>;
|
|
|
|
|
clock-frequency = <32768>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-04 07:26:12 +07:00
|
|
|
|
2013-12-19 23:06:20 +07:00
|
|
|
gpio-keys {
|
|
|
|
|
compatible = "gpio-keys";
|
|
|
|
|
|
|
|
|
|
power {
|
|
|
|
|
label = "Power";
|
|
|
|
|
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
|
|
|
|
|
linux,code = <KEY_POWER>;
|
|
|
|
|
debounce-interval = <10>;
|
2016-02-09 04:55:43 +07:00
|
|
|
wakeup-source;
|
2013-12-19 23:06:20 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:24 +07:00
|
|
|
panel: panel {
|
|
|
|
|
compatible = "lg,lp129qe", "simple-panel";
|
|
|
|
|
|
|
|
|
|
backlight = <&backlight>;
|
|
|
|
|
ddc-i2c-bus = <&dpaux>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-18 19:52:59 +07:00
|
|
|
regulators {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_mux: regulator@0 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <0>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDD_MUX";
|
|
|
|
|
regulator-min-microvolt = <12000000>;
|
|
|
|
|
regulator-max-microvolt = <12000000>;
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-always-on;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-boot-on;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_5v0_sys: regulator@1 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <1>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+5V_SYS";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_mux>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_3v3_sys: regulator@2 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <2>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+3.3V_SYS";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
vin-supply = <&vdd_mux>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_3v3_run: regulator@3 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <3>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+3.3V_RUN";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2014-04-16 05:27:01 +07:00
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
2014-02-28 23:40:28 +07:00
|
|
|
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
|
2013-12-18 19:52:59 +07:00
|
|
|
enable-active-high;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_3v3_sys>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_3v3_hdmi: regulator@4 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <4>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_3v3_run>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_led: regulator@5 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <5>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+VDD_LED";
|
2014-07-18 17:11:44 +07:00
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2014-02-28 23:40:20 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
|
2013-12-18 19:52:59 +07:00
|
|
|
enable-active-high;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_mux>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_5v0_ts: regulator@6 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <6>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+5V_VDD_TS_SW";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
regulator-boot-on;
|
2014-02-28 23:40:20 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
|
2013-12-18 19:52:59 +07:00
|
|
|
enable-active-high;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_usb1_vbus: regulator@7 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <7>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+5V_USB_HS";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
2014-02-28 23:40:20 +07:00
|
|
|
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
|
2013-12-18 19:52:59 +07:00
|
|
|
enable-active-high;
|
|
|
|
|
gpio-open-drain;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2014-02-28 23:40:20 +07:00
|
|
|
vdd_usb3_vbus: regulator@8 {
|
2013-12-18 19:52:59 +07:00
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <8>;
|
2014-02-28 23:40:20 +07:00
|
|
|
regulator-name = "+5V_USB_SS";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
gpio-open-drain;
|
|
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_3v3_panel: regulator@9 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <9>;
|
|
|
|
|
regulator-name = "+3.3V_PANEL";
|
2013-12-18 19:52:59 +07:00
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
2014-02-28 23:40:28 +07:00
|
|
|
gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
|
2014-02-28 23:40:20 +07:00
|
|
|
enable-active-high;
|
|
|
|
|
vin-supply = <&vdd_3v3_run>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_3v3_lp0: regulator@10 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <10>;
|
|
|
|
|
regulator-name = "+3.3V_LP0";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
/*
|
|
|
|
|
* TODO: find a way to wire this up with the USB EHCI
|
|
|
|
|
* controllers so that it can be enabled on demand.
|
|
|
|
|
*/
|
|
|
|
|
regulator-always-on;
|
2014-02-28 23:40:28 +07:00
|
|
|
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
|
2013-12-18 19:52:59 +07:00
|
|
|
enable-active-high;
|
2014-02-28 23:40:20 +07:00
|
|
|
vin-supply = <&vdd_3v3_sys>;
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
2014-04-25 22:44:46 +07:00
|
|
|
|
|
|
|
|
vdd_hdmi_pll: regulator@11 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <11>;
|
|
|
|
|
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
|
|
|
|
|
regulator-min-microvolt = <1050000>;
|
|
|
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
|
|
|
|
|
vin-supply = <&vdd_1v05_run>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vdd_5v0_hdmi: regulator@12 {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
reg = <12>;
|
|
|
|
|
regulator-name = "+5V_HDMI_CON";
|
|
|
|
|
regulator-min-microvolt = <5000000>;
|
|
|
|
|
regulator-max-microvolt = <5000000>;
|
|
|
|
|
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
|
|
|
|
|
enable-active-high;
|
|
|
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
|
|
|
};
|
2013-12-18 19:52:59 +07:00
|
|
|
};
|
|
|
|
|
|
2013-12-04 07:26:12 +07:00
|
|
|
sound {
|
|
|
|
|
compatible = "nvidia,tegra-audio-max98090-venice2",
|
|
|
|
|
"nvidia,tegra-audio-max98090";
|
|
|
|
|
nvidia,model = "NVIDIA Tegra Venice2";
|
|
|
|
|
|
|
|
|
|
nvidia,audio-routing =
|
|
|
|
|
"Headphones", "HPR",
|
|
|
|
|
"Headphones", "HPL",
|
|
|
|
|
"Speakers", "SPKR",
|
|
|
|
|
"Speakers", "SPKL",
|
|
|
|
|
"Mic Jack", "MICBIAS",
|
|
|
|
|
"IN34", "Mic Jack";
|
|
|
|
|
|
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
|
|
|
nvidia,audio-codec = <&acodec>;
|
|
|
|
|
|
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
|
|
|
|
|
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
|
|
|
|
<&tegra_car TEGRA124_CLK_EXTERN1>;
|
|
|
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
|
|
|
};
|
2013-10-08 11:50:06 +07:00
|
|
|
};
|
2014-06-05 05:20:19 +07:00
|
|
|
|
|
|
|
|
#include "cros-ec-keyboard.dtsi"
|