2018-09-25 14:34:05 +07:00
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/* SPDX-License-Identifier: GPL-2.0
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*
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2016-05-04 19:32:56 +07:00
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* R-Car Gen3 Clock Pulse Generator
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*
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2018-07-11 18:54:30 +07:00
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* Copyright (C) 2015-2018 Glider bvba
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2019-03-25 23:35:50 +07:00
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* Copyright (C) 2018 Renesas Electronics Corp.
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2016-05-04 19:32:56 +07:00
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*
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*/
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#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
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#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
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enum rcar_gen3_clk_types {
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CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_GEN3_PLL0,
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CLK_TYPE_GEN3_PLL1,
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CLK_TYPE_GEN3_PLL2,
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CLK_TYPE_GEN3_PLL3,
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CLK_TYPE_GEN3_PLL4,
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CLK_TYPE_GEN3_SD,
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CLK_TYPE_GEN3_R,
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2018-07-11 19:19:47 +07:00
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CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
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2018-01-30 01:01:49 +07:00
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CLK_TYPE_GEN3_Z,
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2018-01-30 01:01:50 +07:00
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CLK_TYPE_GEN3_Z2,
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2018-07-11 18:14:44 +07:00
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CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
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2018-07-11 18:54:30 +07:00
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CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
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2019-01-23 02:59:35 +07:00
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CLK_TYPE_GEN3_RPCSRC,
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CLK_TYPE_GEN3_RPC,
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CLK_TYPE_GEN3_RPCD2,
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2018-09-02 03:12:28 +07:00
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/* SoC specific definitions start here */
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CLK_TYPE_GEN3_SOC_BASE,
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2016-05-04 19:32:56 +07:00
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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2018-07-11 19:19:47 +07:00
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#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
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(_parent0) << 16 | (_parent1), \
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.div = (_div0) << 16 | (_div1), .offset = _md)
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2017-07-19 22:39:54 +07:00
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#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
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_div_clean) \
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2018-07-11 19:19:47 +07:00
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DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
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_parent_clean, _div_clean)
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2018-07-11 18:14:44 +07:00
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#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
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2017-07-19 22:39:54 +07:00
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2018-07-11 18:54:30 +07:00
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#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
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(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
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2017-07-19 22:39:54 +07:00
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2019-03-25 23:35:51 +07:00
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#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
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DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
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2019-03-25 23:35:50 +07:00
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2016-05-04 19:32:56 +07:00
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struct rcar_gen3_cpg_pll_config {
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2017-07-19 21:30:45 +07:00
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u8 extal_div;
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u8 pll1_mult;
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u8 pll1_div;
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u8 pll3_mult;
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u8 pll3_div;
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2018-07-11 18:14:44 +07:00
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u8 osc_prediv;
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2016-05-04 19:32:56 +07:00
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};
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2019-01-23 02:59:35 +07:00
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#define CPG_RPCCKCR 0x238
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2016-05-04 19:32:56 +07:00
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#define CPG_RCKCR 0x240
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struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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2017-06-22 03:24:15 +07:00
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers);
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2016-05-04 19:32:56 +07:00
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int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
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2017-03-10 17:36:33 +07:00
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unsigned int clk_extalr, u32 mode);
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2016-05-04 19:32:56 +07:00
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#endif
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