2019-06-03 12:44:50 +07:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2012-12-10 20:27:52 +07:00
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/*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Derived from arch/arm/include/kvm_emulate.h
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#ifndef __ARM64_KVM_EMULATE_H__
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#define __ARM64_KVM_EMULATE_H__
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#include <linux/kvm_host.h>
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2014-11-24 20:59:30 +07:00
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2018-11-09 22:07:11 +07:00
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#include <asm/debug-monitors.h>
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2014-11-24 20:59:30 +07:00
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#include <asm/esr.h>
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2012-12-10 20:27:52 +07:00
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#include <asm/kvm_arm.h>
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2017-12-28 02:01:52 +07:00
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#include <asm/kvm_hyp.h>
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2012-12-10 20:27:52 +07:00
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#include <asm/kvm_mmio.h>
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#include <asm/ptrace.h>
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2014-06-02 20:37:13 +07:00
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#include <asm/cputype.h>
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2015-01-29 22:47:55 +07:00
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#include <asm/virt.h>
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2012-12-10 20:27:52 +07:00
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2013-02-07 02:40:29 +07:00
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unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
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2017-12-28 03:59:09 +07:00
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unsigned long vcpu_read_spsr32(const struct kvm_vcpu *vcpu);
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void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v);
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2013-02-07 02:40:29 +07:00
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2013-02-07 02:54:04 +07:00
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bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
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void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
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2012-12-10 20:27:52 +07:00
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void kvm_inject_undefined(struct kvm_vcpu *vcpu);
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2016-09-06 20:02:01 +07:00
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void kvm_inject_vabt(struct kvm_vcpu *vcpu);
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2012-12-10 20:27:52 +07:00
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
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2017-10-29 09:18:09 +07:00
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void kvm_inject_undef32(struct kvm_vcpu *vcpu);
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void kvm_inject_dabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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void kvm_inject_pabt32(struct kvm_vcpu *vcpu, unsigned long addr);
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2012-12-10 20:27:52 +07:00
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2017-12-14 04:56:48 +07:00
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static inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu)
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{
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return !(vcpu->arch.hcr_el2 & HCR_RW);
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}
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2014-10-16 22:21:16 +07:00
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static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
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2015-01-29 22:47:55 +07:00
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if (is_kernel_in_hyp_mode())
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vcpu->arch.hcr_el2 |= HCR_E2H;
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2018-01-16 02:39:06 +07:00
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if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) {
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/* route synchronous external abort exceptions to EL2 */
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vcpu->arch.hcr_el2 |= HCR_TEA;
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/* trap error record accesses */
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vcpu->arch.hcr_el2 |= HCR_TERR;
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}
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2018-04-06 18:27:28 +07:00
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if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
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vcpu->arch.hcr_el2 |= HCR_FWB;
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2018-01-16 02:39:06 +07:00
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2015-01-11 20:10:11 +07:00
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if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features))
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vcpu->arch.hcr_el2 &= ~HCR_RW;
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2017-12-01 22:19:40 +07:00
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/*
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* TID3: trap feature register accesses that we virtualise.
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* For now this is conditional, since no AArch32 feature regs
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* are currently virtualised.
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*/
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2017-12-14 04:56:48 +07:00
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if (!vcpu_el1_is_32bit(vcpu))
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2017-12-01 22:19:40 +07:00
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vcpu->arch.hcr_el2 |= HCR_TID3;
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2019-01-31 20:17:17 +07:00
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2019-01-31 20:17:18 +07:00
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if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||
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vcpu_el1_is_32bit(vcpu))
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2019-01-31 20:17:17 +07:00
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vcpu->arch.hcr_el2 |= HCR_TID2;
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2014-10-16 22:21:16 +07:00
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}
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2017-08-03 17:09:05 +07:00
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static inline unsigned long *vcpu_hcr(struct kvm_vcpu *vcpu)
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2014-12-19 23:05:31 +07:00
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{
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2017-08-03 17:09:05 +07:00
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return (unsigned long *)&vcpu->arch.hcr_el2;
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2014-12-19 23:05:31 +07:00
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}
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2018-06-21 16:43:59 +07:00
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static inline void vcpu_clear_wfe_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 &= ~HCR_TWE;
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}
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static inline void vcpu_set_wfe_traps(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 |= HCR_TWE;
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}
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KVM: arm/arm64: Context-switch ptrauth registers
When pointer authentication is supported, a guest may wish to use it.
This patch adds the necessary KVM infrastructure for this to work, with
a semi-lazy context switch of the pointer auth state.
Pointer authentication feature is only enabled when VHE is built
in the kernel and present in the CPU implementation so only VHE code
paths are modified.
When we schedule a vcpu, we disable guest usage of pointer
authentication instructions and accesses to the keys. While these are
disabled, we avoid context-switching the keys. When we trap the guest
trying to use pointer authentication functionality, we change to eagerly
context-switching the keys, and enable the feature. The next time the
vcpu is scheduled out/in, we start again. However the host key save is
optimized and implemented inside ptrauth instruction/register access
trap.
Pointer authentication consists of address authentication and generic
authentication, and CPUs in a system might have varied support for
either. Where support for either feature is not uniform, it is hidden
from guests via ID register emulation, as a result of the cpufeature
framework in the host.
Unfortunately, address authentication and generic authentication cannot
be trapped separately, as the architecture provides a single EL2 trap
covering both. If we wish to expose one without the other, we cannot
prevent a (badly-written) guest from intermittently using a feature
which is not uniformly supported (when scheduled on a physical CPU which
supports the relevant feature). Hence, this patch expects both type of
authentication to be present in a cpu.
This switch of key is done from guest enter/exit assembly as preparation
for the upcoming in-kernel pointer authentication support. Hence, these
key switching routines are not implemented in C code as they may cause
pointer authentication key signing error in some situations.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[Only VHE, key switch in full assembly, vcpu_has_ptrauth checks
, save host key in ptrauth exception trap]
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
[maz: various fixups]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-23 11:42:35 +07:00
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static inline void vcpu_ptrauth_enable(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 |= (HCR_API | HCR_APK);
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}
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static inline void vcpu_ptrauth_disable(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.hcr_el2 &= ~(HCR_API | HCR_APK);
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}
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static inline void vcpu_ptrauth_setup_lazy(struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_ptrauth(vcpu))
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vcpu_ptrauth_disable(vcpu);
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}
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2018-07-19 22:24:22 +07:00
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static inline unsigned long vcpu_get_vsesr(struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vsesr_el2;
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}
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2018-01-16 02:39:01 +07:00
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static inline void vcpu_set_vsesr(struct kvm_vcpu *vcpu, u64 vsesr)
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{
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vcpu->arch.vsesr_el2 = vsesr;
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}
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2012-12-10 20:27:52 +07:00
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static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
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}
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2017-12-28 02:51:04 +07:00
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static inline unsigned long *__vcpu_elr_el1(const struct kvm_vcpu *vcpu)
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2012-12-10 20:27:52 +07:00
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
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}
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2017-12-28 02:51:04 +07:00
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static inline unsigned long vcpu_read_elr_el1(const struct kvm_vcpu *vcpu)
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{
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if (vcpu->arch.sysregs_loaded_on_cpu)
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KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
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return read_sysreg_el1(SYS_ELR);
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2017-12-28 02:51:04 +07:00
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else
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return *__vcpu_elr_el1(vcpu);
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}
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static inline void vcpu_write_elr_el1(const struct kvm_vcpu *vcpu, unsigned long v)
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{
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if (vcpu->arch.sysregs_loaded_on_cpu)
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KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
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write_sysreg_el1(v, SYS_ELR);
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2017-12-28 02:51:04 +07:00
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else
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*__vcpu_elr_el1(vcpu) = v;
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}
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2012-12-10 20:27:52 +07:00
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static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
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{
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return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
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}
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static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
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{
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2013-02-07 02:40:29 +07:00
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return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
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2012-12-10 20:27:52 +07:00
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}
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static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
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{
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2013-02-07 02:54:04 +07:00
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if (vcpu_mode_is_32bit(vcpu))
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return kvm_condition_valid32(vcpu);
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return true;
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2012-12-10 20:27:52 +07:00
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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{
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2018-07-05 21:16:53 +07:00
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*vcpu_cpsr(vcpu) |= PSR_AA32_T_BIT;
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2012-12-10 20:27:52 +07:00
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}
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2015-11-16 17:28:17 +07:00
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/*
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2015-12-04 19:03:14 +07:00
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* vcpu_get_reg and vcpu_set_reg should always be passed a register number
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* coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
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* AArch32 with banked registers.
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2015-11-16 17:28:17 +07:00
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*/
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2015-12-04 19:03:11 +07:00
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static inline unsigned long vcpu_get_reg(const struct kvm_vcpu *vcpu,
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u8 reg_num)
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{
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return (reg_num == 31) ? 0 : vcpu_gp_regs(vcpu)->regs.regs[reg_num];
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}
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static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u8 reg_num,
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unsigned long val)
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{
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if (reg_num != 31)
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vcpu_gp_regs(vcpu)->regs.regs[reg_num] = val;
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}
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2017-12-28 02:01:52 +07:00
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static inline unsigned long vcpu_read_spsr(const struct kvm_vcpu *vcpu)
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2012-12-10 20:27:52 +07:00
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{
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2017-12-28 03:59:09 +07:00
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if (vcpu_mode_is_32bit(vcpu))
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return vcpu_read_spsr32(vcpu);
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2017-12-28 02:01:52 +07:00
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if (vcpu->arch.sysregs_loaded_on_cpu)
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KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
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return read_sysreg_el1(SYS_SPSR);
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2017-12-28 02:01:52 +07:00
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else
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2017-12-28 03:59:09 +07:00
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return vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
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2017-12-28 02:01:52 +07:00
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}
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2013-02-07 02:40:29 +07:00
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2017-12-28 03:59:09 +07:00
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static inline void vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long v)
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2017-12-28 02:01:52 +07:00
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{
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if (vcpu_mode_is_32bit(vcpu)) {
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2017-12-28 03:59:09 +07:00
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vcpu_write_spsr32(vcpu, v);
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return;
|
2017-12-28 02:01:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (vcpu->arch.sysregs_loaded_on_cpu)
|
KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
|
|
|
write_sysreg_el1(v, SYS_SPSR);
|
2017-12-28 02:01:52 +07:00
|
|
|
else
|
2017-12-28 03:59:09 +07:00
|
|
|
vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1] = v;
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2016-01-13 16:16:39 +07:00
|
|
|
u32 mode;
|
2012-12-10 20:27:52 +07:00
|
|
|
|
2016-01-13 16:16:39 +07:00
|
|
|
if (vcpu_mode_is_32bit(vcpu)) {
|
2018-07-05 21:16:53 +07:00
|
|
|
mode = *vcpu_cpsr(vcpu) & PSR_AA32_MODE_MASK;
|
|
|
|
return mode > PSR_AA32_MODE_USR;
|
2016-01-13 16:16:39 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
|
2013-02-07 02:40:29 +07:00
|
|
|
|
2012-12-10 20:27:52 +07:00
|
|
|
return mode != PSR_MODE_EL0t;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return vcpu->arch.fault.esr_el2;
|
|
|
|
}
|
|
|
|
|
2016-09-06 15:28:41 +07:00
|
|
|
static inline int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
u32 esr = kvm_vcpu_get_hsr(vcpu);
|
|
|
|
|
|
|
|
if (esr & ESR_ELx_CV)
|
|
|
|
return (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT;
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2012-12-10 20:27:52 +07:00
|
|
|
static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return vcpu->arch.fault.far_el2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
|
|
|
|
}
|
|
|
|
|
KVM: arm64: Handle RAS SErrors from EL2 on guest exit
We expect to have firmware-first handling of RAS SErrors, with errors
notified via an APEI method. For systems without firmware-first, add
some minimal handling to KVM.
There are two ways KVM can take an SError due to a guest, either may be a
RAS error: we exit the guest due to an SError routed to EL2 by HCR_EL2.AMO,
or we take an SError from EL2 when we unmask PSTATE.A from __guest_exit.
The current SError from EL2 code unmasks SError and tries to fence any
pending SError into a single instruction window. It then leaves SError
unmasked.
With the v8.2 RAS Extensions we may take an SError for a 'corrected'
error, but KVM is only able to handle SError from EL2 if they occur
during this single instruction window...
The RAS Extensions give us a new instruction to synchronise and
consume SErrors. The RAS Extensions document (ARM DDI0587),
'2.4.1 ESB and Unrecoverable errors' describes ESB as synchronising
SError interrupts generated by 'instructions, translation table walks,
hardware updates to the translation tables, and instruction fetches on
the same PE'. This makes ESB equivalent to KVMs existing
'dsb, mrs-daifclr, isb' sequence.
Use the alternatives to synchronise and consume any SError using ESB
instead of unmasking and taking the SError. Set ARM_EXIT_WITH_SERROR_BIT
in the exit_code so that we can restart the vcpu if it turns out this
SError has no impact on the vcpu.
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2018-01-16 02:39:05 +07:00
|
|
|
static inline u64 kvm_vcpu_get_disr(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return vcpu->arch.fault.disr_el1;
|
|
|
|
}
|
|
|
|
|
2015-01-12 23:53:36 +07:00
|
|
|
static inline u32 kvm_vcpu_hvc_get_imm(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2015-01-23 19:39:51 +07:00
|
|
|
return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_xVC_IMM_MASK;
|
2015-01-12 23:53:36 +07:00
|
|
|
}
|
|
|
|
|
2012-12-10 20:27:52 +07:00
|
|
|
static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_ISV);
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SSE);
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return (kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT;
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_S1PTW);
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
arm64: KVM: Take S1 walks into account when determining S2 write faults
The WnR bit in the HSR/ESR_EL2 indicates whether a data abort was
generated by a read or a write instruction. For stage 2 data aborts
generated by a stage 1 translation table walk (i.e. the actual page
table access faults at EL2), the WnR bit therefore reports whether the
instruction generating the walk was a load or a store, *not* whether the
page table walker was reading or writing the entry.
For page tables marked as read-only at stage 2 (e.g. due to KSM merging
them with the tables from another guest), this could result in livelock,
where a page table walk generated by a load instruction attempts to
set the access flag in the stage 1 descriptor, but fails to trigger
CoW in the host since only a read fault is reported.
This patch modifies the arm64 kvm_vcpu_dabt_iswrite function to
take into account stage 2 faults in stage 1 walks. Since DBM cannot be
disabled at EL2 for CPUs that implement it, we assume that these faults
are always causes by writes, avoiding the livelock situation at the
expense of occasional, spurious CoWs.
We could, in theory, do a bit better by checking the guest TCR
configuration and inspecting the page table to see why the PTE faulted.
However, I doubt this is measurable in practice, and the threat of
livelock is real.
Cc: <stable@vger.kernel.org>
Cc: Julien Grall <julien.grall@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-09-29 18:37:01 +07:00
|
|
|
static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_WNR) ||
|
|
|
|
kvm_vcpu_dabt_iss1tw(vcpu); /* AF/DBM update */
|
|
|
|
}
|
|
|
|
|
2016-01-29 22:01:28 +07:00
|
|
|
static inline bool kvm_vcpu_dabt_is_cm(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_CM);
|
|
|
|
}
|
|
|
|
|
2012-12-10 20:27:52 +07:00
|
|
|
static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT);
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This one is not specific to Data Abort */
|
|
|
|
static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return !!(kvm_vcpu_get_hsr(vcpu) & ESR_ELx_IL);
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2016-05-31 18:33:02 +07:00
|
|
|
return ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_IABT_LOW;
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
|
2014-09-26 17:29:34 +07:00
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC;
|
2014-09-26 17:29:34 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vcpu)
|
2012-12-10 20:27:52 +07:00
|
|
|
{
|
2014-11-24 20:59:30 +07:00
|
|
|
return kvm_vcpu_get_hsr(vcpu) & ESR_ELx_FSC_TYPE;
|
2012-12-10 20:27:52 +07:00
|
|
|
}
|
|
|
|
|
2017-07-18 19:37:41 +07:00
|
|
|
static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2017-10-30 13:05:18 +07:00
|
|
|
switch (kvm_vcpu_trap_get_fault(vcpu)) {
|
2017-07-18 19:37:41 +07:00
|
|
|
case FSC_SEA:
|
|
|
|
case FSC_SEA_TTW0:
|
|
|
|
case FSC_SEA_TTW1:
|
|
|
|
case FSC_SEA_TTW2:
|
|
|
|
case FSC_SEA_TTW3:
|
|
|
|
case FSC_SECC:
|
|
|
|
case FSC_SECC_TTW0:
|
|
|
|
case FSC_SECC_TTW1:
|
|
|
|
case FSC_SECC_TTW2:
|
|
|
|
case FSC_SECC_TTW3:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-04-28 01:06:48 +07:00
|
|
|
static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
u32 esr = kvm_vcpu_get_hsr(vcpu);
|
2018-09-20 11:06:19 +07:00
|
|
|
return ESR_ELx_SYS64_ISS_RT(esr);
|
2017-04-28 01:06:48 +07:00
|
|
|
}
|
|
|
|
|
2016-05-02 03:29:58 +07:00
|
|
|
static inline bool kvm_is_write_fault(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
if (kvm_vcpu_trap_is_iabt(vcpu))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return kvm_vcpu_dabt_iswrite(vcpu);
|
|
|
|
}
|
|
|
|
|
2014-06-02 20:37:13 +07:00
|
|
|
static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)
|
2013-10-19 00:19:03 +07:00
|
|
|
{
|
2016-03-16 21:38:53 +07:00
|
|
|
return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;
|
2013-10-19 00:19:03 +07:00
|
|
|
}
|
|
|
|
|
2019-05-03 21:27:49 +07:00
|
|
|
static inline bool kvm_arm_get_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
return vcpu->arch.workaround_flags & VCPU_WORKAROUND_2_FLAG;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void kvm_arm_set_vcpu_workaround_2_flag(struct kvm_vcpu *vcpu,
|
|
|
|
bool flag)
|
|
|
|
{
|
|
|
|
if (flag)
|
|
|
|
vcpu->arch.workaround_flags |= VCPU_WORKAROUND_2_FLAG;
|
|
|
|
else
|
|
|
|
vcpu->arch.workaround_flags &= ~VCPU_WORKAROUND_2_FLAG;
|
|
|
|
}
|
|
|
|
|
2013-11-05 21:12:15 +07:00
|
|
|
static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2016-03-16 21:38:53 +07:00
|
|
|
if (vcpu_mode_is_32bit(vcpu)) {
|
2018-07-05 21:16:53 +07:00
|
|
|
*vcpu_cpsr(vcpu) |= PSR_AA32_E_BIT;
|
2016-03-16 21:38:53 +07:00
|
|
|
} else {
|
|
|
|
u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);
|
|
|
|
sctlr |= (1 << 25);
|
KVM: arm64: Fix order of vcpu_write_sys_reg() arguments
A typo in kvm_vcpu_set_be()'s call:
| vcpu_write_sys_reg(vcpu, SCTLR_EL1, sctlr)
causes us to use the 32bit register value as an index into the sys_reg[]
array, and sail off the end of the linear map when we try to bring up
big-endian secondaries.
| Unable to handle kernel paging request at virtual address ffff80098b982c00
| Mem abort info:
| ESR = 0x96000045
| Exception class = DABT (current EL), IL = 32 bits
| SET = 0, FnV = 0
| EA = 0, S1PTW = 0
| Data abort info:
| ISV = 0, ISS = 0x00000045
| CM = 0, WnR = 1
| swapper pgtable: 4k pages, 48-bit VAs, pgdp = 000000002ea0571a
| [ffff80098b982c00] pgd=00000009ffff8803, pud=0000000000000000
| Internal error: Oops: 96000045 [#1] PREEMPT SMP
| Modules linked in:
| CPU: 2 PID: 1561 Comm: kvm-vcpu-0 Not tainted 4.17.0-rc3-00001-ga912e2261ca6-dirty #1323
| Hardware name: ARM Juno development board (r1) (DT)
| pstate: 60000005 (nZCv daif -PAN -UAO)
| pc : vcpu_write_sys_reg+0x50/0x134
| lr : vcpu_write_sys_reg+0x50/0x134
| Process kvm-vcpu-0 (pid: 1561, stack limit = 0x000000006df4728b)
| Call trace:
| vcpu_write_sys_reg+0x50/0x134
| kvm_psci_vcpu_on+0x14c/0x150
| kvm_psci_0_2_call+0x244/0x2a4
| kvm_hvc_call_handler+0x1cc/0x258
| handle_hvc+0x20/0x3c
| handle_exit+0x130/0x1ec
| kvm_arch_vcpu_ioctl_run+0x340/0x614
| kvm_vcpu_ioctl+0x4d0/0x840
| do_vfs_ioctl+0xc8/0x8d0
| ksys_ioctl+0x78/0xa8
| sys_ioctl+0xc/0x18
| el0_svc_naked+0x30/0x34
| Code: 73620291 604d00b0 00201891 1ab10194 (957a33f8)
|---[ end trace 4b4a4f9628596602 ]---
Fix the order of the arguments.
Fixes: 8d404c4c24613 ("KVM: arm64: Rewrite system register accessors to read/write functions")
CC: Christoffer Dall <cdall@cs.columbia.edu>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-02 18:17:02 +07:00
|
|
|
vcpu_write_sys_reg(vcpu, sctlr, SCTLR_EL1);
|
2016-03-16 21:38:53 +07:00
|
|
|
}
|
2013-11-05 21:12:15 +07:00
|
|
|
}
|
|
|
|
|
2013-02-12 19:40:22 +07:00
|
|
|
static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
|
|
|
if (vcpu_mode_is_32bit(vcpu))
|
2018-07-05 21:16:53 +07:00
|
|
|
return !!(*vcpu_cpsr(vcpu) & PSR_AA32_E_BIT);
|
2013-02-12 19:40:22 +07:00
|
|
|
|
2016-03-16 21:38:53 +07:00
|
|
|
return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));
|
2013-02-12 19:40:22 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long data,
|
|
|
|
unsigned int len)
|
|
|
|
{
|
|
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
|
|
|
return data & 0xff;
|
|
|
|
case 2:
|
|
|
|
return be16_to_cpu(data & 0xffff);
|
|
|
|
case 4:
|
|
|
|
return be32_to_cpu(data & 0xffffffff);
|
|
|
|
default:
|
|
|
|
return be64_to_cpu(data);
|
|
|
|
}
|
2014-06-12 23:30:08 +07:00
|
|
|
} else {
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
|
|
|
return data & 0xff;
|
|
|
|
case 2:
|
|
|
|
return le16_to_cpu(data & 0xffff);
|
|
|
|
case 4:
|
|
|
|
return le32_to_cpu(data & 0xffffffff);
|
|
|
|
default:
|
|
|
|
return le64_to_cpu(data);
|
|
|
|
}
|
2013-02-12 19:40:22 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return data; /* Leave LE untouched */
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned long vcpu_data_host_to_guest(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned long data,
|
|
|
|
unsigned int len)
|
|
|
|
{
|
|
|
|
if (kvm_vcpu_is_be(vcpu)) {
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
|
|
|
return data & 0xff;
|
|
|
|
case 2:
|
|
|
|
return cpu_to_be16(data & 0xffff);
|
|
|
|
case 4:
|
|
|
|
return cpu_to_be32(data & 0xffffffff);
|
|
|
|
default:
|
|
|
|
return cpu_to_be64(data);
|
|
|
|
}
|
2014-06-12 23:30:08 +07:00
|
|
|
} else {
|
|
|
|
switch (len) {
|
|
|
|
case 1:
|
|
|
|
return data & 0xff;
|
|
|
|
case 2:
|
|
|
|
return cpu_to_le16(data & 0xffff);
|
|
|
|
case 4:
|
|
|
|
return cpu_to_le32(data & 0xffffffff);
|
|
|
|
default:
|
|
|
|
return cpu_to_le64(data);
|
|
|
|
}
|
2013-02-12 19:40:22 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
return data; /* Leave LE untouched */
|
|
|
|
}
|
|
|
|
|
2018-11-09 22:07:11 +07:00
|
|
|
static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
|
|
|
|
{
|
|
|
|
if (vcpu_mode_is_32bit(vcpu))
|
|
|
|
kvm_skip_instr32(vcpu, is_wide_instr);
|
|
|
|
else
|
|
|
|
*vcpu_pc(vcpu) += 4;
|
|
|
|
|
|
|
|
/* advance the singlestep state machine */
|
|
|
|
*vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Skip an instruction which has been emulated at hyp while most guest sysregs
|
|
|
|
* are live.
|
|
|
|
*/
|
|
|
|
static inline void __hyp_text __kvm_skip_instr(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
|
|
|
*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
|
|
|
|
vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
|
2018-11-09 22:07:11 +07:00
|
|
|
|
|
|
|
kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
|
|
|
|
|
KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Currently, the {read,write}_sysreg_el*() accessors for accessing
particular ELs' sysregs in the presence of VHE rely on some local
hacks and define their system register encodings in a way that is
inconsistent with the core definitions in <asm/sysreg.h>.
As a result, it is necessary to add duplicate definitions for any
system register that already needs a definition in sysreg.h for
other reasons.
This is a bit of a maintenance headache, and the reasons for the
_el*() accessors working the way they do is a bit historical.
This patch gets rid of the shadow sysreg definitions in
<asm/kvm_hyp.h>, converts the _el*() accessors to use the core
__msr_s/__mrs_s interface, and converts all call sites to use the
standard sysreg #define names (i.e., upper case, with SYS_ prefix).
This patch will conflict heavily anyway, so the opportunity
to clean up some bad whitespace in the context of the changes is
taken.
The change exposes a few system registers that have no sysreg.h
definition, due to msr_s/mrs_s being used in place of msr/mrs:
additions are made in order to fill in the gaps.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Link: https://www.spinics.net/lists/kvm-arm/msg31717.html
[Rebased to v4.21-rc1]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
[Rebased to v5.2-rc5, changelog updates]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-04-06 17:29:40 +07:00
|
|
|
write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
|
|
|
|
write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
|
2018-11-09 22:07:11 +07:00
|
|
|
}
|
|
|
|
|
2012-12-10 20:27:52 +07:00
|
|
|
#endif /* __ARM64_KVM_EMULATE_H__ */
|