2018-05-08 01:23:40 +07:00
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// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2011 Freescale Semiconductor, Inc.
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// Copyright 2011 Linaro Ltd.
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2011-09-06 12:53:26 +07:00
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2014-06-15 19:36:50 +07:00
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#include <dt-bindings/clock/imx6qdl-clock.h>
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2014-03-05 20:25:50 +07:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2011-09-06 12:53:26 +07:00
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/ {
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2016-11-12 22:30:35 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2017-01-23 23:54:10 +07:00
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/*
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* The decompressor and also some bootloaders rely on a
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* pre-existing /chosen node to be available to insert the
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* command line and merge other ATAGS info.
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* Also for U-Boot there must be a pre-existing /memory node.
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*/
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chosen {};
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2018-01-24 20:22:13 +07:00
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memory { device_type = "memory"; };
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2016-11-12 22:30:35 +07:00
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2011-09-06 12:53:26 +07:00
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aliases {
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2014-02-28 18:58:41 +07:00
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ethernet0 = &fec;
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2013-12-12 20:27:57 +07:00
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can0 = &can1;
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can1 = &can2;
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2012-08-05 13:01:28 +07:00
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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gpio5 = &gpio6;
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gpio6 = &gpio7;
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2013-06-25 20:51:57 +07:00
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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2015-12-02 20:42:22 +07:00
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ipu0 = &ipu1;
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2014-01-16 19:44:20 +07:00
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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mmc3 = &usdhc4;
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2013-06-25 20:51:57 +07:00
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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2013-12-20 14:52:05 +07:00
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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2011-09-06 12:53:26 +07:00
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};
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clocks {
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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2014-04-11 08:56:46 +07:00
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#clock-cells = <0>;
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2011-09-06 12:53:26 +07:00
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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2014-04-11 08:56:46 +07:00
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#clock-cells = <0>;
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2011-09-06 12:53:26 +07:00
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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2014-04-11 08:56:46 +07:00
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#clock-cells = <0>;
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2011-09-06 12:53:26 +07:00
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clock-frequency = <24000000>;
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};
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};
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2017-11-30 01:54:35 +07:00
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tempmon: tempmon {
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compatible = "fsl,imx6q-tempmon";
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interrupt-parent = <&gpc>;
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interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tempmon = <&anatop>;
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fsl,tempmon-data = <&ocotp>;
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clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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};
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ldb: ldb {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
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gpr = <&gpr>;
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status = "disabled";
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lvds-channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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status = "disabled";
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port@0 {
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reg = <0>;
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lvds0_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_lvds0>;
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};
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};
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port@1 {
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reg = <1>;
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lvds0_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_lvds0>;
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};
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};
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};
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lvds-channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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status = "disabled";
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port@0 {
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reg = <0>;
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lvds1_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_lvds1>;
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};
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};
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port@1 {
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reg = <1>;
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lvds1_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_lvds1>;
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};
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};
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};
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};
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2018-02-06 00:08:40 +07:00
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pmu: pmu {
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2017-11-30 01:54:35 +07:00
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compatible = "arm,cortex-a9-pmu";
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interrupt-parent = <&gpc>;
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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};
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2011-09-06 12:53:26 +07:00
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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2015-02-24 00:45:18 +07:00
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interrupt-parent = <&gpc>;
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2011-09-06 12:53:26 +07:00
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ranges;
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2017-09-22 01:10:10 +07:00
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dma_apbh: dma-apbh@110000 {
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2012-06-07 08:22:57 +07:00
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x00110000 0x2000>;
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2013-11-15 04:02:13 +07:00
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>;
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2013-02-25 20:56:56 +07:00
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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2014-06-15 19:36:50 +07:00
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clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
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2012-06-07 08:22:57 +07:00
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};
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2017-09-22 01:10:10 +07:00
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gpmi: gpmi-nand@112000 {
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2012-08-22 20:36:28 +07:00
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compatible = "fsl,imx6q-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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2013-11-15 04:02:13 +07:00
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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2013-07-16 16:13:00 +07:00
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interrupt-names = "bch";
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2014-06-15 19:36:50 +07:00
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clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
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<&clks IMX6QDL_CLK_GPMI_APB>,
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<&clks IMX6QDL_CLK_GPMI_BCH>,
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<&clks IMX6QDL_CLK_GPMI_BCH_APB>,
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<&clks IMX6QDL_CLK_PER1_BCH>;
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2012-08-22 20:36:28 +07:00
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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2013-02-25 20:56:56 +07:00
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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2012-08-22 20:36:28 +07:00
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status = "disabled";
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2012-07-02 10:38:46 +07:00
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};
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2017-09-22 01:10:10 +07:00
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hdmi: hdmi@120000 {
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2015-04-01 16:26:54 +07:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00120000 0x9000>;
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interrupts = <0 115 0x04>;
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gpr = <&gpr>;
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clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
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<&clks IMX6QDL_CLK_HDMI_ISFR>;
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clock-names = "iahb", "isfr";
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status = "disabled";
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port@0 {
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reg = <0>;
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hdmi_mux_0: endpoint {
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remote-endpoint = <&ipu1_di0_hdmi>;
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};
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};
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port@1 {
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reg = <1>;
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hdmi_mux_1: endpoint {
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remote-endpoint = <&ipu1_di1_hdmi>;
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};
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};
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};
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2017-09-22 01:10:10 +07:00
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gpu_3d: gpu@130000 {
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2015-12-15 23:30:09 +07:00
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compatible = "vivante,gc";
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reg = <0x00130000 0x4000>;
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interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
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<&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>;
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clock-names = "bus", "core", "shader";
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2017-04-12 23:45:59 +07:00
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power-domains = <&pd_pu>;
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2015-12-15 23:30:09 +07:00
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};
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2017-09-22 01:10:10 +07:00
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gpu_2d: gpu@134000 {
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2015-12-15 23:30:09 +07:00
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compatible = "vivante,gc";
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reg = <0x00134000 0x4000>;
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interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>;
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clock-names = "bus", "core";
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2017-04-12 23:45:59 +07:00
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power-domains = <&pd_pu>;
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2015-12-15 23:30:09 +07:00
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};
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2017-09-22 01:10:10 +07:00
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timer@a00600 {
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2012-01-11 02:44:19 +07:00
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x00a00600 0x20>;
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interrupts = <1 13 0xf01>;
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2015-02-24 00:45:18 +07:00
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interrupt-parent = <&intc>;
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2014-06-15 19:36:50 +07:00
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clocks = <&clks IMX6QDL_CLK_TWD>;
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2011-09-06 12:53:26 +07:00
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};
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2017-09-22 01:10:10 +07:00
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intc: interrupt-controller@a01000 {
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2015-12-02 20:42:55 +07:00
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00a01000 0x1000>,
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<0x00a00100 0x100>;
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interrupt-parent = <&intc>;
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};
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2017-09-22 01:10:10 +07:00
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L2: l2-cache@a02000 {
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2011-09-06 12:53:26 +07:00
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compatible = "arm,pl310-cache";
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reg = <0x00a02000 0x1000>;
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2013-11-15 04:02:13 +07:00
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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2011-09-06 12:53:26 +07:00
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cache-unified;
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cache-level = <2>;
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2013-04-26 15:13:55 +07:00
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arm,tag-latency = <4 2 3>;
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arm,data-latency = <4 2 3>;
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2016-06-07 16:39:25 +07:00
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arm,shared-override;
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2011-09-06 12:53:26 +07:00
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};
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2017-03-22 09:03:03 +07:00
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pcie: pcie@1ffc000 {
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2013-09-26 09:51:09 +07:00
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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2014-08-08 00:39:41 +07:00
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reg = <0x01ffc000 0x04000>,
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<0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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2013-09-26 09:51:09 +07:00
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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2017-03-22 09:03:03 +07:00
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bus-range = <0x00 0xff>;
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2015-12-01 00:00:10 +07:00
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ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
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2013-09-26 09:51:09 +07:00
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
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num-lanes = <1>;
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2014-04-30 12:58:15 +07:00
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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2014-03-05 20:25:50 +07:00
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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2015-08-05 23:54:37 +07:00
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interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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2016-10-14 16:39:29 +07:00
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<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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2014-06-15 19:36:50 +07:00
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clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
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<&clks IMX6QDL_CLK_LVDS1_GATE>,
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<&clks IMX6QDL_CLK_PCIE_REF_125M>;
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2014-04-30 12:58:15 +07:00
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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2013-09-26 09:51:09 +07:00
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status = "disabled";
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};
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2017-09-22 01:10:10 +07:00
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aips-bus@2000000 { /* AIPS1 */
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2011-09-06 12:53:26 +07:00
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x100000>;
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ranges;
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2017-09-22 01:10:10 +07:00
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spba-bus@2000000 {
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2011-09-06 12:53:26 +07:00
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x40000>;
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ranges;
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2017-09-22 01:10:10 +07:00
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spdif: spdif@2004000 {
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2013-09-03 09:51:41 +07:00
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|
|
compatible = "fsl,imx35-spdif";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02004000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
2013-09-03 09:51:41 +07:00
|
|
|
dmas = <&sdma 14 18 0>,
|
|
|
|
<&sdma 15 18 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2015-10-10 17:15:07 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
|
|
|
|
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
|
|
|
|
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
|
2016-08-31 20:56:48 +07:00
|
|
|
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
|
2015-10-10 17:15:07 +07:00
|
|
|
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
|
2013-09-03 09:51:41 +07:00
|
|
|
clock-names = "core", "rxtx0",
|
|
|
|
"rxtx1", "rxtx2",
|
|
|
|
"rxtx3", "rxtx4",
|
|
|
|
"rxtx5", "rxtx6",
|
2015-11-26 09:39:30 +07:00
|
|
|
"rxtx7", "spba";
|
2013-09-03 09:51:41 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ecspi1: ecspi@2008000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
|
|
reg = <0x02008000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ECSPI1>,
|
|
|
|
<&clks IMX6QDL_CLK_ECSPI1>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2016-02-17 20:28:59 +07:00
|
|
|
dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
|
2014-01-04 05:53:52 +07:00
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ecspi2: ecspi@200c000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
|
|
reg = <0x0200c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ECSPI2>,
|
|
|
|
<&clks IMX6QDL_CLK_ECSPI2>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2016-02-17 20:28:59 +07:00
|
|
|
dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
|
2014-01-04 05:53:52 +07:00
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ecspi3: ecspi@2010000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
|
|
reg = <0x02010000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ECSPI3>,
|
|
|
|
<&clks IMX6QDL_CLK_ECSPI3>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2016-02-17 20:28:59 +07:00
|
|
|
dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
|
2014-01-04 05:53:52 +07:00
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ecspi4: ecspi@2014000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
|
|
|
|
reg = <0x02014000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ECSPI4>,
|
|
|
|
<&clks IMX6QDL_CLK_ECSPI4>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2016-02-17 20:28:59 +07:00
|
|
|
dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
|
2014-01-04 05:53:52 +07:00
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
uart1: serial@2020000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
|
|
reg = <0x02020000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-07-12 17:02:09 +07:00
|
|
|
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
esai: esai@2024000 {
|
2015-06-18 12:58:44 +07:00
|
|
|
#sound-dai-cells = <0>;
|
|
|
|
compatible = "fsl,imx35-esai";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02024000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
|
2015-06-18 12:58:44 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_ESAI_MEM>,
|
|
|
|
<&clks IMX6QDL_CLK_ESAI_EXTAL>,
|
|
|
|
<&clks IMX6QDL_CLK_ESAI_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_SPBA>;
|
2015-11-26 09:39:30 +07:00
|
|
|
clock-names = "core", "mem", "extal", "fsys", "spba";
|
2015-06-18 12:58:44 +07:00
|
|
|
dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
|
|
|
|
dma-names = "rx", "tx";
|
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ssi1: ssi@2028000 {
|
2014-08-19 23:00:09 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2014-01-17 16:07:42 +07:00
|
|
|
compatible = "fsl,imx6q-ssi",
|
2014-07-07 20:04:52 +07:00
|
|
|
"fsl,imx51-ssi";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02028000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-09 16:13:26 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_SSI1>;
|
|
|
|
clock-names = "ipg", "baud";
|
2013-07-17 12:50:54 +07:00
|
|
|
dmas = <&sdma 37 1 0>,
|
|
|
|
<&sdma 38 1 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2012-05-02 09:29:10 +07:00
|
|
|
fsl,fifo-depth = <15>;
|
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ssi2: ssi@202c000 {
|
2014-08-19 23:00:09 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2014-01-17 16:07:42 +07:00
|
|
|
compatible = "fsl,imx6q-ssi",
|
2014-07-07 20:04:52 +07:00
|
|
|
"fsl,imx51-ssi";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0202c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-09 16:13:26 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_SSI2>;
|
|
|
|
clock-names = "ipg", "baud";
|
2013-07-17 12:50:54 +07:00
|
|
|
dmas = <&sdma 41 1 0>,
|
|
|
|
<&sdma 42 1 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2012-05-02 09:29:10 +07:00
|
|
|
fsl,fifo-depth = <15>;
|
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ssi3: ssi@2030000 {
|
2014-08-19 23:00:09 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2014-01-17 16:07:42 +07:00
|
|
|
compatible = "fsl,imx6q-ssi",
|
2014-07-07 20:04:52 +07:00
|
|
|
"fsl,imx51-ssi";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02030000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-09 16:13:26 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_SSI3>;
|
|
|
|
clock-names = "ipg", "baud";
|
2013-07-17 12:50:54 +07:00
|
|
|
dmas = <&sdma 45 1 0>,
|
|
|
|
<&sdma 46 1 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2012-05-02 09:29:10 +07:00
|
|
|
fsl,fifo-depth = <15>;
|
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
asrc: asrc@2034000 {
|
2015-06-18 12:58:44 +07:00
|
|
|
compatible = "fsl,imx53-asrc";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02034000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
|
2015-06-18 12:58:44 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
|
|
|
|
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
|
|
|
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
|
|
|
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
|
|
|
<&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
|
|
|
|
<&clks IMX6QDL_CLK_SPBA>;
|
|
|
|
clock-names = "mem", "ipg", "asrck_0",
|
|
|
|
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
|
|
|
|
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
|
|
|
|
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
|
2015-11-26 09:39:30 +07:00
|
|
|
"asrck_d", "asrck_e", "asrck_f", "spba";
|
2015-06-18 12:58:44 +07:00
|
|
|
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
|
|
|
|
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
|
|
|
|
dma-names = "rxa", "rxb", "rxc",
|
|
|
|
"txa", "txb", "txc";
|
|
|
|
fsl,asrc-rate = <48000>;
|
|
|
|
fsl,asrc-width = <16>;
|
|
|
|
status = "okay";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
spba@203c000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0203c000 0x4000>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
vpu: vpu@2040000 {
|
2014-11-12 04:12:47 +07:00
|
|
|
compatible = "cnm,coda960";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02040000 0x3c000>;
|
2014-11-28 22:23:46 +07:00
|
|
|
interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 3 IRQ_TYPE_LEVEL_HIGH>;
|
2014-11-12 04:12:47 +07:00
|
|
|
interrupt-names = "bit", "jpeg";
|
|
|
|
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
|
2014-12-16 20:02:41 +07:00
|
|
|
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
|
|
|
|
clock-names = "per", "ahb";
|
2017-04-12 23:45:59 +07:00
|
|
|
power-domains = <&pd_pu>;
|
2014-11-12 04:12:47 +07:00
|
|
|
resets = <&src 1>;
|
|
|
|
iram = <&ocram>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
aipstz@207c000 { /* AIPSTZ1 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0207c000 0x4000>;
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
pwm1: pwm@2080000 {
|
2012-11-21 18:18:28 +07:00
|
|
|
#pwm-cells = <2>;
|
|
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02080000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_PWM1>;
|
2012-11-21 18:18:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2015-03-09 23:40:36 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
pwm2: pwm@2084000 {
|
2012-11-21 18:18:28 +07:00
|
|
|
#pwm-cells = <2>;
|
|
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02084000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_PWM2>;
|
2012-11-21 18:18:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2015-03-09 23:40:36 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
pwm3: pwm@2088000 {
|
2012-11-21 18:18:28 +07:00
|
|
|
#pwm-cells = <2>;
|
|
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02088000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_PWM3>;
|
2012-11-21 18:18:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2015-03-09 23:40:36 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
pwm4: pwm@208c000 {
|
2012-11-21 18:18:28 +07:00
|
|
|
#pwm-cells = <2>;
|
|
|
|
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0208c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_PWM4>;
|
2012-11-21 18:18:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2015-03-09 23:40:36 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
can1: flexcan@2090000 {
|
2013-06-25 20:51:46 +07:00
|
|
|
compatible = "fsl,imx6q-flexcan";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02090000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_CAN1_SERIAL>;
|
2013-06-25 20:51:46 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-10-23 11:51:27 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
can2: flexcan@2094000 {
|
2013-06-25 20:51:46 +07:00
|
|
|
compatible = "fsl,imx6q-flexcan";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02094000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_CAN2_SERIAL>;
|
2013-06-25 20:51:46 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-10-23 11:51:27 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpt: gpt@2098000 {
|
2013-06-25 20:51:47 +07:00
|
|
|
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x02098000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
|
2014-09-11 10:29:41 +07:00
|
|
|
<&clks IMX6QDL_CLK_GPT_IPG_PER>,
|
|
|
|
<&clks IMX6QDL_CLK_GPT_3M>;
|
|
|
|
clock-names = "ipg", "per", "osc_per";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio1: gpio@209c000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0209c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 67 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio2: gpio@20a0000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020a0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 69 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio3: gpio@20a4000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020a4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 71 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio4: gpio@20a8000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020a8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 73 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio5: gpio@20ac000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020ac000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 75 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio6: gpio@20b0000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020b0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 77 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpio7: gpio@20b4000 {
|
2012-06-23 02:04:06 +07:00
|
|
|
compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020b4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 79 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
gpio-controller;
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
2012-07-06 19:03:37 +07:00
|
|
|
#interrupt-cells = <2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
kpp: kpp@20b8000 {
|
2014-06-06 18:02:59 +07:00
|
|
|
compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020b8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>;
|
2014-06-25 07:13:44 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
wdog1: wdog@20bc000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
|
|
reg = <0x020bc000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
wdog2: wdog@20c0000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
|
|
|
|
reg = <0x020c0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_DUMMY>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
clks: ccm@20c4000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-ccm";
|
|
|
|
reg = <0x020c4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 88 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-22 20:36:28 +07:00
|
|
|
#clock-cells = <1>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
anatop: anatop@20c8000 {
|
2012-09-05 09:57:15 +07:00
|
|
|
compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020c8000 0x1000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 127 IRQ_TYPE_LEVEL_HIGH>;
|
2012-03-30 20:46:53 +07:00
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
regulator-1p1 {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
|
|
|
regulator-name = "vdd1p1";
|
2017-01-19 21:21:34 +07:00
|
|
|
regulator-min-microvolt = <1000000>;
|
|
|
|
regulator-max-microvolt = <1200000>;
|
2012-03-30 20:46:53 +07:00
|
|
|
regulator-always-on;
|
|
|
|
anatop-reg-offset = <0x110>;
|
|
|
|
anatop-vol-bit-shift = <8>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
|
|
|
anatop-min-bit-val = <4>;
|
|
|
|
anatop-min-voltage = <800000>;
|
|
|
|
anatop-max-voltage = <1375000>;
|
2017-05-15 21:52:59 +07:00
|
|
|
anatop-enable-bit = <0>;
|
2012-03-30 20:46:53 +07:00
|
|
|
};
|
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
regulator-3p0 {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
|
|
|
regulator-name = "vdd3p0";
|
|
|
|
regulator-min-microvolt = <2800000>;
|
|
|
|
regulator-max-microvolt = <3150000>;
|
|
|
|
regulator-always-on;
|
|
|
|
anatop-reg-offset = <0x120>;
|
|
|
|
anatop-vol-bit-shift = <8>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
|
|
|
anatop-min-bit-val = <0>;
|
|
|
|
anatop-min-voltage = <2625000>;
|
|
|
|
anatop-max-voltage = <3400000>;
|
2017-05-15 21:52:59 +07:00
|
|
|
anatop-enable-bit = <0>;
|
2012-03-30 20:46:53 +07:00
|
|
|
};
|
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
regulator-2p5 {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
|
|
|
regulator-name = "vdd2p5";
|
2017-01-19 21:21:34 +07:00
|
|
|
regulator-min-microvolt = <2250000>;
|
2012-03-30 20:46:53 +07:00
|
|
|
regulator-max-microvolt = <2750000>;
|
|
|
|
regulator-always-on;
|
|
|
|
anatop-reg-offset = <0x130>;
|
|
|
|
anatop-vol-bit-shift = <8>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
|
|
|
anatop-min-bit-val = <0>;
|
2017-01-19 21:21:33 +07:00
|
|
|
anatop-min-voltage = <2100000>;
|
|
|
|
anatop-max-voltage = <2875000>;
|
2017-05-15 21:52:59 +07:00
|
|
|
anatop-enable-bit = <0>;
|
2012-03-30 20:46:53 +07:00
|
|
|
};
|
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
reg_arm: regulator-vddcore {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
2013-12-20 06:08:52 +07:00
|
|
|
regulator-name = "vddarm";
|
2012-03-30 20:46:53 +07:00
|
|
|
regulator-min-microvolt = <725000>;
|
|
|
|
regulator-max-microvolt = <1450000>;
|
|
|
|
regulator-always-on;
|
|
|
|
anatop-reg-offset = <0x140>;
|
|
|
|
anatop-vol-bit-shift = <0>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
2013-01-31 05:33:44 +07:00
|
|
|
anatop-delay-reg-offset = <0x170>;
|
|
|
|
anatop-delay-bit-shift = <24>;
|
|
|
|
anatop-delay-bit-width = <2>;
|
2012-03-30 20:46:53 +07:00
|
|
|
anatop-min-bit-val = <1>;
|
|
|
|
anatop-min-voltage = <725000>;
|
|
|
|
anatop-max-voltage = <1450000>;
|
|
|
|
};
|
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
reg_pu: regulator-vddpu {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
|
|
|
regulator-name = "vddpu";
|
|
|
|
regulator-min-microvolt = <725000>;
|
|
|
|
regulator-max-microvolt = <1450000>;
|
2015-02-24 00:40:15 +07:00
|
|
|
regulator-enable-ramp-delay = <150>;
|
2012-03-30 20:46:53 +07:00
|
|
|
anatop-reg-offset = <0x140>;
|
|
|
|
anatop-vol-bit-shift = <9>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
2013-01-31 05:33:44 +07:00
|
|
|
anatop-delay-reg-offset = <0x170>;
|
|
|
|
anatop-delay-bit-shift = <26>;
|
|
|
|
anatop-delay-bit-width = <2>;
|
2012-03-30 20:46:53 +07:00
|
|
|
anatop-min-bit-val = <1>;
|
|
|
|
anatop-min-voltage = <725000>;
|
|
|
|
anatop-max-voltage = <1450000>;
|
|
|
|
};
|
|
|
|
|
2018-05-14 20:31:54 +07:00
|
|
|
reg_soc: regulator-vddsoc {
|
2012-03-30 20:46:53 +07:00
|
|
|
compatible = "fsl,anatop-regulator";
|
|
|
|
regulator-name = "vddsoc";
|
|
|
|
regulator-min-microvolt = <725000>;
|
|
|
|
regulator-max-microvolt = <1450000>;
|
|
|
|
regulator-always-on;
|
|
|
|
anatop-reg-offset = <0x140>;
|
|
|
|
anatop-vol-bit-shift = <18>;
|
|
|
|
anatop-vol-bit-width = <5>;
|
2013-01-31 05:33:44 +07:00
|
|
|
anatop-delay-reg-offset = <0x170>;
|
|
|
|
anatop-delay-bit-shift = <28>;
|
|
|
|
anatop-delay-bit-width = <2>;
|
2012-03-30 20:46:53 +07:00
|
|
|
anatop-min-bit-val = <1>;
|
|
|
|
anatop-min-voltage = <725000>;
|
|
|
|
anatop-max-voltage = <1450000>;
|
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbphy1: usbphy@20c9000 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020c9000 0x1000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBPHY1>;
|
2013-12-20 14:52:01 +07:00
|
|
|
fsl,anatop = <&anatop>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbphy2: usbphy@20ca000 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020ca000 0x1000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBPHY2>;
|
2013-12-20 14:52:01 +07:00
|
|
|
fsl,anatop = <&anatop>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
snvs: snvs@20cc000 {
|
2015-05-26 23:25:59 +07:00
|
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
|
|
reg = <0x020cc000 0x4000>;
|
2012-07-02 19:13:03 +07:00
|
|
|
|
2015-05-26 23:25:59 +07:00
|
|
|
snvs_rtc: snvs-rtc-lp {
|
2012-07-02 19:13:03 +07:00
|
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
2015-05-26 23:25:59 +07:00
|
|
|
regmap = <&snvs>;
|
|
|
|
offset = <0x34>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 20 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-02 19:13:03 +07:00
|
|
|
};
|
2014-11-12 15:20:37 +07:00
|
|
|
|
2015-05-26 23:25:59 +07:00
|
|
|
snvs_poweroff: snvs-poweroff {
|
|
|
|
compatible = "syscon-poweroff";
|
|
|
|
regmap = <&snvs>;
|
|
|
|
offset = <0x38>;
|
2017-07-04 23:19:12 +07:00
|
|
|
value = <0x60>;
|
2015-05-26 23:25:59 +07:00
|
|
|
mask = <0x60>;
|
2014-11-12 15:20:37 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
2017-06-20 14:09:32 +07:00
|
|
|
|
|
|
|
snvs_lpgpr: snvs-lpgpr {
|
|
|
|
compatible = "fsl,imx6q-snvs-lpgpr";
|
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
epit1: epit@20d0000 { /* EPIT1 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020d0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
epit2: epit@20d4000 { /* EPIT2 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020d4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
src: src@20d8000 {
|
2013-03-28 23:35:22 +07:00
|
|
|
compatible = "fsl,imx6q-src", "fsl,imx51-src";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020d8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 96 IRQ_TYPE_LEVEL_HIGH>;
|
2013-03-28 23:35:20 +07:00
|
|
|
#reset-cells = <1>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpc: gpc@20dc000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-gpc";
|
|
|
|
reg = <0x020dc000 0x4000>;
|
2015-02-24 00:45:18 +07:00
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <3>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 90 IRQ_TYPE_LEVEL_HIGH>;
|
2015-02-24 00:45:18 +07:00
|
|
|
interrupt-parent = <&intc>;
|
2017-04-12 23:45:59 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPG>;
|
|
|
|
clock-names = "ipg";
|
|
|
|
|
|
|
|
pgc {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
power-domain@0 {
|
|
|
|
reg = <0>;
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
};
|
|
|
|
pd_pu: power-domain@1 {
|
|
|
|
reg = <1>;
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
power-supply = <®_pu>;
|
|
|
|
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
|
|
|
|
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
|
|
|
|
<&clks IMX6QDL_CLK_GPU2D_CORE>,
|
|
|
|
<&clks IMX6QDL_CLK_GPU2D_AXI>,
|
|
|
|
<&clks IMX6QDL_CLK_OPENVG_AXI>,
|
|
|
|
<&clks IMX6QDL_CLK_VPU_AXI>;
|
|
|
|
};
|
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
gpr: iomuxc-gpr@20e0000 {
|
2017-06-13 01:23:54 +07:00
|
|
|
compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
|
2017-09-22 01:10:10 +07:00
|
|
|
reg = <0x20e0000 0x38>;
|
2017-06-13 01:23:54 +07:00
|
|
|
|
|
|
|
mux: mux-controller {
|
|
|
|
compatible = "mmio-mux";
|
|
|
|
#mux-control-cells = <1>;
|
|
|
|
};
|
2012-09-05 09:57:14 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
iomuxc: iomuxc@20e0000 {
|
2013-07-11 12:58:36 +07:00
|
|
|
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
|
2017-09-22 01:10:10 +07:00
|
|
|
reg = <0x20e0000 0x4000>;
|
2013-07-11 12:58:36 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
dcic1: dcic@20e4000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020e4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
dcic2: dcic@20e8000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x020e8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
sdma: sdma@20ec000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
|
|
|
|
reg = <0x020ec000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_SDMA>,
|
|
|
|
<&clks IMX6QDL_CLK_SDMA>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "ahb";
|
2013-07-02 09:15:29 +07:00
|
|
|
#dma-cells = <3>;
|
2013-01-17 21:13:25 +07:00
|
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
aips-bus@2100000 { /* AIPS2 */
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
reg = <0x02100000 0x100000>;
|
|
|
|
ranges;
|
|
|
|
|
2015-08-06 01:28:44 +07:00
|
|
|
crypto: caam@2100000 {
|
|
|
|
compatible = "fsl,sec-v4.0";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
reg = <0x2100000 0x10000>;
|
|
|
|
ranges = <0 0x2100000 0x10000>;
|
|
|
|
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
|
|
|
|
<&clks IMX6QDL_CLK_CAAM_ACLK>,
|
|
|
|
<&clks IMX6QDL_CLK_CAAM_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_EIM_SLOW>;
|
|
|
|
clock-names = "mem", "aclk", "ipg", "emi_slow";
|
|
|
|
|
|
|
|
sec_jr0: jr0@1000 {
|
|
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
|
|
reg = <0x1000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
};
|
|
|
|
|
|
|
|
sec_jr1: jr1@2000 {
|
|
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
|
|
reg = <0x2000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
aipstz@217c000 { /* AIPSTZ2 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0217c000 0x4000>;
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbotg: usb@2184000 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
|
|
reg = <0x02184000 0x200>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
2012-07-12 13:21:41 +07:00
|
|
|
fsl,usbphy = <&usbphy1>;
|
2012-09-14 13:42:45 +07:00
|
|
|
fsl,usbmisc = <&usbmisc 0>;
|
2015-09-30 09:17:16 +07:00
|
|
|
ahb-burst-config = <0x0>;
|
2015-09-30 09:17:17 +07:00
|
|
|
tx-burst-size-dword = <0x10>;
|
|
|
|
rx-burst-size-dword = <0x10>;
|
2012-07-12 13:21:41 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbh1: usb@2184200 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
|
|
reg = <0x02184200 0x200>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
2012-07-12 13:21:41 +07:00
|
|
|
fsl,usbphy = <&usbphy2>;
|
2012-09-14 13:42:45 +07:00
|
|
|
fsl,usbmisc = <&usbmisc 1>;
|
2015-02-27 21:06:00 +07:00
|
|
|
dr_mode = "host";
|
2015-09-30 09:17:16 +07:00
|
|
|
ahb-burst-config = <0x0>;
|
2015-09-30 09:17:17 +07:00
|
|
|
tx-burst-size-dword = <0x10>;
|
|
|
|
rx-burst-size-dword = <0x10>;
|
2012-07-12 13:21:41 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbh2: usb@2184400 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
|
|
reg = <0x02184400 0x200>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
2012-09-14 13:42:45 +07:00
|
|
|
fsl,usbmisc = <&usbmisc 2>;
|
2015-02-27 21:06:00 +07:00
|
|
|
dr_mode = "host";
|
2015-09-30 09:17:16 +07:00
|
|
|
ahb-burst-config = <0x0>;
|
2015-09-30 09:17:17 +07:00
|
|
|
tx-burst-size-dword = <0x10>;
|
|
|
|
rx-burst-size-dword = <0x10>;
|
2012-07-12 13:21:41 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbh3: usb@2184600 {
|
2012-07-12 13:21:41 +07:00
|
|
|
compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
|
|
|
|
reg = <0x02184600 0x200>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
2012-09-14 13:42:45 +07:00
|
|
|
fsl,usbmisc = <&usbmisc 3>;
|
2015-02-27 21:06:00 +07:00
|
|
|
dr_mode = "host";
|
2015-09-30 09:17:16 +07:00
|
|
|
ahb-burst-config = <0x0>;
|
2015-09-30 09:17:17 +07:00
|
|
|
tx-burst-size-dword = <0x10>;
|
|
|
|
rx-burst-size-dword = <0x10>;
|
2012-07-12 13:21:41 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usbmisc: usbmisc@2184800 {
|
2012-09-14 13:42:45 +07:00
|
|
|
#index-cells = <1>;
|
|
|
|
compatible = "fsl,imx6q-usbmisc";
|
|
|
|
reg = <0x02184800 0x200>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USBOH3>;
|
2012-09-14 13:42:45 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
fec: ethernet@2188000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-fec";
|
|
|
|
reg = <0x02188000 0x4000>;
|
2017-11-04 00:29:58 +07:00
|
|
|
interrupt-names = "int0", "pps";
|
2013-12-21 01:47:10 +07:00
|
|
|
interrupts-extended =
|
|
|
|
<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_ENET>,
|
|
|
|
<&clks IMX6QDL_CLK_ENET>,
|
|
|
|
<&clks IMX6QDL_CLK_ENET_REF>;
|
2012-10-31 01:24:57 +07:00
|
|
|
clock-names = "ipg", "ahb", "ptp";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
mlb@218c000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x0218c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 126 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usdhc1: usdhc@2190000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-usdhc";
|
|
|
|
reg = <0x02190000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USDHC1>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC1>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC1>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "ahb", "per";
|
2012-09-25 16:49:33 +07:00
|
|
|
bus-width = <4>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usdhc2: usdhc@2194000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-usdhc";
|
|
|
|
reg = <0x02194000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USDHC2>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC2>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC2>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "ahb", "per";
|
2012-09-25 16:49:33 +07:00
|
|
|
bus-width = <4>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usdhc3: usdhc@2198000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-usdhc";
|
|
|
|
reg = <0x02198000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USDHC3>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC3>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC3>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "ahb", "per";
|
2012-09-25 16:49:33 +07:00
|
|
|
bus-width = <4>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
usdhc4: usdhc@219c000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-usdhc";
|
|
|
|
reg = <0x0219c000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_USDHC4>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC4>,
|
|
|
|
<&clks IMX6QDL_CLK_USDHC4>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "ahb", "per";
|
2012-09-25 16:49:33 +07:00
|
|
|
bus-width = <4>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
i2c1: i2c@21a0000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2012-09-14 14:19:00 +07:00
|
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021a0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_I2C1>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
i2c2: i2c@21a4000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2012-09-14 14:19:00 +07:00
|
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021a4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_I2C2>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
i2c3: i2c@21a8000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2012-09-14 14:19:00 +07:00
|
|
|
compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021a8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_I2C3>;
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
romcp@21ac000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021ac000 0x4000>;
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
mmdc0: mmdc@21b0000 { /* MMDC0 */
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-mmdc";
|
|
|
|
reg = <0x021b0000 0x4000>;
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
mmdc1: mmdc@21b4000 { /* MMDC1 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021b4000 0x4000>;
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
weim: weim@21b8000 {
|
2016-11-02 06:51:45 +07:00
|
|
|
#address-cells = <2>;
|
|
|
|
#size-cells = <1>;
|
2013-05-28 13:20:09 +07:00
|
|
|
compatible = "fsl,imx6q-weim";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021b8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
|
2016-11-02 06:51:45 +07:00
|
|
|
fsl,weim-cs-gpr = <&gpr>;
|
2016-12-30 17:09:03 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ocotp: ocotp@21bc000 {
|
2013-07-16 20:16:36 +07:00
|
|
|
compatible = "fsl,imx6q-ocotp", "syscon";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021bc000 0x4000>;
|
2016-04-21 00:26:15 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IIM>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
tzasc@21d0000 { /* TZASC1 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021d0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
tzasc@21d4000 { /* TZASC2 */
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021d4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
audmux: audmux@21d8000 {
|
2012-05-02 09:32:26 +07:00
|
|
|
compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021d8000 0x4000>;
|
2012-05-02 09:32:26 +07:00
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
mipi_csi: mipi@21dc000 {
|
2017-06-13 01:23:55 +07:00
|
|
|
compatible = "fsl,imx6-mipi-csi2";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021dc000 0x4000>;
|
2017-06-13 01:23:56 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2017-06-13 01:23:55 +07:00
|
|
|
interrupts = <0 100 0x04>, <0 101 0x04>;
|
|
|
|
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
|
|
|
|
<&clks IMX6QDL_CLK_VIDEO_27M>,
|
|
|
|
<&clks IMX6QDL_CLK_EIM_PODF>;
|
|
|
|
clock-names = "dphy", "ref", "pix";
|
|
|
|
status = "disabled";
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
mipi_dsi: mipi@21e0000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021e0000 0x4000>;
|
2014-03-05 16:21:01 +07:00
|
|
|
status = "disabled";
|
|
|
|
|
2015-02-12 13:01:31 +07:00
|
|
|
ports {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
port@0 {
|
|
|
|
reg = <0>;
|
2014-03-05 16:21:01 +07:00
|
|
|
|
2015-02-12 13:01:31 +07:00
|
|
|
mipi_mux_0: endpoint {
|
|
|
|
remote-endpoint = <&ipu1_di0_mipi>;
|
|
|
|
};
|
2014-03-05 16:21:01 +07:00
|
|
|
};
|
|
|
|
|
2015-02-12 13:01:31 +07:00
|
|
|
port@1 {
|
|
|
|
reg = <1>;
|
2014-03-05 16:21:01 +07:00
|
|
|
|
2015-02-12 13:01:31 +07:00
|
|
|
mipi_mux_1: endpoint {
|
|
|
|
remote-endpoint = <&ipu1_di1_mipi>;
|
|
|
|
};
|
2014-03-05 16:21:01 +07:00
|
|
|
};
|
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
vdoa@21e4000 {
|
2017-01-20 21:00:19 +07:00
|
|
|
compatible = "fsl,imx6q-vdoa";
|
2011-09-06 12:53:26 +07:00
|
|
|
reg = <0x021e4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
2017-01-20 21:00:19 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_VDOA>;
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
uart2: serial@21e8000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
|
|
reg = <0x021e8000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-07-12 17:02:09 +07:00
|
|
|
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
uart3: serial@21ec000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
|
|
reg = <0x021ec000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-07-12 17:02:09 +07:00
|
|
|
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
uart4: serial@21f0000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
|
|
reg = <0x021f0000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-07-12 17:02:09 +07:00
|
|
|
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
uart5: serial@21f4000 {
|
2011-09-06 12:53:26 +07:00
|
|
|
compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
|
|
|
|
reg = <0x021f4000 0x4000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_UART_IPG>,
|
|
|
|
<&clks IMX6QDL_CLK_UART_SERIAL>;
|
2012-08-22 20:36:28 +07:00
|
|
|
clock-names = "ipg", "per";
|
2013-07-12 17:02:09 +07:00
|
|
|
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
|
|
|
dma-names = "rx", "tx";
|
2011-09-06 12:53:26 +07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
};
|
2012-11-12 21:52:21 +07:00
|
|
|
|
2017-09-22 01:10:10 +07:00
|
|
|
ipu1: ipu@2400000 {
|
2014-03-05 16:21:01 +07:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2012-11-12 21:52:21 +07:00
|
|
|
compatible = "fsl,imx6q-ipu";
|
|
|
|
reg = <0x02400000 0x400000>;
|
2013-11-15 04:02:13 +07:00
|
|
|
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 5 IRQ_TYPE_LEVEL_HIGH>;
|
2014-06-15 19:36:50 +07:00
|
|
|
clocks = <&clks IMX6QDL_CLK_IPU1>,
|
|
|
|
<&clks IMX6QDL_CLK_IPU1_DI0>,
|
|
|
|
<&clks IMX6QDL_CLK_IPU1_DI1>;
|
2012-11-12 21:52:21 +07:00
|
|
|
clock-names = "bus", "di0", "di1";
|
2013-03-28 23:35:20 +07:00
|
|
|
resets = <&src 2>;
|
2014-03-05 16:21:01 +07:00
|
|
|
|
2014-05-27 22:26:37 +07:00
|
|
|
ipu1_csi0: port@0 {
|
|
|
|
reg = <0>;
|
2017-06-13 01:23:56 +07:00
|
|
|
|
|
|
|
ipu1_csi0_from_ipu1_csi0_mux: endpoint {
|
|
|
|
remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
|
|
|
|
};
|
2014-05-27 22:26:37 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
ipu1_csi1: port@1 {
|
|
|
|
reg = <1>;
|
|
|
|
};
|
|
|
|
|
2014-03-05 16:21:01 +07:00
|
|
|
ipu1_di0: port@2 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <2>;
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di0_disp0: endpoint@0 {
|
|
|
|
reg = <0>;
|
2014-03-05 16:21:01 +07:00
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di0_hdmi: endpoint@1 {
|
|
|
|
reg = <1>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&hdmi_mux_0>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di0_mipi: endpoint@2 {
|
|
|
|
reg = <2>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&mipi_mux_0>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di0_lvds0: endpoint@3 {
|
|
|
|
reg = <3>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&lvds0_mux_0>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di0_lvds1: endpoint@4 {
|
|
|
|
reg = <4>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&lvds1_mux_0>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
ipu1_di1: port@3 {
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
reg = <3>;
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di1_disp1: endpoint@0 {
|
|
|
|
reg = <0>;
|
2014-03-05 16:21:01 +07:00
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di1_hdmi: endpoint@1 {
|
|
|
|
reg = <1>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&hdmi_mux_1>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di1_mipi: endpoint@2 {
|
|
|
|
reg = <2>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&mipi_mux_1>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di1_lvds0: endpoint@3 {
|
|
|
|
reg = <3>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&lvds0_mux_1>;
|
|
|
|
};
|
|
|
|
|
2018-05-08 20:59:26 +07:00
|
|
|
ipu1_di1_lvds1: endpoint@4 {
|
|
|
|
reg = <4>;
|
2014-03-05 16:21:01 +07:00
|
|
|
remote-endpoint = <&lvds1_mux_1>;
|
|
|
|
};
|
|
|
|
};
|
2012-11-12 21:52:21 +07:00
|
|
|
};
|
2011-09-06 12:53:26 +07:00
|
|
|
};
|
|
|
|
};
|