2013-12-19 19:33:38 +07:00
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/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* AM437x GP EVM */
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/dts-v1/;
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#include "am4372.dtsi"
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#include <dt-bindings/pinctrl/am43xx.h>
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2013-12-19 19:33:39 +07:00
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#include <dt-bindings/pwm/pwm.h>
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2013-12-19 19:33:41 +07:00
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#include <dt-bindings/gpio/gpio.h>
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2013-12-19 19:33:38 +07:00
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/ {
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model = "TI AM437x GP EVM";
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compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
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2013-12-19 19:33:39 +07:00
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2014-03-24 18:01:56 +07:00
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aliases {
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display0 = &lcd0;
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};
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2017-01-18 11:03:24 +07:00
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chosen {
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stdout-path = &uart0;
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};
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2015-07-02 21:06:25 +07:00
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evm_v3_3d: fixedregulator-v3_3d {
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2014-03-03 21:50:18 +07:00
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compatible = "regulator-fixed";
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2015-07-02 21:06:25 +07:00
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regulator-name = "evm_v3_3d";
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2014-03-03 21:50:18 +07:00
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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};
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2014-05-06 02:58:28 +07:00
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vtt_fixed: fixedregulator-vtt {
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compatible = "regulator-fixed";
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regulator-name = "vtt_fixed";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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regulator-always-on;
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regulator-boot-on;
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enable-active-high;
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gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
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};
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2015-05-04 19:24:24 +07:00
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vmmcwl_fixed: fixedregulator-mmcwl {
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compatible = "regulator-fixed";
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regulator-name = "vmmcwl_fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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2017-12-15 19:09:32 +07:00
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lcd_bl: backlight {
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2013-12-19 19:33:39 +07:00
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compatible = "pwm-backlight";
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pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
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brightness-levels = <0 51 53 56 62 75 101 152 255>;
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default-brightness-level = <8>;
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};
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2013-12-19 19:33:41 +07:00
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2016-08-01 23:46:57 +07:00
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matrix_keypad: matrix_keypad0 {
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2013-12-19 19:33:41 +07:00
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compatible = "gpio-matrix-keypad";
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debounce-delay-ms = <5>;
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col-scan-delay-us = <2>;
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row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
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&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
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&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
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col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
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&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
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linux,keymap = <0x00000201 /* P1 */
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0x00010202 /* P2 */
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0x01000067 /* UP */
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0x0101006a /* RIGHT */
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0x02000069 /* LEFT */
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0x0201006c>; /* DOWN */
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};
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2014-03-24 18:01:56 +07:00
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lcd0: display {
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compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
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label = "lcd";
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2017-12-15 19:09:32 +07:00
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backlight = <&lcd_bl>;
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2014-03-24 18:01:56 +07:00
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panel-timing {
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clock-frequency = <33000000>;
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hactive = <800>;
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vactive = <480>;
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hfront-porch = <210>;
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hback-porch = <16>;
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hsync-len = <30>;
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vback-porch = <10>;
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vfront-porch = <22>;
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vsync-len = <13>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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port {
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lcd_in: endpoint {
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remote-endpoint = <&dpi_out>;
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};
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};
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};
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2015-03-13 06:38:21 +07:00
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/* fixed 12MHz oscillator */
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refclk: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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2015-08-18 16:41:14 +07:00
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/* fixed 32k external oscillator clock */
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clk_32k_rtc: clk_32k_rtc {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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2016-04-02 03:20:21 +07:00
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sound0: sound0 {
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2015-07-02 21:06:28 +07:00
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compatible = "simple-audio-card";
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simple-audio-card,name = "AM437x-GP-EVM";
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simple-audio-card,widgets =
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"Headphone", "Headphone Jack",
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"Line", "Line In";
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simple-audio-card,routing =
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"Headphone Jack", "HPLOUT",
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"Headphone Jack", "HPROUT",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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simple-audio-card,format = "dsp_b";
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simple-audio-card,bitclock-master = <&sound0_master>;
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simple-audio-card,frame-master = <&sound0_master>;
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simple-audio-card,bitclock-inversion;
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simple-audio-card,cpu {
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sound-dai = <&mcasp1>;
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system-clock-frequency = <12000000>;
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};
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sound0_master: simple-audio-card,codec {
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sound-dai = <&tlv320aic3106>;
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system-clock-frequency = <12000000>;
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};
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};
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2017-06-20 12:09:21 +07:00
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beeper: beeper {
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compatible = "gpio-beeper";
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pinctrl-names = "default";
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pinctrl-0 = <&beeper_pins>;
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gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
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};
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2013-12-19 19:33:38 +07:00
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};
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&am43xx_pinmux {
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2015-05-04 19:24:24 +07:00
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&wlan_pins_default>;
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pinctrl-1 = <&wlan_pins_sleep>;
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2013-12-19 19:33:38 +07:00
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i2c0_pins: i2c0_pins {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
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AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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2013-12-19 19:33:38 +07:00
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>;
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};
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i2c1_pins: i2c1_pins {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
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AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
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2013-12-19 19:33:38 +07:00
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>;
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};
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2013-12-19 19:33:39 +07:00
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2014-03-03 21:50:18 +07:00
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mmc1_pins: pinmux_mmc1_pins {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
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2014-03-03 21:50:18 +07:00
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>;
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};
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2013-12-19 19:33:39 +07:00
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ecap0_pins: backlight_pins {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
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2013-12-19 19:33:39 +07:00
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>;
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};
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2014-04-30 19:43:25 +07:00
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pixcir_ts_pins: pixcir_ts_pins {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
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2014-04-30 19:43:25 +07:00
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>;
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};
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2014-05-13 15:44:31 +07:00
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cpsw_default: cpsw_default {
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pinctrl-single,pins = <
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/* Slave 1 */
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
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AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
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AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
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AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
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AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
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AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
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AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
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AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
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AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
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AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
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AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
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AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
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2014-05-13 15:44:31 +07:00
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>;
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};
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cpsw_sleep: cpsw_sleep {
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pinctrl-single,pins = <
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/* Slave 1 reset value */
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
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2014-05-13 15:44:31 +07:00
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>;
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};
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davinci_mdio_default: davinci_mdio_default {
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pinctrl-single,pins = <
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/* MDIO */
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
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AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
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2014-05-13 15:44:31 +07:00
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>;
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};
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davinci_mdio_sleep: davinci_mdio_sleep {
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pinctrl-single,pins = <
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/* MDIO reset value */
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
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AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
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2014-05-13 15:44:31 +07:00
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>;
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};
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2014-05-19 16:15:46 +07:00
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nand_flash_x8: nand_flash_x8 {
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pinctrl-single,pins = <
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2015-11-13 11:53:54 +07:00
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AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
|
|
|
|
AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
|
|
|
|
AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
|
|
|
|
AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
|
|
|
|
|
AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
|
|
|
|
AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
|
|
|
|
AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
|
|
|
|
AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
|
|
|
|
AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
2014-05-19 16:15:46 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2014-03-24 18:01:56 +07:00
|
|
|
|
|
|
|
|
dss_pins: dss_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
|
|
|
|
AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
|
|
|
|
|
AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
|
|
|
|
|
AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
|
|
|
|
|
AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
|
|
|
|
|
AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
|
|
|
|
|
AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
|
|
|
|
|
AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
|
|
|
|
|
AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
|
|
|
|
|
AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
|
2014-03-24 18:01:56 +07:00
|
|
|
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-07-02 21:06:24 +07:00
|
|
|
display_mux_pins: display_mux_pins {
|
2014-03-24 18:01:56 +07:00
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
/* GPIO 5_8 to select LCD / HDMI */
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
|
2014-03-24 18:01:56 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2014-07-18 12:59:11 +07:00
|
|
|
|
|
|
|
|
dcan0_default: dcan0_default_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
|
|
|
|
|
AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
|
2014-07-18 12:59:11 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2015-08-18 21:01:57 +07:00
|
|
|
dcan0_sleep: dcan0_sleep_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */
|
|
|
|
|
AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */
|
2015-08-18 21:01:57 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-18 12:59:11 +07:00
|
|
|
dcan1_default: dcan1_default_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
|
|
|
|
|
AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
|
2014-07-18 12:59:11 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2014-12-18 23:24:14 +07:00
|
|
|
|
2015-08-18 21:01:57 +07:00
|
|
|
dcan1_sleep: dcan1_sleep_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */
|
|
|
|
|
AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */
|
2015-08-18 21:01:57 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-12-18 23:24:14 +07:00
|
|
|
vpfe0_pins_default: vpfe0_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
|
2014-12-18 23:24:14 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vpfe0_pins_sleep: vpfe0_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
|
2014-12-18 23:24:14 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vpfe1_pins_default: vpfe1_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
|
2014-12-18 23:24:14 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
vpfe1_pins_sleep: vpfe1_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
|
|
|
|
|
AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
|
2014-12-18 23:24:14 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2015-05-04 19:24:24 +07:00
|
|
|
|
|
|
|
|
mmc3_pins_default: pinmux_mmc3_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */
|
|
|
|
|
AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
|
|
|
|
|
AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
|
|
|
|
|
AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
|
|
|
|
|
AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
|
|
|
|
|
AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */
|
2015-05-04 19:24:24 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */
|
|
|
|
|
AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */
|
|
|
|
|
AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */
|
|
|
|
|
AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */
|
|
|
|
|
AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */
|
|
|
|
|
AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */
|
2015-05-04 19:24:24 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wlan_pins_default: pinmux_wlan_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
|
|
|
|
AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
|
|
|
|
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
2015-05-04 19:24:24 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
wlan_pins_sleep: pinmux_wlan_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */
|
|
|
|
|
AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/
|
|
|
|
|
AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/
|
2015-05-04 19:24:24 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3_pins: uart3_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */
|
|
|
|
|
AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
|
|
|
|
|
AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */
|
|
|
|
|
AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
|
2015-05-04 19:24:24 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2015-07-02 21:06:27 +07:00
|
|
|
|
|
|
|
|
mcasp1_pins: mcasp1_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
|
|
|
|
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
|
|
|
|
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
|
|
|
|
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
2015-07-02 21:06:27 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcasp1_sleep_pins: mcasp1_sleep_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
|
|
|
|
AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
|
2015-07-02 21:06:27 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2015-08-04 22:34:59 +07:00
|
|
|
|
|
|
|
|
gpio0_pins: gpio0_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
|
2015-08-04 22:34:59 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2015-08-04 22:35:00 +07:00
|
|
|
|
|
|
|
|
emmc_pins_default: emmc_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
|
|
|
|
|
AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
|
|
|
|
|
AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
|
|
|
|
|
AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
|
|
|
|
|
AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
|
|
|
|
|
AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
|
|
|
|
|
AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
|
|
|
|
|
AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
|
|
|
|
|
AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
|
|
|
|
|
AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
|
2015-08-04 22:35:00 +07:00
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emmc_pins_sleep: emmc_pins_sleep {
|
|
|
|
|
pinctrl-single,pins = <
|
2015-11-13 11:53:54 +07:00
|
|
|
AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
|
|
|
|
|
AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
|
|
|
|
|
AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
|
|
|
|
|
AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
|
|
|
|
|
AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
|
|
|
|
|
AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
|
|
|
|
|
AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
|
|
|
|
|
AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
|
|
|
|
|
AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
|
|
|
|
|
AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
|
2015-08-04 22:35:00 +07:00
|
|
|
>;
|
|
|
|
|
};
|
2017-03-22 22:36:34 +07:00
|
|
|
|
|
|
|
|
uart0_pins_default: uart0_pins_default {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
AM4372_IOPAD(0x968, PIN_INPUT | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
|
|
|
|
|
AM4372_IOPAD(0x96C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
|
|
|
|
|
AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
|
|
|
|
AM4372_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
|
|
|
|
>;
|
|
|
|
|
};
|
2017-06-20 12:09:21 +07:00
|
|
|
|
|
|
|
|
beeper_pins: beeper_pins {
|
|
|
|
|
pinctrl-single,pins = <
|
|
|
|
|
AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-22 22:36:34 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart0_pins_default>;
|
2013-12-19 19:33:38 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&i2c0 {
|
2014-07-09 12:36:31 +07:00
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c0_pins>;
|
2014-09-04 01:46:21 +07:00
|
|
|
clock-frequency = <100000>;
|
2014-07-09 12:36:32 +07:00
|
|
|
|
|
|
|
|
tps65218: tps65218@24 {
|
|
|
|
|
reg = <0x24>;
|
|
|
|
|
compatible = "ti,tps65218";
|
2018-05-08 20:20:50 +07:00
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
|
2014-07-09 12:36:32 +07:00
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
|
|
|
|
|
dcdc1: regulator-dcdc1 {
|
|
|
|
|
regulator-name = "vdd_core";
|
|
|
|
|
regulator-min-microvolt = <912000>;
|
|
|
|
|
regulator-max-microvolt = <1144000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdc2: regulator-dcdc2 {
|
|
|
|
|
regulator-name = "vdd_mpu";
|
|
|
|
|
regulator-min-microvolt = <912000>;
|
|
|
|
|
regulator-max-microvolt = <1378000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdc3: regulator-dcdc3 {
|
|
|
|
|
regulator-name = "vdcdc3";
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
2016-08-11 12:27:48 +07:00
|
|
|
regulator-state-mem {
|
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
|
};
|
2016-08-11 12:27:49 +07:00
|
|
|
regulator-state-disk {
|
|
|
|
|
regulator-off-in-suspend;
|
|
|
|
|
};
|
2014-07-09 12:36:32 +07:00
|
|
|
};
|
2016-08-11 12:27:48 +07:00
|
|
|
|
2014-07-09 12:36:32 +07:00
|
|
|
dcdc5: regulator-dcdc5 {
|
|
|
|
|
regulator-name = "v1_0bat";
|
|
|
|
|
regulator-min-microvolt = <1000000>;
|
|
|
|
|
regulator-max-microvolt = <1000000>;
|
2015-08-05 17:49:46 +07:00
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
2016-08-11 12:27:48 +07:00
|
|
|
regulator-state-mem {
|
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
|
};
|
2014-07-09 12:36:32 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dcdc6: regulator-dcdc6 {
|
|
|
|
|
regulator-name = "v1_8bat";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
2015-08-05 17:49:46 +07:00
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
2016-08-11 12:27:48 +07:00
|
|
|
regulator-state-mem {
|
|
|
|
|
regulator-on-in-suspend;
|
|
|
|
|
};
|
2014-07-09 12:36:32 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ldo1: regulator-ldo1 {
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
};
|
2015-03-13 06:38:21 +07:00
|
|
|
|
|
|
|
|
ov2659@30 {
|
|
|
|
|
compatible = "ovti,ov2659";
|
|
|
|
|
reg = <0x30>;
|
|
|
|
|
|
|
|
|
|
clocks = <&refclk 0>;
|
|
|
|
|
clock-names = "xvclk";
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
ov2659_0: endpoint {
|
|
|
|
|
remote-endpoint = <&vpfe1_ep>;
|
|
|
|
|
link-frequencies = /bits/ 64 <70000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-12-19 19:33:38 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&i2c1 {
|
2014-07-09 12:36:31 +07:00
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c1_pins>;
|
2014-04-30 19:43:25 +07:00
|
|
|
pixcir_ts@5c {
|
|
|
|
|
compatible = "pixcir,pixcir_tangoc";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pixcir_ts_pins>;
|
|
|
|
|
reg = <0x5c>;
|
|
|
|
|
|
|
|
|
|
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
|
2015-10-14 20:54:25 +07:00
|
|
|
/*
|
|
|
|
|
* 0x264 represents the offset of padconf register of
|
|
|
|
|
* gpio3_22 from am43xx_pinmux base.
|
|
|
|
|
*/
|
2015-12-28 20:52:39 +07:00
|
|
|
interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
|
2015-10-14 20:54:25 +07:00
|
|
|
<&am43xx_pinmux 0x264>;
|
|
|
|
|
interrupt-names = "tsc", "wakeup";
|
|
|
|
|
|
2014-07-29 00:11:37 +07:00
|
|
|
touchscreen-size-x = <1024>;
|
|
|
|
|
touchscreen-size-y = <600>;
|
2015-10-14 20:54:25 +07:00
|
|
|
wakeup-source;
|
2014-04-30 19:43:25 +07:00
|
|
|
};
|
2015-03-13 06:38:21 +07:00
|
|
|
|
|
|
|
|
ov2659@30 {
|
|
|
|
|
compatible = "ovti,ov2659";
|
|
|
|
|
reg = <0x30>;
|
|
|
|
|
|
|
|
|
|
clocks = <&refclk 0>;
|
|
|
|
|
clock-names = "xvclk";
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
ov2659_1: endpoint {
|
|
|
|
|
remote-endpoint = <&vpfe0_ep>;
|
|
|
|
|
link-frequencies = /bits/ 64 <70000000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2015-07-02 21:06:26 +07:00
|
|
|
|
|
|
|
|
tlv320aic3106: tlv320aic3106@1b {
|
2015-07-02 21:06:28 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2015-07-02 21:06:26 +07:00
|
|
|
compatible = "ti,tlv320aic3106";
|
|
|
|
|
reg = <0x1b>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
/* Regulators */
|
|
|
|
|
IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
|
|
|
|
|
AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
|
|
|
|
|
DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
|
|
|
|
|
DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
|
|
|
|
|
};
|
2013-12-19 19:33:38 +07:00
|
|
|
};
|
2013-12-19 19:33:39 +07:00
|
|
|
|
|
|
|
|
&epwmss0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2014-11-21 17:14:22 +07:00
|
|
|
&tscadc {
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
adc {
|
|
|
|
|
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-19 19:33:39 +07:00
|
|
|
&ecap0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&ecap0_pins>;
|
|
|
|
|
};
|
2013-12-19 19:33:40 +07:00
|
|
|
|
2014-03-03 21:50:18 +07:00
|
|
|
&gpio0 {
|
2015-08-04 22:34:59 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&gpio0_pins>;
|
2014-03-03 21:50:18 +07:00
|
|
|
status = "okay";
|
2015-08-04 22:34:59 +07:00
|
|
|
|
|
|
|
|
p23 {
|
|
|
|
|
gpio-hog;
|
|
|
|
|
gpios = <23 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
/* SelEMMCorNAND selects between eMMC and NAND:
|
|
|
|
|
* Low: NAND
|
|
|
|
|
* High: eMMC
|
|
|
|
|
* When changing this line make sure the newly
|
|
|
|
|
* selected device node is enabled and the previously
|
|
|
|
|
* selected device node is disabled.
|
|
|
|
|
*/
|
|
|
|
|
output-low;
|
|
|
|
|
line-name = "SelEMMCorNAND";
|
|
|
|
|
};
|
2014-03-03 21:50:18 +07:00
|
|
|
};
|
|
|
|
|
|
2015-05-04 19:24:24 +07:00
|
|
|
&gpio1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2013-12-19 19:33:40 +07:00
|
|
|
&gpio3 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&gpio4 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-03-03 21:50:18 +07:00
|
|
|
|
2014-03-21 12:20:13 +07:00
|
|
|
&gpio5 {
|
2015-07-02 21:06:24 +07:00
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&display_mux_pins>;
|
2014-03-21 12:20:13 +07:00
|
|
|
status = "okay";
|
|
|
|
|
ti,no-reset-on-init;
|
2015-07-02 21:06:24 +07:00
|
|
|
|
|
|
|
|
p8 {
|
|
|
|
|
/*
|
|
|
|
|
* SelLCDorHDMI selects between display and audio paths:
|
|
|
|
|
* Low: HDMI display with audio via HDMI
|
|
|
|
|
* High: LCD display with analog audio via aic3111 codec
|
|
|
|
|
*/
|
|
|
|
|
gpio-hog;
|
|
|
|
|
gpios = <8 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
output-high;
|
|
|
|
|
line-name = "SelLCDorHDMI";
|
|
|
|
|
};
|
2014-03-21 12:20:13 +07:00
|
|
|
};
|
|
|
|
|
|
2014-03-03 21:50:18 +07:00
|
|
|
&mmc1 {
|
|
|
|
|
status = "okay";
|
2015-07-02 21:06:25 +07:00
|
|
|
vmmc-supply = <&evm_v3_3d>;
|
2014-03-03 21:50:18 +07:00
|
|
|
bus-width = <4>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&mmc1_pins>;
|
2015-10-12 16:07:11 +07:00
|
|
|
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
2014-03-03 21:50:18 +07:00
|
|
|
};
|
2014-03-19 17:10:02 +07:00
|
|
|
|
2015-08-04 22:35:00 +07:00
|
|
|
/* eMMC sits on mmc2 */
|
|
|
|
|
&mmc2 {
|
|
|
|
|
/*
|
|
|
|
|
* When enabling eMMC, disable GPMC/NAND and set
|
|
|
|
|
* SelEMMCorNAND to output-high
|
|
|
|
|
*/
|
|
|
|
|
status = "disabled";
|
|
|
|
|
vmmc-supply = <&evm_v3_3d>;
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&emmc_pins_default>;
|
|
|
|
|
pinctrl-1 = <&emmc_pins_sleep>;
|
|
|
|
|
ti,non-removable;
|
|
|
|
|
};
|
|
|
|
|
|
2015-05-04 19:24:24 +07:00
|
|
|
&mmc3 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
/* these are on the crossbar and are outlined in the
|
|
|
|
|
xbar-event-map element */
|
2015-12-17 20:33:37 +07:00
|
|
|
dmas = <&edma_xbar 30 0 1>,
|
|
|
|
|
<&edma_xbar 31 0 2>;
|
2015-05-04 19:24:24 +07:00
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
vmmc-supply = <&vmmcwl_fixed>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&mmc3_pins_default>;
|
|
|
|
|
pinctrl-1 = <&mmc3_pins_sleep>;
|
|
|
|
|
cap-power-off-card;
|
|
|
|
|
keep-power-in-suspend;
|
|
|
|
|
ti,non-removable;
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
wlcore: wlcore@0 {
|
|
|
|
|
compatible = "ti,wl1835";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
interrupt-parent = <&gpio1>;
|
2018-07-03 13:57:20 +07:00
|
|
|
interrupts = <23 IRQ_TYPE_EDGE_RISING>;
|
2015-05-04 19:24:24 +07:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&uart3 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&uart3_pins>;
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-19 17:10:02 +07:00
|
|
|
&usb2_phy1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usb1 {
|
2018-03-16 18:11:43 +07:00
|
|
|
dr_mode = "otg";
|
2014-03-19 17:10:02 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usb2_phy2 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usb2 {
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-05-13 15:44:31 +07:00
|
|
|
|
|
|
|
|
&mac {
|
|
|
|
|
slaves = <1>;
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&cpsw_default>;
|
|
|
|
|
pinctrl-1 = <&cpsw_sleep>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&davinci_mdio {
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&davinci_mdio_default>;
|
|
|
|
|
pinctrl-1 = <&davinci_mdio_sleep>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&cpsw_emac0 {
|
|
|
|
|
phy_id = <&davinci_mdio>, <0>;
|
|
|
|
|
phy-mode = "rgmii";
|
|
|
|
|
};
|
2014-05-19 16:15:46 +07:00
|
|
|
|
|
|
|
|
&elm {
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&gpmc {
|
2015-08-04 22:35:00 +07:00
|
|
|
/*
|
|
|
|
|
* When enabling GPMC, disable eMMC and set
|
|
|
|
|
* SelEMMCorNAND to output-low
|
|
|
|
|
*/
|
2014-05-19 16:15:46 +07:00
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&nand_flash_x8>;
|
2016-02-23 23:37:19 +07:00
|
|
|
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
|
2014-05-19 16:15:46 +07:00
|
|
|
nand@0,0 {
|
2016-02-23 23:37:19 +07:00
|
|
|
compatible = "ti,omap2-nand";
|
2014-05-19 16:15:46 +07:00
|
|
|
reg = <0 0 4>; /* device IO registers */
|
2016-02-23 23:37:19 +07:00
|
|
|
interrupt-parent = <&gpmc>;
|
|
|
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
|
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
2016-04-07 17:25:38 +07:00
|
|
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
2017-07-26 09:15:51 +07:00
|
|
|
ti,nand-xfer-type = "prefetch-dma";
|
2014-09-02 20:57:03 +07:00
|
|
|
ti,nand-ecc-opt = "bch16";
|
2014-05-19 16:15:46 +07:00
|
|
|
ti,elm-id = <&elm>;
|
|
|
|
|
nand-bus-width = <8>;
|
|
|
|
|
gpmc,device-width = <1>;
|
|
|
|
|
gpmc,sync-clk-ps = <0>;
|
|
|
|
|
gpmc,cs-on-ns = <0>;
|
|
|
|
|
gpmc,cs-rd-off-ns = <40>;
|
|
|
|
|
gpmc,cs-wr-off-ns = <40>;
|
|
|
|
|
gpmc,adv-on-ns = <0>;
|
|
|
|
|
gpmc,adv-rd-off-ns = <25>;
|
|
|
|
|
gpmc,adv-wr-off-ns = <25>;
|
|
|
|
|
gpmc,we-on-ns = <0>;
|
|
|
|
|
gpmc,we-off-ns = <20>;
|
|
|
|
|
gpmc,oe-on-ns = <3>;
|
|
|
|
|
gpmc,oe-off-ns = <30>;
|
|
|
|
|
gpmc,access-ns = <30>;
|
|
|
|
|
gpmc,rd-cycle-ns = <40>;
|
|
|
|
|
gpmc,wr-cycle-ns = <40>;
|
|
|
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
|
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
|
|
|
gpmc,clk-activation-ns = <0>;
|
|
|
|
|
gpmc,wr-access-ns = <40>;
|
|
|
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
|
|
|
/* MTD partition table */
|
|
|
|
|
/* All SPL-* partitions are sized to minimal length
|
|
|
|
|
* which can be independently programmable. For
|
|
|
|
|
* NAND flash this is equal to size of erase-block */
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
partition@0 {
|
|
|
|
|
label = "NAND.SPL";
|
|
|
|
|
reg = <0x00000000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@1 {
|
|
|
|
|
label = "NAND.SPL.backup1";
|
|
|
|
|
reg = <0x00040000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@2 {
|
|
|
|
|
label = "NAND.SPL.backup2";
|
|
|
|
|
reg = <0x00080000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@3 {
|
|
|
|
|
label = "NAND.SPL.backup3";
|
|
|
|
|
reg = <0x000c0000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@4 {
|
|
|
|
|
label = "NAND.u-boot-spl-os";
|
|
|
|
|
reg = <0x00100000 0x00080000>;
|
|
|
|
|
};
|
|
|
|
|
partition@5 {
|
|
|
|
|
label = "NAND.u-boot";
|
|
|
|
|
reg = <0x00180000 0x00100000>;
|
|
|
|
|
};
|
|
|
|
|
partition@6 {
|
|
|
|
|
label = "NAND.u-boot-env";
|
|
|
|
|
reg = <0x00280000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@7 {
|
|
|
|
|
label = "NAND.u-boot-env.backup1";
|
|
|
|
|
reg = <0x002c0000 0x00040000>;
|
|
|
|
|
};
|
|
|
|
|
partition@8 {
|
|
|
|
|
label = "NAND.kernel";
|
|
|
|
|
reg = <0x00300000 0x00700000>;
|
|
|
|
|
};
|
|
|
|
|
partition@9 {
|
|
|
|
|
label = "NAND.file-system";
|
|
|
|
|
reg = <0x00a00000 0x1f600000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-03-24 18:01:56 +07:00
|
|
|
|
|
|
|
|
&dss {
|
|
|
|
|
status = "ok";
|
|
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&dss_pins>;
|
|
|
|
|
|
|
|
|
|
port {
|
2016-06-28 02:21:04 +07:00
|
|
|
dpi_out: endpoint {
|
2014-03-24 18:01:56 +07:00
|
|
|
remote-endpoint = <&lcd_in>;
|
|
|
|
|
data-lines = <24>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-07-18 12:59:11 +07:00
|
|
|
|
|
|
|
|
&dcan0 {
|
2015-08-18 21:01:57 +07:00
|
|
|
pinctrl-names = "default", "sleep";
|
2014-07-18 12:59:11 +07:00
|
|
|
pinctrl-0 = <&dcan0_default>;
|
2015-08-18 21:01:57 +07:00
|
|
|
pinctrl-1 = <&dcan0_sleep>;
|
2014-07-18 12:59:11 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&dcan1 {
|
2015-08-18 21:01:57 +07:00
|
|
|
pinctrl-names = "default", "sleep";
|
2014-07-18 12:59:11 +07:00
|
|
|
pinctrl-0 = <&dcan1_default>;
|
2015-08-18 21:01:57 +07:00
|
|
|
pinctrl-1 = <&dcan1_sleep>;
|
2014-07-18 12:59:11 +07:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
2014-12-18 23:24:14 +07:00
|
|
|
|
|
|
|
|
&vpfe0 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&vpfe0_pins_default>;
|
|
|
|
|
pinctrl-1 = <&vpfe0_pins_sleep>;
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
vpfe0_ep: endpoint {
|
2015-03-13 06:38:21 +07:00
|
|
|
remote-endpoint = <&ov2659_1>;
|
2014-12-18 23:24:14 +07:00
|
|
|
ti,am437x-vpfe-interface = <0>;
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
hsync-active = <0>;
|
|
|
|
|
vsync-active = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&vpfe1 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&vpfe1_pins_default>;
|
|
|
|
|
pinctrl-1 = <&vpfe1_pins_sleep>;
|
|
|
|
|
|
|
|
|
|
port {
|
|
|
|
|
vpfe1_ep: endpoint {
|
2015-03-13 06:38:21 +07:00
|
|
|
remote-endpoint = <&ov2659_0>;
|
2014-12-18 23:24:14 +07:00
|
|
|
ti,am437x-vpfe-interface = <0>;
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
hsync-active = <0>;
|
|
|
|
|
vsync-active = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2015-07-02 21:06:27 +07:00
|
|
|
|
|
|
|
|
&mcasp1 {
|
2015-07-02 21:06:28 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2015-07-02 21:06:27 +07:00
|
|
|
pinctrl-names = "default", "sleep";
|
|
|
|
|
pinctrl-0 = <&mcasp1_pins>;
|
|
|
|
|
pinctrl-1 = <&mcasp1_sleep_pins>;
|
|
|
|
|
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
|
|
|
tdm-slots = <2>;
|
|
|
|
|
/* 4 serializers */
|
|
|
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
|
|
|
0 0 1 2
|
|
|
|
|
>;
|
|
|
|
|
tx-num-evt = <32>;
|
|
|
|
|
rx-num-evt = <32>;
|
|
|
|
|
};
|
2015-08-18 16:41:14 +07:00
|
|
|
|
|
|
|
|
&rtc {
|
|
|
|
|
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
|
|
|
|
|
clock-names = "ext-clk", "int-clk";
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
2016-05-19 06:36:30 +07:00
|
|
|
|
|
|
|
|
&cpu {
|
|
|
|
|
cpu0-supply = <&dcdc2>;
|
|
|
|
|
};
|
