2011-04-04 10:46:58 +07:00
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/*
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* Common definitions accross all variants of ICP and ICS interrupt
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* controllers.
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*/
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#ifndef _XICS_H
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#define _XICS_H
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2011-04-15 05:31:58 +07:00
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#include <linux/interrupt.h>
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2011-04-04 10:46:58 +07:00
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#define XICS_IPI 2
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#define XICS_IRQ_SPURIOUS 0
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/* Want a priority other than 0. Various HW issues require this. */
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#define DEFAULT_PRIORITY 5
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/*
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2011-10-22 06:56:27 +07:00
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* Mark IPIs as higher priority so we can take them inside interrupts
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* FIXME: still true now?
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2011-04-04 10:46:58 +07:00
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*/
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#define IPI_PRIORITY 4
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/* The least favored priority */
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#define LOWEST_PRIORITY 0xFF
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/* The number of priorities defined above */
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#define MAX_NUM_PRIORITIES 3
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/* Native ICP */
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2011-09-20 00:45:02 +07:00
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#ifdef CONFIG_PPC_ICP_NATIVE
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2011-04-04 10:46:58 +07:00
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extern int icp_native_init(void);
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2011-09-20 00:45:02 +07:00
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#else
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static inline int icp_native_init(void) { return -ENODEV; }
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#endif
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2011-04-04 10:46:58 +07:00
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/* PAPR ICP */
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2011-09-20 00:45:02 +07:00
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#ifdef CONFIG_PPC_ICP_HV
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2011-04-04 10:46:58 +07:00
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extern int icp_hv_init(void);
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2011-09-20 00:45:02 +07:00
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#else
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static inline int icp_hv_init(void) { return -ENODEV; }
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#endif
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2011-04-04 10:46:58 +07:00
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/* ICP ops */
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struct icp_ops {
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unsigned int (*get_irq)(void);
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void (*eoi)(struct irq_data *d);
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void (*set_priority)(unsigned char prio);
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void (*teardown_cpu)(void);
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void (*flush_ipi)(void);
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#ifdef CONFIG_SMP
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powerpc: Consolidate ipi message mux and demux
Consolidate the mux and demux of ipi messages into smp.c and call
a new smp_ops callback to actually trigger the ipi.
The powerpc architecture code is optimised for having 4 distinct
ipi triggers, which are mapped to 4 distinct messages (ipi many, ipi
single, scheduler ipi, and enter debugger). However, several interrupt
controllers only provide a single software triggered interrupt that
can be delivered to each cpu. To resolve this limitation, each smp_ops
implementation created a per-cpu variable that is manipulated with atomic
bitops. Since these lines will be contended they are optimialy marked as
shared_aligned and take a full cache line for each cpu. Distro kernels
may have 2 or 3 of these in their config, each taking per-cpu space
even though at most one will be in use.
This consolidation removes smp_message_recv and replaces the single call
actions cases with direct calls from the common message recognition loop.
The complicated debugger ipi case with its muxed crash handling code is
moved to debug_ipi_action which is now called from the demux code (instead
of the multi-message action calling smp_message_recv).
I put a call to reschedule_action to increase the likelyhood of correctly
merging the anticipated scheduler_ipi() hook coming from the scheduler
tree; that single required call can be inlined later.
The actual message decode is a copy of the old pseries xics code with its
memory barriers and cache line spacing, augmented with a per-cpu unsigned
long based on the book-e doorbell code. The optional data is set via a
callback from the implementation and is passed to the new cause-ipi hook
along with the logical cpu number. While currently only the doorbell
implemntation uses this data it should be almost zero cost to retrieve and
pass it -- it adds a single register load for the argument from the same
cache line to which we just completed a store and the register is dead
on return from the call. I extended the data element from unsigned int
to unsigned long in case some other code wanted to associate a pointer.
The doorbell check_self is replaced by a call to smp_muxed_ipi_resend,
conditioned on the CPU_DBELL feature. The ifdef guard could be relaxed
to CONFIG_SMP but I left it with BOOKE for now.
Also, the doorbell interrupt vector for book-e was not calling irq_enter
and irq_exit, which throws off cpu accounting and causes code to not
realize it is running in interrupt context. Add the missing calls.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2011-05-11 02:29:39 +07:00
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void (*cause_ipi)(int cpu, unsigned long data);
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2011-04-04 10:46:58 +07:00
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irq_handler_t ipi_action;
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#endif
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};
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extern const struct icp_ops *icp_ops;
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/* Native ICS */
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extern int ics_native_init(void);
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/* RTAS ICS */
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2011-09-20 00:45:02 +07:00
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#ifdef CONFIG_PPC_ICS_RTAS
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2011-04-04 10:46:58 +07:00
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extern int ics_rtas_init(void);
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2011-09-20 00:45:02 +07:00
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#else
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static inline int ics_rtas_init(void) { return -ENODEV; }
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#endif
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/* HAL ICS */
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#ifdef CONFIG_PPC_POWERNV
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extern int ics_opal_init(void);
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#else
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static inline int ics_opal_init(void) { return -ENODEV; }
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#endif
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2011-04-04 10:46:58 +07:00
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/* ICS instance, hooked up to chip_data of an irq */
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struct ics {
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struct list_head link;
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int (*map)(struct ics *ics, unsigned int virq);
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void (*mask_unknown)(struct ics *ics, unsigned long vec);
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long (*get_server)(struct ics *ics, unsigned long vec);
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2011-04-15 05:31:59 +07:00
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int (*host_match)(struct ics *ics, struct device_node *node);
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2011-04-04 10:46:58 +07:00
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char data[];
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};
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/* Commons */
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extern unsigned int xics_default_server;
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extern unsigned int xics_default_distrib_server;
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extern unsigned int xics_interrupt_server_size;
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2012-02-15 04:06:50 +07:00
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extern struct irq_domain *xics_host;
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2011-04-04 10:46:58 +07:00
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struct xics_cppr {
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unsigned char stack[MAX_NUM_PRIORITIES];
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int index;
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};
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DECLARE_PER_CPU(struct xics_cppr, xics_cppr);
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static inline void xics_push_cppr(unsigned int vec)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
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return;
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if (vec == XICS_IPI)
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os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
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else
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os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
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}
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static inline unsigned char xics_pop_cppr(void)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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if (WARN_ON(os_cppr->index < 1))
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return LOWEST_PRIORITY;
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return os_cppr->stack[--os_cppr->index];
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}
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static inline void xics_set_base_cppr(unsigned char cppr)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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/* we only really want to set the priority when there's
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* just one cppr value on the stack
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*/
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WARN_ON(os_cppr->index != 0);
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os_cppr->stack[0] = cppr;
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}
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static inline unsigned char xics_cppr_top(void)
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{
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struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
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return os_cppr->stack[os_cppr->index];
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}
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DECLARE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
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extern void xics_init(void);
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extern void xics_setup_cpu(void);
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extern void xics_update_irq_servers(void);
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extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
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extern void xics_mask_unknown_vec(unsigned int vec);
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extern irqreturn_t xics_ipi_dispatch(int cpu);
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extern int xics_smp_probe(void);
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extern void xics_register_ics(struct ics *ics);
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extern void xics_teardown_cpu(void);
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extern void xics_kexec_teardown_cpu(int secondary);
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extern void xics_migrate_irqs_away(void);
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2013-04-26 02:20:59 +07:00
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extern void icp_native_eoi(struct irq_data *d);
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2011-04-04 10:46:58 +07:00
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#ifdef CONFIG_SMP
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extern int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
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unsigned int strict_check);
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#else
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#define xics_get_irq_server(virq, cpumask, strict_check) (xics_default_server)
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#endif
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#endif /* _XICS_H */
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