2012-05-11 21:25:46 +07:00
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/*
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* core.c - ChipIdea USB IP core family device controller
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Description: ChipIdea USB IP core family device controller
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*
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* This driver is composed of several blocks:
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* - HW: hardware interface
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* - DBG: debug facilities (optional)
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* - UTIL: utilities
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* - ISR: interrupts handling
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* - ENDPT: endpoint operations (Gadget API)
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* - GADGET: gadget operations (Gadget API)
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* - BUS: bus glue code, bus abstraction layer
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*
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* Compile Options
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* - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
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* - STALL_IN: non-empty bulk-in pipes cannot be halted
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* if defined mass storage compliance succeeds but with warnings
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* => case 4: Hi > Dn
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* => case 5: Hi > Di
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* => case 8: Hi <> Do
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* if undefined usbtest 13 fails
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* - TRACE: enable function tracing (depends on DEBUG)
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*
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* Main Features
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* - Chapter 9 & Mass Storage Compliance with Gadget File Storage
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* - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
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* - Normal & LPM support
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*
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* USBTEST Report
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* - OK: 0-12, 13 (STALL_IN defined) & 14
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* - Not Supported: 15 & 16 (ISO)
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*
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* TODO List
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* - OTG
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2013-06-13 21:59:47 +07:00
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* - Interrupt Traffic
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2012-05-11 21:25:46 +07:00
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* - GET_STATUS(device) - always reports 0
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* - Gadget API (majority of optional features)
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* - Suspend & Remote Wakeup
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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2012-07-07 21:56:42 +07:00
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#include <linux/idr.h>
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2012-05-11 21:25:46 +07:00
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/otg.h>
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#include <linux/usb/chipidea.h>
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2013-06-13 21:59:56 +07:00
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#include <linux/usb/of.h>
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2014-02-19 12:41:43 +07:00
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#include <linux/of.h>
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2013-06-13 21:59:56 +07:00
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#include <linux/phy.h>
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2013-08-14 16:44:03 +07:00
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#include <linux/regulator/consumer.h>
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2012-05-11 21:25:46 +07:00
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#include "ci.h"
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#include "udc.h"
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#include "bits.h"
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2012-05-11 21:25:54 +07:00
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#include "host.h"
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2012-05-11 21:25:46 +07:00
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#include "debug.h"
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2013-08-14 16:44:06 +07:00
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#include "otg.h"
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2012-05-11 21:25:46 +07:00
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2012-05-11 21:25:47 +07:00
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/* Controller register map */
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2014-01-06 09:10:39 +07:00
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static const u8 ci_regs_nolpm[] = {
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[CAP_CAPLENGTH] = 0x00U,
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[CAP_HCCPARAMS] = 0x08U,
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[CAP_DCCPARAMS] = 0x24U,
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[CAP_TESTMODE] = 0x38U,
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[OP_USBCMD] = 0x00U,
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[OP_USBSTS] = 0x04U,
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0x64U,
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[OP_USBMODE] = 0x68U,
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[OP_ENDPTSETUPSTAT] = 0x6CU,
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[OP_ENDPTPRIME] = 0x70U,
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[OP_ENDPTFLUSH] = 0x74U,
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[OP_ENDPTSTAT] = 0x78U,
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[OP_ENDPTCOMPLETE] = 0x7CU,
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[OP_ENDPTCTRL] = 0x80U,
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2012-05-11 21:25:46 +07:00
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};
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2014-01-06 09:10:39 +07:00
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static const u8 ci_regs_lpm[] = {
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[CAP_CAPLENGTH] = 0x00U,
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[CAP_HCCPARAMS] = 0x08U,
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[CAP_DCCPARAMS] = 0x24U,
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[CAP_TESTMODE] = 0xFCU,
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[OP_USBCMD] = 0x00U,
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[OP_USBSTS] = 0x04U,
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[OP_USBINTR] = 0x08U,
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[OP_DEVICEADDR] = 0x14U,
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[OP_ENDPTLISTADDR] = 0x18U,
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[OP_PORTSC] = 0x44U,
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[OP_DEVLC] = 0x84U,
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[OP_OTGSC] = 0xC4U,
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[OP_USBMODE] = 0xC8U,
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[OP_ENDPTSETUPSTAT] = 0xD8U,
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[OP_ENDPTPRIME] = 0xDCU,
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[OP_ENDPTFLUSH] = 0xE0U,
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[OP_ENDPTSTAT] = 0xE4U,
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[OP_ENDPTCOMPLETE] = 0xE8U,
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[OP_ENDPTCTRL] = 0xECU,
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2012-05-11 21:25:46 +07:00
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};
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2013-06-24 18:46:36 +07:00
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static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
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2012-05-11 21:25:46 +07:00
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{
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int i;
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for (i = 0; i < OP_ENDPTCTRL; i++)
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.regmap[i] =
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(i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
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2012-05-11 21:25:46 +07:00
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(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
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for (; i <= OP_LAST; i++)
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.regmap[i] = ci->hw_bank.op +
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2012-05-11 21:25:46 +07:00
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4 * (i - OP_ENDPTCTRL) +
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(is_lpm
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? ci_regs_lpm[OP_ENDPTCTRL]
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: ci_regs_nolpm[OP_ENDPTCTRL]);
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return 0;
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}
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/**
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* hw_port_test_set: writes port test mode (execute without interruption)
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* @mode: new value
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*
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* This function returns an error code
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*/
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2013-06-24 18:46:36 +07:00
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int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
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2012-05-11 21:25:46 +07:00
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{
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const u8 TEST_MODE_MAX = 7;
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if (mode > TEST_MODE_MAX)
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return -EINVAL;
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2013-03-30 17:53:55 +07:00
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hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
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2012-05-11 21:25:46 +07:00
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return 0;
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}
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/**
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* hw_port_test_get: reads port test mode value
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*
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* This function returns port test mode value
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*/
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2013-06-24 18:46:36 +07:00
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u8 hw_port_test_get(struct ci_hdrc *ci)
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2012-05-11 21:25:46 +07:00
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{
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2013-03-30 17:53:55 +07:00
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return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
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2012-05-11 21:25:46 +07:00
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}
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2013-09-24 11:47:55 +07:00
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/* The PHY enters/leaves low power mode */
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static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
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{
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enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
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bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
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if (enable && !lpm) {
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hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
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PORTSC_PHCD(ci->hw_bank.lpm));
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} else if (!enable && lpm) {
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hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
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0);
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/*
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* The controller needs at least 1ms to reflect
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* PHY's status, the PHY also needs some time (less
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* than 1ms) to leave low power mode.
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*/
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usleep_range(1500, 2000);
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}
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}
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2013-06-24 18:46:36 +07:00
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static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
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2012-05-11 21:25:46 +07:00
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{
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u32 reg;
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/* bank is a module variable */
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.abs = base;
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2012-05-11 21:25:46 +07:00
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.cap = ci->hw_bank.abs;
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2012-06-29 16:48:53 +07:00
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ci->hw_bank.cap += ci->platdata->capoffset;
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2013-03-30 17:54:03 +07:00
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ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
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2012-05-11 21:25:46 +07:00
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2012-05-11 21:25:47 +07:00
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hw_alloc_regmap(ci, false);
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reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
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2013-03-30 17:53:55 +07:00
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__ffs(HCCPARAMS_LEN);
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.lpm = reg;
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2013-12-06 15:35:12 +07:00
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if (reg)
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hw_alloc_regmap(ci, !!reg);
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2012-05-11 21:25:47 +07:00
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ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
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ci->hw_bank.size += OP_LAST;
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ci->hw_bank.size /= sizeof(u32);
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2012-05-11 21:25:46 +07:00
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2012-05-11 21:25:47 +07:00
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reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
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2013-03-30 17:53:55 +07:00
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__ffs(DCCPARAMS_DEN);
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2012-05-11 21:25:47 +07:00
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ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
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2012-05-11 21:25:46 +07:00
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2012-05-15 20:58:18 +07:00
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if (ci->hw_ep_max > ENDPT_MAX)
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2012-05-11 21:25:46 +07:00
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return -ENODEV;
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2013-09-24 11:47:55 +07:00
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ci_hdrc_enter_lpm(ci, false);
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2013-08-14 16:44:09 +07:00
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/* Disable all interrupts bits */
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hw_write(ci, OP_USBINTR, 0xffffffff, 0);
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/* Clear all interrupts status bits*/
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hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
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2012-05-11 21:25:47 +07:00
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dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
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ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
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2012-05-11 21:25:46 +07:00
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/* setup lock mode ? */
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/* ENDPTSETUPSTAT is '0' by default */
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/* HCSPARAMS.bf.ppc SHOULD BE zero for device */
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return 0;
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}
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2013-06-24 18:46:36 +07:00
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static void hw_phymode_configure(struct ci_hdrc *ci)
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2013-06-13 21:59:56 +07:00
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{
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2014-01-10 12:51:29 +07:00
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u32 portsc, lpm, sts = 0;
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2013-06-13 21:59:56 +07:00
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switch (ci->platdata->phy_mode) {
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case USBPHY_INTERFACE_MODE_UTMI:
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portsc = PORTSC_PTS(PTS_UTMI);
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lpm = DEVLC_PTS(PTS_UTMI);
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break;
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case USBPHY_INTERFACE_MODE_UTMIW:
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portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
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lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
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break;
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case USBPHY_INTERFACE_MODE_ULPI:
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portsc = PORTSC_PTS(PTS_ULPI);
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lpm = DEVLC_PTS(PTS_ULPI);
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break;
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case USBPHY_INTERFACE_MODE_SERIAL:
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portsc = PORTSC_PTS(PTS_SERIAL);
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lpm = DEVLC_PTS(PTS_SERIAL);
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sts = 1;
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break;
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case USBPHY_INTERFACE_MODE_HSIC:
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portsc = PORTSC_PTS(PTS_HSIC);
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lpm = DEVLC_PTS(PTS_HSIC);
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break;
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default:
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return;
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}
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if (ci->hw_bank.lpm) {
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hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
|
2014-01-10 12:51:29 +07:00
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if (sts)
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hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
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2013-06-13 21:59:56 +07:00
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} else {
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hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
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2014-01-10 12:51:29 +07:00
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if (sts)
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hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
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2013-06-13 21:59:56 +07:00
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}
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}
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2014-04-23 14:56:37 +07:00
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/**
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* ci_usb_phy_init: initialize phy according to different phy type
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* @ci: the controller
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*
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* This function returns an error code if usb_phy_init has failed
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*/
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static int ci_usb_phy_init(struct ci_hdrc *ci)
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{
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int ret;
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switch (ci->platdata->phy_mode) {
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case USBPHY_INTERFACE_MODE_UTMI:
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case USBPHY_INTERFACE_MODE_UTMIW:
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case USBPHY_INTERFACE_MODE_HSIC:
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ret = usb_phy_init(ci->transceiver);
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if (ret)
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return ret;
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hw_phymode_configure(ci);
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break;
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case USBPHY_INTERFACE_MODE_ULPI:
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case USBPHY_INTERFACE_MODE_SERIAL:
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hw_phymode_configure(ci);
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ret = usb_phy_init(ci->transceiver);
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if (ret)
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return ret;
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break;
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default:
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ret = usb_phy_init(ci->transceiver);
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}
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return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:46 +07:00
|
|
|
/**
|
|
|
|
* hw_device_reset: resets chip (execute without interruption)
|
|
|
|
* @ci: the controller
|
|
|
|
*
|
|
|
|
* This function returns an error code
|
|
|
|
*/
|
2013-06-24 18:46:36 +07:00
|
|
|
int hw_device_reset(struct ci_hdrc *ci, u32 mode)
|
2012-05-11 21:25:46 +07:00
|
|
|
{
|
|
|
|
/* should flush & stop before reset */
|
|
|
|
hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
|
|
|
|
hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
|
|
|
|
|
|
|
|
hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
|
|
|
|
while (hw_read(ci, OP_USBCMD, USBCMD_RST))
|
|
|
|
udelay(10); /* not RTOS friendly */
|
|
|
|
|
2012-06-29 16:48:53 +07:00
|
|
|
if (ci->platdata->notify_event)
|
|
|
|
ci->platdata->notify_event(ci,
|
2013-06-24 18:46:36 +07:00
|
|
|
CI_HDRC_CONTROLLER_RESET_EVENT);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2013-06-24 18:46:36 +07:00
|
|
|
if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
|
2012-05-11 21:25:53 +07:00
|
|
|
hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2014-02-19 12:41:43 +07:00
|
|
|
if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
|
|
|
|
if (ci->hw_bank.lpm)
|
|
|
|
hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
|
|
|
|
else
|
|
|
|
hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
|
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:46 +07:00
|
|
|
/* USBMODE should be configured step by step */
|
|
|
|
hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
|
2012-05-11 21:25:54 +07:00
|
|
|
hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
|
2012-05-11 21:25:46 +07:00
|
|
|
/* HW >= 2.3 */
|
|
|
|
hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
|
|
|
|
|
2012-05-11 21:25:54 +07:00
|
|
|
if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
|
|
|
|
pr_err("cannot enter in %s mode", ci_role(ci)->name);
|
2012-05-11 21:25:46 +07:00
|
|
|
pr_err("lpm = %i", ci->hw_bank.lpm);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-08-14 16:44:12 +07:00
|
|
|
/**
|
|
|
|
* hw_wait_reg: wait the register value
|
|
|
|
*
|
|
|
|
* Sometimes, it needs to wait register value before going on.
|
|
|
|
* Eg, when switch to device mode, the vbus value should be lower
|
|
|
|
* than OTGSC_BSV before connects to host.
|
|
|
|
*
|
|
|
|
* @ci: the controller
|
|
|
|
* @reg: register index
|
|
|
|
* @mask: mast bit
|
|
|
|
* @value: the bit value to wait
|
|
|
|
* @timeout_ms: timeout in millisecond
|
|
|
|
*
|
|
|
|
* This function returns an error code if timeout
|
|
|
|
*/
|
|
|
|
int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
|
|
|
|
u32 value, unsigned int timeout_ms)
|
|
|
|
{
|
|
|
|
unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
|
|
|
|
|
|
|
|
while (hw_read(ci, reg, mask) != value) {
|
|
|
|
if (time_after(jiffies, elapse)) {
|
|
|
|
dev_err(ci->dev, "timeout waiting for %08x in %d\n",
|
|
|
|
mask, reg);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
msleep(20);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
static irqreturn_t ci_irq(int irq, void *data)
|
|
|
|
{
|
2013-06-24 18:46:36 +07:00
|
|
|
struct ci_hdrc *ci = data;
|
2012-05-11 21:25:47 +07:00
|
|
|
irqreturn_t ret = IRQ_NONE;
|
2012-09-12 18:58:11 +07:00
|
|
|
u32 otgsc = 0;
|
2012-05-11 21:25:47 +07:00
|
|
|
|
2012-09-12 18:58:11 +07:00
|
|
|
if (ci->is_otg)
|
2014-04-23 14:56:38 +07:00
|
|
|
otgsc = hw_read_otgsc(ci, ~0);
|
2012-05-11 21:25:47 +07:00
|
|
|
|
2013-08-14 16:44:11 +07:00
|
|
|
/*
|
|
|
|
* Handle id change interrupt, it indicates device/host function
|
|
|
|
* switch.
|
|
|
|
*/
|
|
|
|
if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
|
|
|
|
ci->id_event = true;
|
2014-04-23 14:56:38 +07:00
|
|
|
/* Clear ID change irq status */
|
|
|
|
hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
|
2013-08-14 16:44:11 +07:00
|
|
|
disable_irq_nosync(ci->irq);
|
|
|
|
queue_work(ci->wq, &ci->work);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
2012-09-12 18:58:11 +07:00
|
|
|
|
2013-08-14 16:44:11 +07:00
|
|
|
/*
|
|
|
|
* Handle vbus change interrupt, it indicates device connection
|
|
|
|
* and disconnection events.
|
|
|
|
*/
|
|
|
|
if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
|
|
|
|
ci->b_sess_valid_event = true;
|
2014-04-23 14:56:38 +07:00
|
|
|
/* Clear BSV irq */
|
|
|
|
hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
|
2012-09-12 18:58:11 +07:00
|
|
|
disable_irq_nosync(ci->irq);
|
|
|
|
queue_work(ci->wq, &ci->work);
|
2013-08-14 16:44:11 +07:00
|
|
|
return IRQ_HANDLED;
|
2012-05-11 21:25:47 +07:00
|
|
|
}
|
|
|
|
|
2013-08-14 16:44:11 +07:00
|
|
|
/* Handle device/host interrupt */
|
|
|
|
if (ci->role != CI_ROLE_END)
|
|
|
|
ret = ci_role(ci)->irq(ci);
|
|
|
|
|
2012-09-12 18:58:11 +07:00
|
|
|
return ret;
|
2012-05-11 21:25:47 +07:00
|
|
|
}
|
|
|
|
|
2013-08-14 16:44:03 +07:00
|
|
|
static int ci_get_platdata(struct device *dev,
|
|
|
|
struct ci_hdrc_platform_data *platdata)
|
|
|
|
{
|
2013-09-17 11:37:22 +07:00
|
|
|
if (!platdata->phy_mode)
|
|
|
|
platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
|
|
|
|
|
|
|
|
if (!platdata->dr_mode)
|
|
|
|
platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
|
|
|
|
|
|
|
|
if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
|
|
|
|
platdata->dr_mode = USB_DR_MODE_OTG;
|
|
|
|
|
2013-10-30 08:19:29 +07:00
|
|
|
if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
|
|
|
|
/* Get the vbus regulator */
|
|
|
|
platdata->reg_vbus = devm_regulator_get(dev, "vbus");
|
|
|
|
if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
} else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
|
|
|
|
/* no vbus regualator is needed */
|
|
|
|
platdata->reg_vbus = NULL;
|
|
|
|
} else if (IS_ERR(platdata->reg_vbus)) {
|
|
|
|
dev_err(dev, "Getting regulator error: %ld\n",
|
|
|
|
PTR_ERR(platdata->reg_vbus));
|
|
|
|
return PTR_ERR(platdata->reg_vbus);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-02-19 12:41:43 +07:00
|
|
|
if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
|
|
|
|
platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
|
|
|
|
|
2013-08-14 16:44:03 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-07 21:56:42 +07:00
|
|
|
static DEFINE_IDA(ci_ida);
|
|
|
|
|
2013-06-24 18:46:36 +07:00
|
|
|
struct platform_device *ci_hdrc_add_device(struct device *dev,
|
2012-07-07 21:56:41 +07:00
|
|
|
struct resource *res, int nres,
|
2013-06-24 18:46:36 +07:00
|
|
|
struct ci_hdrc_platform_data *platdata)
|
2012-07-07 21:56:41 +07:00
|
|
|
{
|
|
|
|
struct platform_device *pdev;
|
2012-07-07 21:56:42 +07:00
|
|
|
int id, ret;
|
2012-07-07 21:56:41 +07:00
|
|
|
|
2013-08-14 16:44:03 +07:00
|
|
|
ret = ci_get_platdata(dev, platdata);
|
|
|
|
if (ret)
|
|
|
|
return ERR_PTR(ret);
|
|
|
|
|
2012-07-07 21:56:42 +07:00
|
|
|
id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
|
|
|
|
if (id < 0)
|
|
|
|
return ERR_PTR(id);
|
|
|
|
|
|
|
|
pdev = platform_device_alloc("ci_hdrc", id);
|
|
|
|
if (!pdev) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto put_id;
|
|
|
|
}
|
2012-07-07 21:56:41 +07:00
|
|
|
|
|
|
|
pdev->dev.parent = dev;
|
|
|
|
pdev->dev.dma_mask = dev->dma_mask;
|
|
|
|
pdev->dev.dma_parms = dev->dma_parms;
|
|
|
|
dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
|
|
|
|
|
|
|
|
ret = platform_device_add_resources(pdev, res, nres);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
ret = platform_device_add(pdev);
|
|
|
|
if (ret)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return pdev;
|
|
|
|
|
|
|
|
err:
|
|
|
|
platform_device_put(pdev);
|
2012-07-07 21:56:42 +07:00
|
|
|
put_id:
|
|
|
|
ida_simple_remove(&ci_ida, id);
|
2012-07-07 21:56:41 +07:00
|
|
|
return ERR_PTR(ret);
|
|
|
|
}
|
2013-06-24 18:46:36 +07:00
|
|
|
EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
|
2012-07-07 21:56:41 +07:00
|
|
|
|
2013-06-24 18:46:36 +07:00
|
|
|
void ci_hdrc_remove_device(struct platform_device *pdev)
|
2012-07-07 21:56:41 +07:00
|
|
|
{
|
2012-11-22 16:11:25 +07:00
|
|
|
int id = pdev->id;
|
2012-07-07 21:56:41 +07:00
|
|
|
platform_device_unregister(pdev);
|
2012-11-22 16:11:25 +07:00
|
|
|
ida_simple_remove(&ci_ida, id);
|
2012-07-07 21:56:41 +07:00
|
|
|
}
|
2013-06-24 18:46:36 +07:00
|
|
|
EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
|
2012-07-07 21:56:41 +07:00
|
|
|
|
2013-08-14 16:44:07 +07:00
|
|
|
static inline void ci_role_destroy(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
ci_hdrc_gadget_destroy(ci);
|
|
|
|
ci_hdrc_host_destroy(ci);
|
2013-08-14 16:44:10 +07:00
|
|
|
if (ci->is_otg)
|
|
|
|
ci_hdrc_otg_destroy(ci);
|
2013-08-14 16:44:07 +07:00
|
|
|
}
|
|
|
|
|
2013-08-14 16:44:08 +07:00
|
|
|
static void ci_get_otg_capable(struct ci_hdrc *ci)
|
|
|
|
{
|
|
|
|
if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
|
|
|
|
ci->is_otg = false;
|
|
|
|
else
|
|
|
|
ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
|
|
|
|
DCCPARAMS_DC | DCCPARAMS_HC)
|
|
|
|
== (DCCPARAMS_DC | DCCPARAMS_HC));
|
2013-08-14 16:44:09 +07:00
|
|
|
if (ci->is_otg) {
|
2013-08-14 16:44:08 +07:00
|
|
|
dev_dbg(ci->dev, "It is OTG capable controller\n");
|
2014-04-23 14:56:38 +07:00
|
|
|
/* Disable and clear all OTG irq */
|
|
|
|
hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
|
|
|
|
OTGSC_INT_STATUS_BITS);
|
2013-08-14 16:44:09 +07:00
|
|
|
}
|
2013-08-14 16:44:08 +07:00
|
|
|
}
|
|
|
|
|
2012-11-20 01:21:48 +07:00
|
|
|
static int ci_hdrc_probe(struct platform_device *pdev)
|
2012-05-11 21:25:46 +07:00
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
2013-06-24 18:46:36 +07:00
|
|
|
struct ci_hdrc *ci;
|
2012-05-11 21:25:46 +07:00
|
|
|
struct resource *res;
|
|
|
|
void __iomem *base;
|
|
|
|
int ret;
|
2013-06-13 21:59:57 +07:00
|
|
|
enum usb_dr_mode dr_mode;
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2014-02-19 12:41:42 +07:00
|
|
|
if (!dev_get_platdata(dev)) {
|
2012-05-11 21:25:46 +07:00
|
|
|
dev_err(dev, "platform data missing\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2013-03-30 07:46:27 +07:00
|
|
|
base = devm_ioremap_resource(dev, res);
|
|
|
|
if (IS_ERR(base))
|
|
|
|
return PTR_ERR(base);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
|
|
|
|
if (!ci) {
|
|
|
|
dev_err(dev, "can't allocate device\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
ci->dev = dev;
|
2014-02-19 12:41:42 +07:00
|
|
|
ci->platdata = dev_get_platdata(dev);
|
2014-01-10 12:51:27 +07:00
|
|
|
ci->imx28_write_fix = !!(ci->platdata->flags &
|
|
|
|
CI_HDRC_IMX28_WRITE_FIX);
|
2012-05-11 21:25:47 +07:00
|
|
|
|
|
|
|
ret = hw_device_init(ci, base);
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(dev, "can't initialize hardware\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2014-02-19 12:41:40 +07:00
|
|
|
if (ci->platdata->phy)
|
|
|
|
ci->transceiver = ci->platdata->phy;
|
|
|
|
else
|
|
|
|
ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
|
|
|
|
|
|
|
|
if (IS_ERR(ci->transceiver)) {
|
|
|
|
ret = PTR_ERR(ci->transceiver);
|
|
|
|
/*
|
|
|
|
* if -ENXIO is returned, it means PHY layer wasn't
|
|
|
|
* enabled, so it makes no sense to return -EPROBE_DEFER
|
|
|
|
* in that case, since no PHY driver will ever probe.
|
|
|
|
*/
|
|
|
|
if (ret == -ENXIO)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dev_err(dev, "no usb2 phy configured\n");
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
}
|
|
|
|
|
2014-04-23 14:56:37 +07:00
|
|
|
ret = ci_usb_phy_init(ci);
|
2013-09-24 11:47:53 +07:00
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "unable to init phy: %d\n", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:54 +07:00
|
|
|
ci->hw_bank.phys = res->start;
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
ci->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (ci->irq < 0) {
|
2012-05-11 21:25:46 +07:00
|
|
|
dev_err(dev, "missing IRQ\n");
|
2014-02-19 12:41:44 +07:00
|
|
|
ret = ci->irq;
|
2014-02-19 12:41:40 +07:00
|
|
|
goto deinit_phy;
|
2012-05-11 21:25:47 +07:00
|
|
|
}
|
|
|
|
|
2013-08-14 16:44:08 +07:00
|
|
|
ci_get_otg_capable(ci);
|
|
|
|
|
2013-06-13 21:59:57 +07:00
|
|
|
dr_mode = ci->platdata->dr_mode;
|
2012-05-11 21:25:47 +07:00
|
|
|
/* initialize role(s) before the interrupt is requested */
|
2013-06-13 21:59:57 +07:00
|
|
|
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
|
|
|
|
ret = ci_hdrc_host_init(ci);
|
|
|
|
if (ret)
|
|
|
|
dev_info(dev, "doesn't support host\n");
|
|
|
|
}
|
2012-05-11 21:25:54 +07:00
|
|
|
|
2013-06-13 21:59:57 +07:00
|
|
|
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
|
|
|
|
ret = ci_hdrc_gadget_init(ci);
|
|
|
|
if (ret)
|
|
|
|
dev_info(dev, "doesn't support gadget\n");
|
|
|
|
}
|
2012-05-11 21:25:47 +07:00
|
|
|
|
|
|
|
if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
|
|
|
|
dev_err(dev, "no supported roles\n");
|
2013-09-24 11:47:53 +07:00
|
|
|
ret = -ENODEV;
|
2014-02-19 12:41:40 +07:00
|
|
|
goto deinit_phy;
|
2013-08-14 16:44:10 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ci->is_otg) {
|
|
|
|
ret = ci_hdrc_otg_init(ci);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "init otg fails, ret = %d\n", ret);
|
|
|
|
goto stop;
|
|
|
|
}
|
2012-05-11 21:25:47 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
|
2013-08-14 16:44:08 +07:00
|
|
|
if (ci->is_otg) {
|
|
|
|
/*
|
|
|
|
* ID pin needs 1ms debouce time,
|
|
|
|
* we delay 2ms for safe.
|
|
|
|
*/
|
|
|
|
mdelay(2);
|
|
|
|
ci->role = ci_otg_role(ci);
|
2014-04-23 14:56:38 +07:00
|
|
|
/* Enable ID change irq */
|
|
|
|
hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
|
2013-08-14 16:44:08 +07:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* If the controller is not OTG capable, but support
|
|
|
|
* role switch, the defalt role is gadget, and the
|
|
|
|
* user can switch it through debugfs.
|
|
|
|
*/
|
|
|
|
ci->role = CI_ROLE_GADGET;
|
|
|
|
}
|
2012-05-11 21:25:47 +07:00
|
|
|
} else {
|
|
|
|
ci->role = ci->roles[CI_ROLE_HOST]
|
|
|
|
? CI_ROLE_HOST
|
|
|
|
: CI_ROLE_GADGET;
|
|
|
|
}
|
|
|
|
|
2013-12-05 14:20:50 +07:00
|
|
|
/* only update vbus status for peripheral */
|
|
|
|
if (ci->role == CI_ROLE_GADGET)
|
|
|
|
ci_handle_vbus_change(ci);
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
ret = ci_role_start(ci, ci->role);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
|
2013-08-14 16:44:10 +07:00
|
|
|
goto stop;
|
2012-05-11 21:25:46 +07:00
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
platform_set_drvdata(pdev, ci);
|
2012-06-29 16:48:53 +07:00
|
|
|
ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
|
2012-05-11 21:25:47 +07:00
|
|
|
ci);
|
|
|
|
if (ret)
|
|
|
|
goto stop;
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2013-03-30 17:53:53 +07:00
|
|
|
ret = dbg_create_files(ci);
|
|
|
|
if (!ret)
|
|
|
|
return 0;
|
2012-05-11 21:25:47 +07:00
|
|
|
|
2013-03-30 17:53:53 +07:00
|
|
|
free_irq(ci->irq, ci);
|
2012-05-11 21:25:47 +07:00
|
|
|
stop:
|
2013-08-14 16:44:07 +07:00
|
|
|
ci_role_destroy(ci);
|
2014-02-19 12:41:40 +07:00
|
|
|
deinit_phy:
|
|
|
|
usb_phy_shutdown(ci->transceiver);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-20 01:26:20 +07:00
|
|
|
static int ci_hdrc_remove(struct platform_device *pdev)
|
2012-05-11 21:25:46 +07:00
|
|
|
{
|
2013-06-24 18:46:36 +07:00
|
|
|
struct ci_hdrc *ci = platform_get_drvdata(pdev);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2013-03-30 17:53:53 +07:00
|
|
|
dbg_remove_files(ci);
|
2012-05-11 21:25:47 +07:00
|
|
|
free_irq(ci->irq, ci);
|
2013-08-14 16:44:07 +07:00
|
|
|
ci_role_destroy(ci);
|
2013-09-24 11:47:55 +07:00
|
|
|
ci_hdrc_enter_lpm(ci, true);
|
2014-02-19 12:41:40 +07:00
|
|
|
usb_phy_shutdown(ci->transceiver);
|
|
|
|
kfree(ci->hw_bank.regmap);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
static struct platform_driver ci_hdrc_driver = {
|
|
|
|
.probe = ci_hdrc_probe,
|
2012-11-20 01:21:08 +07:00
|
|
|
.remove = ci_hdrc_remove,
|
2012-05-11 21:25:46 +07:00
|
|
|
.driver = {
|
2012-05-11 21:25:47 +07:00
|
|
|
.name = "ci_hdrc",
|
2012-05-11 21:25:46 +07:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
module_platform_driver(ci_hdrc_driver);
|
2012-05-11 21:25:46 +07:00
|
|
|
|
2012-05-11 21:25:47 +07:00
|
|
|
MODULE_ALIAS("platform:ci_hdrc");
|
2012-05-11 21:25:46 +07:00
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
|
2012-05-11 21:25:47 +07:00
|
|
|
MODULE_DESCRIPTION("ChipIdea HDRC Driver");
|