2017-11-03 17:28:30 +07:00
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// SPDX-License-Identifier: GPL-2.0+
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2011-03-10 07:28:56 +07:00
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/*
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* EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
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*
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* Copyright (C) 2010 Google, Inc.
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2013-01-18 03:15:37 +07:00
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* Copyright (C) 2009 - 2013 NVIDIA Corporation
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2011-03-10 07:28:56 +07:00
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*/
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#include <linux/clk.h>
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2013-06-14 00:24:12 +07:00
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#include <linux/dma-mapping.h>
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2012-06-26 19:10:32 +07:00
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#include <linux/err.h>
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2011-11-04 16:12:40 +07:00
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#include <linux/gpio.h>
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2013-06-14 00:24:12 +07:00
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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2011-11-04 16:12:40 +07:00
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#include <linux/of.h>
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2013-08-12 20:06:54 +07:00
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#include <linux/of_device.h>
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2011-11-04 16:12:40 +07:00
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#include <linux/of_gpio.h>
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2013-06-14 00:24:12 +07:00
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#include <linux/platform_device.h>
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2012-05-01 22:28:49 +07:00
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#include <linux/pm_runtime.h>
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2013-11-07 06:53:58 +07:00
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#include <linux/reset.h>
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2013-06-14 00:24:12 +07:00
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#include <linux/slab.h>
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2013-01-18 03:15:37 +07:00
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#include <linux/usb/ehci_def.h>
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2012-09-05 20:20:23 +07:00
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#include <linux/usb/tegra_usb_phy.h>
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2013-06-14 00:24:12 +07:00
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#include <linux/usb.h>
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#include <linux/usb/hcd.h>
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#include <linux/usb/otg.h>
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#include "ehci.h"
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2012-10-03 05:49:25 +07:00
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2013-06-14 00:24:12 +07:00
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#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
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2011-03-10 07:28:57 +07:00
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#define TEGRA_USB_DMA_ALIGN 32
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2013-06-14 00:24:12 +07:00
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#define DRIVER_DESC "Tegra EHCI driver"
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#define DRV_NAME "tegra-ehci"
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static struct hc_driver __read_mostly tegra_ehci_hc_driver;
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2013-08-12 20:06:54 +07:00
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struct tegra_ehci_soc_config {
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bool has_hostpc;
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};
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2011-03-10 07:28:56 +07:00
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struct tegra_ehci_hcd {
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struct tegra_usb_phy *phy;
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struct clk *clk;
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2013-11-07 06:53:58 +07:00
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struct reset_control *rst;
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2011-03-10 07:28:56 +07:00
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int port_resuming;
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2012-12-14 03:59:08 +07:00
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bool needs_double_reset;
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2011-03-10 07:28:56 +07:00
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enum tegra_usb_phy_port_speed port_speed;
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};
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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static int tegra_reset_usb_controller(struct platform_device *pdev)
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{
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struct device_node *phy_np;
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struct usb_hcd *hcd = platform_get_drvdata(pdev);
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struct tegra_ehci_hcd *tegra =
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(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
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2018-04-10 05:02:58 +07:00
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struct reset_control *rst;
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int err;
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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phy_np = of_parse_phandle(pdev->dev.of_node, "nvidia,phy", 0);
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if (!phy_np)
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return -ENOENT;
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2018-04-10 05:02:58 +07:00
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/*
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* The 1st USB controller contains some UTMI pad registers that are
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* global for all the controllers on the chip. Those registers are
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* also cleared when reset is asserted to the 1st controller.
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*/
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rst = of_reset_control_get_shared(phy_np, "utmi-pads");
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if (IS_ERR(rst)) {
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dev_warn(&pdev->dev,
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"can't get utmi-pads reset from the PHY\n");
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dev_warn(&pdev->dev,
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"continuing, but please update your DT\n");
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} else {
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/*
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* PHY driver performs UTMI-pads reset in a case of
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* non-legacy DT.
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*/
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reset_control_put(rst);
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}
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2016-05-26 22:23:30 +07:00
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2018-04-10 05:02:58 +07:00
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of_node_put(phy_np);
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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2018-04-10 05:02:58 +07:00
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/* reset control is shared, hence initialize it first */
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err = reset_control_deassert(tegra->rst);
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if (err)
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return err;
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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2018-04-10 05:02:58 +07:00
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err = reset_control_assert(tegra->rst);
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if (err)
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return err;
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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2018-04-10 05:02:58 +07:00
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udelay(1);
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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2018-04-10 05:02:58 +07:00
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err = reset_control_deassert(tegra->rst);
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if (err)
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return err;
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USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
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return 0;
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}
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2011-04-17 15:58:25 +07:00
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static int tegra_ehci_internal_port_reset(
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struct ehci_hcd *ehci,
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u32 __iomem *portsc_reg
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)
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{
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u32 temp;
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unsigned long flags;
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int retval = 0;
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int i, tries;
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u32 saved_usbintr;
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spin_lock_irqsave(&ehci->lock, flags);
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saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
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/* disable USB interrupt */
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ehci_writel(ehci, 0, &ehci->regs->intr_enable);
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spin_unlock_irqrestore(&ehci->lock, flags);
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/*
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* Here we have to do Port Reset at most twice for
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* Port Enable bit to be set.
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*/
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for (i = 0; i < 2; i++) {
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temp = ehci_readl(ehci, portsc_reg);
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temp |= PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(10);
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temp &= ~PORT_RESET;
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ehci_writel(ehci, temp, portsc_reg);
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mdelay(1);
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tries = 100;
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do {
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mdelay(1);
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/*
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* Up to this point, Port Enable bit is
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* expected to be set after 2 ms waiting.
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* USB1 usually takes extra 45 ms, for safety,
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* we take 100 ms as timeout.
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*/
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temp = ehci_readl(ehci, portsc_reg);
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} while (!(temp & PORT_PE) && tries--);
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if (temp & PORT_PE)
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break;
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}
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if (i == 2)
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retval = -ETIMEDOUT;
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/*
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* Clear Connect Status Change bit if it's set.
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* We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
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*/
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if (temp & PORT_CSC)
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ehci_writel(ehci, PORT_CSC, portsc_reg);
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/*
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* Write to clear any interrupt status bits that might be set
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* during port reset.
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*/
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temp = ehci_readl(ehci, &ehci->regs->status);
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ehci_writel(ehci, temp, &ehci->regs->status);
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/* restore original interrupt enable bits */
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ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
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return retval;
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}
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2011-03-10 07:28:56 +07:00
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static int tegra_ehci_hub_control(
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struct usb_hcd *hcd,
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u16 typeReq,
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u16 wValue,
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u16 wIndex,
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char *buf,
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u16 wLength
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)
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{
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2013-06-14 00:24:13 +07:00
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
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2011-03-10 07:28:56 +07:00
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u32 __iomem *status_reg;
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u32 temp;
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unsigned long flags;
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int retval = 0;
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status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
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spin_lock_irqsave(&ehci->lock, flags);
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2012-04-19 04:32:46 +07:00
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if (typeReq == GetPortStatus) {
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2011-03-10 07:28:56 +07:00
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temp = ehci_readl(ehci, status_reg);
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if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
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/* Resume completed, re-enable disconnect detection */
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tegra->port_resuming = 0;
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2014-09-25 02:05:50 +07:00
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tegra_usb_phy_postresume(hcd->usb_phy);
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2011-03-10 07:28:56 +07:00
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}
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}
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else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
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temp = ehci_readl(ehci, status_reg);
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if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
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retval = -EPIPE;
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goto done;
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}
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2012-04-26 01:31:10 +07:00
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temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
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2011-03-10 07:28:56 +07:00
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temp |= PORT_WKDISC_E | PORT_WKOC_E;
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ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
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/*
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* If a transaction is in progress, there may be a delay in
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* suspending the port. Poll until the port is suspended.
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*/
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2013-06-14 00:24:09 +07:00
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if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
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2011-03-10 07:28:56 +07:00
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PORT_SUSPEND, 5000))
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pr_err("%s: timeout waiting for SUSPEND\n", __func__);
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set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
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|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2011-04-17 15:58:25 +07:00
|
|
|
/* For USB1 port we need to issue Port Reset twice internally */
|
2012-12-14 03:59:08 +07:00
|
|
|
if (tegra->needs_double_reset &&
|
2011-04-17 15:58:25 +07:00
|
|
|
(typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
|
|
|
|
spin_unlock_irqrestore(&ehci->lock, flags);
|
|
|
|
return tegra_ehci_internal_port_reset(ehci, status_reg);
|
|
|
|
}
|
|
|
|
|
2011-03-10 07:28:56 +07:00
|
|
|
/*
|
|
|
|
* Tegra host controller will time the resume operation to clear the bit
|
|
|
|
* when the port control state switches to HS or FS Idle. This behavior
|
|
|
|
* is different from EHCI where the host controller driver is required
|
|
|
|
* to set this bit to a zero after the resume duration is timed in the
|
|
|
|
* driver.
|
|
|
|
*/
|
|
|
|
else if (typeReq == ClearPortFeature &&
|
|
|
|
wValue == USB_PORT_FEAT_SUSPEND) {
|
|
|
|
temp = ehci_readl(ehci, status_reg);
|
|
|
|
if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
|
|
|
|
retval = -EPIPE;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(temp & PORT_SUSPEND))
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
/* Disable disconnect detection during port resume */
|
2014-09-25 02:05:50 +07:00
|
|
|
tegra_usb_phy_preresume(hcd->usb_phy);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
|
|
|
ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
|
|
|
|
|
|
|
|
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
|
|
|
|
/* start resume signalling */
|
|
|
|
ehci_writel(ehci, temp | PORT_RESUME, status_reg);
|
2012-04-04 02:24:30 +07:00
|
|
|
set_bit(wIndex-1, &ehci->resuming_ports);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&ehci->lock, flags);
|
|
|
|
msleep(20);
|
|
|
|
spin_lock_irqsave(&ehci->lock, flags);
|
|
|
|
|
|
|
|
/* Poll until the controller clears RESUME and SUSPEND */
|
2013-06-14 00:24:09 +07:00
|
|
|
if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
|
2011-03-10 07:28:56 +07:00
|
|
|
pr_err("%s: timeout waiting for RESUME\n", __func__);
|
2013-06-14 00:24:09 +07:00
|
|
|
if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
|
2011-03-10 07:28:56 +07:00
|
|
|
pr_err("%s: timeout waiting for SUSPEND\n", __func__);
|
|
|
|
|
|
|
|
ehci->reset_done[wIndex-1] = 0;
|
2012-04-04 02:24:30 +07:00
|
|
|
clear_bit(wIndex-1, &ehci->resuming_ports);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
|
|
|
tegra->port_resuming = 1;
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&ehci->lock, flags);
|
|
|
|
|
|
|
|
/* Handle the hub control events here */
|
2014-04-16 23:00:10 +07:00
|
|
|
return ehci_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
|
2013-06-14 00:24:12 +07:00
|
|
|
|
2011-03-10 07:28:56 +07:00
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&ehci->lock, flags);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
struct dma_aligned_buffer {
|
2011-03-10 07:28:57 +07:00
|
|
|
void *kmalloc_ptr;
|
|
|
|
void *old_xfer_buffer;
|
|
|
|
u8 data[0];
|
|
|
|
};
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
static void free_dma_aligned_buffer(struct urb *urb)
|
2011-03-10 07:28:57 +07:00
|
|
|
{
|
2012-04-05 12:55:30 +07:00
|
|
|
struct dma_aligned_buffer *temp;
|
2015-04-23 21:06:51 +07:00
|
|
|
size_t length;
|
2011-03-10 07:28:57 +07:00
|
|
|
|
|
|
|
if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
|
|
|
|
return;
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
temp = container_of(urb->transfer_buffer,
|
|
|
|
struct dma_aligned_buffer, data);
|
2011-03-10 07:28:57 +07:00
|
|
|
|
2015-04-23 21:06:51 +07:00
|
|
|
if (usb_urb_dir_in(urb)) {
|
|
|
|
if (usb_pipeisoc(urb->pipe))
|
|
|
|
length = urb->transfer_buffer_length;
|
|
|
|
else
|
|
|
|
length = urb->actual_length;
|
|
|
|
|
|
|
|
memcpy(temp->old_xfer_buffer, temp->data, length);
|
|
|
|
}
|
2011-03-10 07:28:57 +07:00
|
|
|
urb->transfer_buffer = temp->old_xfer_buffer;
|
|
|
|
kfree(temp->kmalloc_ptr);
|
|
|
|
|
|
|
|
urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
|
|
|
|
}
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
|
2011-03-10 07:28:57 +07:00
|
|
|
{
|
2012-04-05 12:55:30 +07:00
|
|
|
struct dma_aligned_buffer *temp, *kmalloc_ptr;
|
2011-03-10 07:28:57 +07:00
|
|
|
size_t kmalloc_size;
|
|
|
|
|
|
|
|
if (urb->num_sgs || urb->sg ||
|
|
|
|
urb->transfer_buffer_length == 0 ||
|
|
|
|
!((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Allocate a buffer with enough padding for alignment */
|
|
|
|
kmalloc_size = urb->transfer_buffer_length +
|
2012-04-05 12:55:30 +07:00
|
|
|
sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
|
2011-03-10 07:28:57 +07:00
|
|
|
|
|
|
|
kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
|
|
|
|
if (!kmalloc_ptr)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
/* Position our struct dma_aligned_buffer such that data is aligned */
|
2011-03-10 07:28:57 +07:00
|
|
|
temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
|
|
|
|
temp->kmalloc_ptr = kmalloc_ptr;
|
|
|
|
temp->old_xfer_buffer = urb->transfer_buffer;
|
2012-04-05 12:55:30 +07:00
|
|
|
if (usb_urb_dir_out(urb))
|
2011-03-10 07:28:57 +07:00
|
|
|
memcpy(temp->data, urb->transfer_buffer,
|
|
|
|
urb->transfer_buffer_length);
|
|
|
|
urb->transfer_buffer = temp->data;
|
|
|
|
|
|
|
|
urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
|
|
|
|
gfp_t mem_flags)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
2012-04-05 12:55:30 +07:00
|
|
|
ret = alloc_dma_aligned_buffer(urb, mem_flags);
|
2011-03-10 07:28:57 +07:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
|
|
|
|
if (ret)
|
2012-04-05 12:55:30 +07:00
|
|
|
free_dma_aligned_buffer(urb);
|
2011-03-10 07:28:57 +07:00
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
|
|
|
|
{
|
|
|
|
usb_hcd_unmap_urb_for_dma(hcd, urb);
|
2012-04-05 12:55:30 +07:00
|
|
|
free_dma_aligned_buffer(urb);
|
2011-03-10 07:28:57 +07:00
|
|
|
}
|
|
|
|
|
2013-08-12 20:06:54 +07:00
|
|
|
static const struct tegra_ehci_soc_config tegra30_soc_config = {
|
|
|
|
.has_hostpc = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct tegra_ehci_soc_config tegra20_soc_config = {
|
|
|
|
.has_hostpc = false,
|
|
|
|
};
|
|
|
|
|
2014-06-18 11:37:24 +07:00
|
|
|
static const struct of_device_id tegra_ehci_of_match[] = {
|
2013-08-12 20:06:54 +07:00
|
|
|
{ .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
|
|
|
|
{ .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
2011-03-10 07:28:56 +07:00
|
|
|
static int tegra_ehci_probe(struct platform_device *pdev)
|
|
|
|
{
|
2013-08-12 20:06:54 +07:00
|
|
|
const struct of_device_id *match;
|
|
|
|
const struct tegra_ehci_soc_config *soc_config;
|
2011-03-10 07:28:56 +07:00
|
|
|
struct resource *res;
|
|
|
|
struct usb_hcd *hcd;
|
2013-06-14 00:24:13 +07:00
|
|
|
struct ehci_hcd *ehci;
|
2011-03-10 07:28:56 +07:00
|
|
|
struct tegra_ehci_hcd *tegra;
|
|
|
|
int err = 0;
|
|
|
|
int irq;
|
2013-01-18 03:15:37 +07:00
|
|
|
struct usb_phy *u_phy;
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2013-08-12 20:06:54 +07:00
|
|
|
match = of_match_device(tegra_ehci_of_match, &pdev->dev);
|
|
|
|
if (!match) {
|
|
|
|
dev_err(&pdev->dev, "Error: No device match found\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
soc_config = match->data;
|
|
|
|
|
2011-11-04 16:12:40 +07:00
|
|
|
/* Right now device-tree probed devices don't get dma_mask set.
|
|
|
|
* Since shared usb code relies on it, set it here for now.
|
|
|
|
* Once we have dma capability bindings this can go away.
|
|
|
|
*/
|
2013-06-27 18:36:37 +07:00
|
|
|
err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
|
2013-06-10 22:28:49 +07:00
|
|
|
if (err)
|
|
|
|
return err;
|
2011-11-04 16:12:40 +07:00
|
|
|
|
2013-06-14 00:24:13 +07:00
|
|
|
hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
|
|
|
|
dev_name(&pdev->dev));
|
|
|
|
if (!hcd) {
|
|
|
|
dev_err(&pdev->dev, "Unable to create HCD\n");
|
2013-07-17 14:37:49 +07:00
|
|
|
return -ENOMEM;
|
2013-06-14 00:24:13 +07:00
|
|
|
}
|
|
|
|
platform_set_drvdata(pdev, hcd);
|
|
|
|
ehci = hcd_to_ehci(hcd);
|
|
|
|
tegra = (struct tegra_ehci_hcd *)ehci->priv;
|
|
|
|
|
|
|
|
hcd->has_tt = 1;
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2012-07-30 21:43:41 +07:00
|
|
|
tegra->clk = devm_clk_get(&pdev->dev, NULL);
|
2011-03-10 07:28:56 +07:00
|
|
|
if (IS_ERR(tegra->clk)) {
|
|
|
|
dev_err(&pdev->dev, "Can't get ehci clock\n");
|
2013-06-14 00:24:13 +07:00
|
|
|
err = PTR_ERR(tegra->clk);
|
|
|
|
goto cleanup_hcd_create;
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
|
|
|
|
2018-04-10 05:02:58 +07:00
|
|
|
tegra->rst = devm_reset_control_get_shared(&pdev->dev, "usb");
|
2013-11-07 06:53:58 +07:00
|
|
|
if (IS_ERR(tegra->rst)) {
|
|
|
|
dev_err(&pdev->dev, "Can't get ehci reset\n");
|
|
|
|
err = PTR_ERR(tegra->rst);
|
|
|
|
goto cleanup_hcd_create;
|
|
|
|
}
|
|
|
|
|
2012-06-05 11:29:38 +07:00
|
|
|
err = clk_prepare_enable(tegra->clk);
|
2011-03-10 07:28:56 +07:00
|
|
|
if (err)
|
2013-09-27 15:22:08 +07:00
|
|
|
goto cleanup_hcd_create;
|
2011-03-10 07:28:56 +07:00
|
|
|
|
USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
|
|
|
err = tegra_reset_usb_controller(pdev);
|
2018-04-10 05:02:58 +07:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to reset controller\n");
|
USB: EHCI: tegra: Fix probe order issue leading to broken USB
The Tegra USB complex has a particularly annoying misdesign: some of the
UTMI pad configuration registers are global for all the 3 USB controllers
on the chip, but those registers are located in the first controller's
register space and will be cleared when the reset to the first
controller is asserted. Currently, this means that if the 1st controller
were to finish probing after the 2nd or 3rd controller, USB would not
work at all.
Fix this situation by always resetting the 1st controller before doing
any other setup to any of the controllers, and then never ever reset the
first controller again. As the UTMI registers are related to the PHY,
the PHY driver should probably reset the Tegra controllers instead,
but since old device trees only have reset phandles in the EHCI nodes,
do it here, which means a bit of device tree groveling. Those old DTs
also won't get the reset fix from this commit, so we'll dev_warn() them,
but the driver will still keep probing successfully.
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-07-04 08:09:38 +07:00
|
|
|
goto cleanup_clk_en;
|
2018-04-10 05:02:58 +07:00
|
|
|
}
|
2013-04-03 17:41:12 +07:00
|
|
|
|
2013-07-26 01:38:06 +07:00
|
|
|
u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
|
2013-05-16 21:13:02 +07:00
|
|
|
if (IS_ERR(u_phy)) {
|
2014-12-24 17:16:30 +07:00
|
|
|
err = -EPROBE_DEFER;
|
2013-06-14 00:24:13 +07:00
|
|
|
goto cleanup_clk_en;
|
2013-05-16 21:13:02 +07:00
|
|
|
}
|
2014-09-25 02:05:50 +07:00
|
|
|
hcd->usb_phy = u_phy;
|
2018-03-04 04:43:03 +07:00
|
|
|
hcd->skip_phy_initialization = 1;
|
2013-05-16 21:13:02 +07:00
|
|
|
|
2012-12-14 03:59:08 +07:00
|
|
|
tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"nvidia,needs-double-reset");
|
|
|
|
|
2011-03-10 07:28:56 +07:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2014-05-10 19:00:09 +07:00
|
|
|
hcd->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(hcd->regs)) {
|
|
|
|
err = PTR_ERR(hcd->regs);
|
2013-06-14 00:24:13 +07:00
|
|
|
goto cleanup_clk_en;
|
2011-11-04 16:12:40 +07:00
|
|
|
}
|
2014-11-04 09:21:10 +07:00
|
|
|
hcd->rsrc_start = res->start;
|
|
|
|
hcd->rsrc_len = resource_size(res);
|
|
|
|
|
2013-06-14 00:24:13 +07:00
|
|
|
ehci->caps = hcd->regs + 0x100;
|
2013-08-12 20:06:54 +07:00
|
|
|
ehci->has_hostpc = soc_config->has_hostpc;
|
2011-11-04 16:12:40 +07:00
|
|
|
|
2014-09-25 02:05:50 +07:00
|
|
|
err = usb_phy_init(hcd->usb_phy);
|
2013-05-16 21:13:02 +07:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to initialize phy\n");
|
2013-06-14 00:24:13 +07:00
|
|
|
goto cleanup_clk_en;
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
|
|
|
|
2013-01-18 03:15:37 +07:00
|
|
|
u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!u_phy->otg) {
|
|
|
|
err = -ENOMEM;
|
2013-05-16 21:13:02 +07:00
|
|
|
goto cleanup_phy;
|
2013-01-18 03:15:37 +07:00
|
|
|
}
|
|
|
|
u_phy->otg->host = hcd_to_bus(hcd);
|
|
|
|
|
2014-09-25 02:05:50 +07:00
|
|
|
err = usb_phy_set_suspend(hcd->usb_phy, 0);
|
2011-03-10 07:28:56 +07:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to power on the phy\n");
|
2013-05-16 21:13:02 +07:00
|
|
|
goto cleanup_phy;
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
|
|
|
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (!irq) {
|
|
|
|
dev_err(&pdev->dev, "Failed to get IRQ\n");
|
|
|
|
err = -ENODEV;
|
2013-05-16 21:13:02 +07:00
|
|
|
goto cleanup_phy;
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
|
|
|
|
2013-07-26 01:38:02 +07:00
|
|
|
otg_set_host(u_phy->otg, &hcd->self);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2011-09-07 15:10:52 +07:00
|
|
|
err = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
2011-03-10 07:28:56 +07:00
|
|
|
if (err) {
|
|
|
|
dev_err(&pdev->dev, "Failed to add USB HCD\n");
|
2013-07-26 01:38:02 +07:00
|
|
|
goto cleanup_otg_set_host;
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
2013-11-05 09:46:02 +07:00
|
|
|
device_wakeup_enable(hcd->self.controller);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
|
|
|
return err;
|
|
|
|
|
2013-07-26 01:38:02 +07:00
|
|
|
cleanup_otg_set_host:
|
|
|
|
otg_set_host(u_phy->otg, NULL);
|
2013-06-14 18:21:21 +07:00
|
|
|
cleanup_phy:
|
2014-09-25 02:05:50 +07:00
|
|
|
usb_phy_shutdown(hcd->usb_phy);
|
2013-06-14 00:24:13 +07:00
|
|
|
cleanup_clk_en:
|
|
|
|
clk_disable_unprepare(tegra->clk);
|
2013-05-16 21:13:02 +07:00
|
|
|
cleanup_hcd_create:
|
2011-03-10 07:28:56 +07:00
|
|
|
usb_put_hcd(hcd);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tegra_ehci_remove(struct platform_device *pdev)
|
|
|
|
{
|
2013-06-14 00:24:13 +07:00
|
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
|
|
|
struct tegra_ehci_hcd *tegra =
|
|
|
|
(struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2014-09-25 02:05:50 +07:00
|
|
|
otg_set_host(hcd->usb_phy->otg, NULL);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2014-09-25 02:05:50 +07:00
|
|
|
usb_phy_shutdown(hcd->usb_phy);
|
2011-03-10 07:28:56 +07:00
|
|
|
usb_remove_hcd(hcd);
|
2012-08-10 13:12:43 +07:00
|
|
|
|
2018-04-10 05:02:58 +07:00
|
|
|
reset_control_assert(tegra->rst);
|
|
|
|
udelay(1);
|
|
|
|
|
2012-06-05 11:29:38 +07:00
|
|
|
clk_disable_unprepare(tegra->clk);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
2014-06-17 21:17:40 +07:00
|
|
|
usb_put_hcd(hcd);
|
|
|
|
|
2011-03-10 07:28:56 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
2013-06-14 00:24:13 +07:00
|
|
|
struct usb_hcd *hcd = platform_get_drvdata(pdev);
|
2011-03-10 07:28:56 +07:00
|
|
|
|
|
|
|
if (hcd->driver->shutdown)
|
|
|
|
hcd->driver->shutdown(hcd);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver tegra_ehci_driver = {
|
|
|
|
.probe = tegra_ehci_probe,
|
|
|
|
.remove = tegra_ehci_remove,
|
|
|
|
.shutdown = tegra_ehci_hcd_shutdown,
|
|
|
|
.driver = {
|
2013-06-14 00:24:12 +07:00
|
|
|
.name = DRV_NAME,
|
2011-11-04 16:12:40 +07:00
|
|
|
.of_match_table = tegra_ehci_of_match,
|
2011-03-10 07:28:56 +07:00
|
|
|
}
|
|
|
|
};
|
2013-06-14 00:24:12 +07:00
|
|
|
|
2014-04-15 04:21:23 +07:00
|
|
|
static int tegra_ehci_reset(struct usb_hcd *hcd)
|
|
|
|
{
|
|
|
|
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
|
|
|
|
int retval;
|
|
|
|
int txfifothresh;
|
|
|
|
|
|
|
|
retval = ehci_setup(hcd);
|
|
|
|
if (retval)
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We should really pull this value out of tegra_ehci_soc_config, but
|
|
|
|
* to avoid needing access to it, make use of the fact that Tegra20 is
|
|
|
|
* the only one so far that needs a value of 10, and Tegra20 is the
|
|
|
|
* only one which doesn't set has_hostpc.
|
|
|
|
*/
|
|
|
|
txfifothresh = ehci->has_hostpc ? 0x10 : 10;
|
|
|
|
ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-06-14 00:24:12 +07:00
|
|
|
static const struct ehci_driver_overrides tegra_overrides __initconst = {
|
|
|
|
.extra_priv_size = sizeof(struct tegra_ehci_hcd),
|
2014-04-15 04:21:23 +07:00
|
|
|
.reset = tegra_ehci_reset,
|
2013-06-14 00:24:12 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
static int __init ehci_tegra_init(void)
|
|
|
|
{
|
|
|
|
if (usb_disabled())
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
pr_info(DRV_NAME ": " DRIVER_DESC "\n");
|
|
|
|
|
|
|
|
ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The Tegra HW has some unusual quirks, which require Tegra-specific
|
|
|
|
* workarounds. We override certain hc_driver functions here to
|
|
|
|
* achieve that. We explicitly do not enhance ehci_driver_overrides to
|
|
|
|
* allow this more easily, since this is an unusual case, and we don't
|
|
|
|
* want to encourage others to override these functions by making it
|
|
|
|
* too easy.
|
|
|
|
*/
|
|
|
|
|
|
|
|
tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
|
|
|
|
tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
|
|
|
|
tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
|
|
|
|
|
|
|
|
return platform_driver_register(&tegra_ehci_driver);
|
|
|
|
}
|
|
|
|
module_init(ehci_tegra_init);
|
|
|
|
|
|
|
|
static void __exit ehci_tegra_cleanup(void)
|
|
|
|
{
|
|
|
|
platform_driver_unregister(&tegra_ehci_driver);
|
|
|
|
}
|
|
|
|
module_exit(ehci_tegra_cleanup);
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_ALIAS("platform:" DRV_NAME);
|
|
|
|
MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);
|