2018-09-11 02:27:58 +07:00
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include "panfrost_device.h"
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#include "panfrost_devfreq.h"
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#include "panfrost_features.h"
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#include "panfrost_gpu.h"
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#include "panfrost_job.h"
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#include "panfrost_mmu.h"
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static int panfrost_reset_init(struct panfrost_device *pfdev)
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{
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int err;
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pfdev->rstc = devm_reset_control_array_get(pfdev->dev, false, true);
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if (IS_ERR(pfdev->rstc)) {
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dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc));
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return PTR_ERR(pfdev->rstc);
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}
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err = reset_control_deassert(pfdev->rstc);
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if (err)
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return err;
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return 0;
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}
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static void panfrost_reset_fini(struct panfrost_device *pfdev)
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{
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reset_control_assert(pfdev->rstc);
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}
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static int panfrost_clk_init(struct panfrost_device *pfdev)
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{
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int err;
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unsigned long rate;
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pfdev->clock = devm_clk_get(pfdev->dev, NULL);
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if (IS_ERR(pfdev->clock)) {
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dev_err(pfdev->dev, "get clock failed %ld\n", PTR_ERR(pfdev->clock));
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return PTR_ERR(pfdev->clock);
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}
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rate = clk_get_rate(pfdev->clock);
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dev_info(pfdev->dev, "clock rate = %lu\n", rate);
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err = clk_prepare_enable(pfdev->clock);
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if (err)
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return err;
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2019-05-21 23:10:57 +07:00
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pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
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if (IS_ERR(pfdev->bus_clock)) {
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dev_err(pfdev->dev, "get bus_clock failed %ld\n",
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PTR_ERR(pfdev->bus_clock));
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return PTR_ERR(pfdev->bus_clock);
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}
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if (pfdev->bus_clock) {
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rate = clk_get_rate(pfdev->bus_clock);
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dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
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err = clk_prepare_enable(pfdev->bus_clock);
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if (err)
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goto disable_clock;
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}
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2018-09-11 02:27:58 +07:00
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return 0;
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2019-05-21 23:10:57 +07:00
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disable_clock:
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clk_disable_unprepare(pfdev->clock);
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return err;
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2018-09-11 02:27:58 +07:00
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}
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static void panfrost_clk_fini(struct panfrost_device *pfdev)
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{
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2019-05-21 23:10:57 +07:00
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clk_disable_unprepare(pfdev->bus_clock);
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2018-09-11 02:27:58 +07:00
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clk_disable_unprepare(pfdev->clock);
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}
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static int panfrost_regulator_init(struct panfrost_device *pfdev)
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{
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int ret;
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pfdev->regulator = devm_regulator_get_optional(pfdev->dev, "mali");
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if (IS_ERR(pfdev->regulator)) {
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ret = PTR_ERR(pfdev->regulator);
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pfdev->regulator = NULL;
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if (ret == -ENODEV)
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return 0;
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dev_err(pfdev->dev, "failed to get regulator: %d\n", ret);
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return ret;
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}
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ret = regulator_enable(pfdev->regulator);
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if (ret < 0) {
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dev_err(pfdev->dev, "failed to enable regulator: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static void panfrost_regulator_fini(struct panfrost_device *pfdev)
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{
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if (pfdev->regulator)
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regulator_disable(pfdev->regulator);
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}
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int panfrost_device_init(struct panfrost_device *pfdev)
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{
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int err;
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struct resource *res;
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mutex_init(&pfdev->sched_lock);
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2019-04-18 15:41:48 +07:00
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mutex_init(&pfdev->reset_lock);
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2018-09-11 02:27:58 +07:00
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INIT_LIST_HEAD(&pfdev->scheduled_jobs);
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spin_lock_init(&pfdev->hwaccess_lock);
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err = panfrost_clk_init(pfdev);
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if (err) {
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dev_err(pfdev->dev, "clk init failed %d\n", err);
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return err;
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}
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err = panfrost_regulator_init(pfdev);
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if (err) {
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dev_err(pfdev->dev, "regulator init failed %d\n", err);
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goto err_out0;
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}
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err = panfrost_reset_init(pfdev);
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if (err) {
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dev_err(pfdev->dev, "reset init failed %d\n", err);
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goto err_out1;
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}
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res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
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pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
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if (IS_ERR(pfdev->iomem)) {
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dev_err(pfdev->dev, "failed to ioremap iomem\n");
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err = PTR_ERR(pfdev->iomem);
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goto err_out2;
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}
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err = panfrost_gpu_init(pfdev);
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if (err)
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goto err_out2;
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err = panfrost_mmu_init(pfdev);
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if (err)
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goto err_out3;
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err = panfrost_job_init(pfdev);
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if (err)
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goto err_out4;
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/* runtime PM will wake us up later */
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panfrost_gpu_power_off(pfdev);
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pm_runtime_set_active(pfdev->dev);
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pm_runtime_get_sync(pfdev->dev);
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pm_runtime_mark_last_busy(pfdev->dev);
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pm_runtime_put_autosuspend(pfdev->dev);
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return 0;
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err_out4:
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panfrost_mmu_fini(pfdev);
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err_out3:
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panfrost_gpu_fini(pfdev);
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err_out2:
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panfrost_reset_fini(pfdev);
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err_out1:
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panfrost_regulator_fini(pfdev);
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err_out0:
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panfrost_clk_fini(pfdev);
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return err;
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}
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void panfrost_device_fini(struct panfrost_device *pfdev)
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{
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2019-05-13 15:17:34 +07:00
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panfrost_job_fini(pfdev);
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panfrost_mmu_fini(pfdev);
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panfrost_gpu_fini(pfdev);
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panfrost_reset_fini(pfdev);
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2018-09-11 02:27:58 +07:00
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panfrost_regulator_fini(pfdev);
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panfrost_clk_fini(pfdev);
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}
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const char *panfrost_exception_name(struct panfrost_device *pfdev, u32 exception_code)
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{
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switch (exception_code) {
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/* Non-Fault Status code */
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case 0x00: return "NOT_STARTED/IDLE/OK";
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case 0x01: return "DONE";
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case 0x02: return "INTERRUPTED";
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case 0x03: return "STOPPED";
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case 0x04: return "TERMINATED";
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case 0x08: return "ACTIVE";
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/* Job exceptions */
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case 0x40: return "JOB_CONFIG_FAULT";
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case 0x41: return "JOB_POWER_FAULT";
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case 0x42: return "JOB_READ_FAULT";
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case 0x43: return "JOB_WRITE_FAULT";
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case 0x44: return "JOB_AFFINITY_FAULT";
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case 0x48: return "JOB_BUS_FAULT";
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case 0x50: return "INSTR_INVALID_PC";
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case 0x51: return "INSTR_INVALID_ENC";
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case 0x52: return "INSTR_TYPE_MISMATCH";
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case 0x53: return "INSTR_OPERAND_FAULT";
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case 0x54: return "INSTR_TLS_FAULT";
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case 0x55: return "INSTR_BARRIER_FAULT";
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case 0x56: return "INSTR_ALIGN_FAULT";
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case 0x58: return "DATA_INVALID_FAULT";
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case 0x59: return "TILE_RANGE_FAULT";
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case 0x5A: return "ADDR_RANGE_FAULT";
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case 0x60: return "OUT_OF_MEMORY";
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/* GPU exceptions */
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case 0x80: return "DELAYED_BUS_FAULT";
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case 0x88: return "SHAREABILITY_FAULT";
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/* MMU exceptions */
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case 0xC1: return "TRANSLATION_FAULT_LEVEL1";
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case 0xC2: return "TRANSLATION_FAULT_LEVEL2";
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case 0xC3: return "TRANSLATION_FAULT_LEVEL3";
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case 0xC4: return "TRANSLATION_FAULT_LEVEL4";
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case 0xC8: return "PERMISSION_FAULT";
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case 0xC9 ... 0xCF: return "PERMISSION_FAULT";
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case 0xD1: return "TRANSTAB_BUS_FAULT_LEVEL1";
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case 0xD2: return "TRANSTAB_BUS_FAULT_LEVEL2";
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case 0xD3: return "TRANSTAB_BUS_FAULT_LEVEL3";
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case 0xD4: return "TRANSTAB_BUS_FAULT_LEVEL4";
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case 0xD8: return "ACCESS_FLAG";
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case 0xD9 ... 0xDF: return "ACCESS_FLAG";
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case 0xE0 ... 0xE7: return "ADDRESS_SIZE_FAULT";
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case 0xE8 ... 0xEF: return "MEMORY_ATTRIBUTES_FAULT";
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}
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return "UNKNOWN";
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}
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#ifdef CONFIG_PM
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int panfrost_device_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct panfrost_device *pfdev = platform_get_drvdata(pdev);
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panfrost_gpu_soft_reset(pfdev);
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/* TODO: Re-enable all other address spaces */
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panfrost_gpu_power_on(pfdev);
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panfrost_mmu_enable(pfdev, 0);
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panfrost_job_enable_interrupts(pfdev);
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panfrost_devfreq_resume(pfdev);
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return 0;
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}
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int panfrost_device_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct panfrost_device *pfdev = platform_get_drvdata(pdev);
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if (!panfrost_job_is_idle(pfdev))
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return -EBUSY;
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panfrost_devfreq_suspend(pfdev);
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panfrost_gpu_power_off(pfdev);
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return 0;
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}
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#endif
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