2008-03-18 15:22:06 +07:00
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/*
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* linux/arch/arm/mach-omap2/clock.h
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*
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2009-12-09 06:21:29 +07:00
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2009 Nokia Corporation
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2008-03-18 15:22:06 +07:00
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*
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2008-03-18 16:56:39 +07:00
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* Contacts:
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* Richard Woodruff <r-woodruff2@ti.com>
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2008-03-18 15:22:06 +07:00
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
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2009-10-20 23:40:47 +07:00
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#include <plat/clock.h>
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2008-03-18 15:22:06 +07:00
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 16:24:46 +07:00
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/* The maximum error between a target DPLL rate and the rounded rate in Hz */
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#define DEFAULT_DPLL_RATE_TOLERANCE 50000
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[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 20:29:22 +07:00
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/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
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#define CORE_CLK_SRC_32K 0x0
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#define CORE_CLK_SRC_DPLL 0x1
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#define CORE_CLK_SRC_DPLL_X2 0x2
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/* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP2XXX_EN_DPLL_LPBYPASS 0x1
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#define OMAP2XXX_EN_DPLL_FRBYPASS 0x2
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#define OMAP2XXX_EN_DPLL_LOCKED 0x3
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/* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP3XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP3XXX_EN_DPLL_LOCKED 0x7
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2009-12-09 08:47:16 +07:00
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/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
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#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
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#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
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#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
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#define OMAP4XXX_EN_DPLL_LOCKED 0x7
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2009-12-09 08:47:16 +07:00
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/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
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#define DPLL_LOW_POWER_STOP 0x1
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#define DPLL_LOW_POWER_BYPASS 0x5
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#define DPLL_LOCKED 0x7
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2008-10-06 19:49:36 +07:00
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int omap2_clk_init(void);
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2008-03-18 15:22:06 +07:00
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int omap2_clk_enable(struct clk *clk);
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void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
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int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
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2009-01-28 09:12:50 +07:00
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int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
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ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 16:24:46 +07:00
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long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
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2009-12-09 08:47:16 +07:00
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unsigned long omap3_dpll_recalc(struct clk *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk *clk);
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void omap3_dpll_allow_idle(struct clk *clk);
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void omap3_dpll_deny_idle(struct clk *clk);
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u32 omap3_dpll_autoidle_read(struct clk *clk);
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int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
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int omap3_noncore_dpll_enable(struct clk *clk);
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void omap3_noncore_dpll_disable(struct clk *clk);
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2008-03-18 15:22:06 +07:00
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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void omap2_clk_disable_unused(struct clk *clk);
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#else
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#define omap2_clk_disable_unused NULL
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#endif
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2009-02-12 17:12:59 +07:00
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unsigned long omap2_clksel_recalc(struct clk *clk);
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2008-08-19 15:08:45 +07:00
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void omap2_init_clk_clkdm(struct clk *clk);
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2008-03-18 15:22:06 +07:00
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void omap2_init_clksel_parent(struct clk *clk);
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u32 omap2_clksel_get_divisor(struct clk *clk);
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u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
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u32 *new_div);
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u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
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u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
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long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
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int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
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u32 omap2_get_dpll_rate(struct clk *clk);
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2009-12-09 08:47:17 +07:00
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void omap2_init_dpll_parent(struct clk *clk);
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2008-03-18 15:22:06 +07:00
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int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
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2008-07-03 16:24:44 +07:00
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void omap2_clk_prepare_for_reboot(void);
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2009-07-25 08:44:03 +07:00
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int omap2_dflt_clk_enable(struct clk *clk);
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void omap2_dflt_clk_disable(struct clk *clk);
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void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
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u8 *idlest_bit);
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2008-03-18 15:22:06 +07:00
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2009-12-09 06:21:29 +07:00
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extern u8 cpu_mask;
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2008-11-05 00:59:52 +07:00
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extern const struct clkops clkops_omap2_dflt_wait;
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2008-11-05 01:59:32 +07:00
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extern const struct clkops clkops_omap2_dflt;
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2008-11-05 00:59:52 +07:00
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2009-12-09 06:18:47 +07:00
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extern struct clk_functions omap2_clk_functions;
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2009-12-09 06:21:29 +07:00
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extern struct clk *vclk, *sclk;
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2009-12-09 06:18:47 +07:00
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2009-12-09 06:21:29 +07:00
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extern const struct clksel_rate gpt_32k_rates[];
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extern const struct clksel_rate gpt_sys_rates[];
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extern const struct clksel_rate gfx_l3_rates[];
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2008-03-18 15:22:06 +07:00
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#endif
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