2019-06-03 12:44:50 +07:00
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// SPDX-License-Identifier: GPL-2.0-only
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irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
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dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
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/*
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* Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
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* Author: Jun Ma <majun258@huawei.com>
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* Author: Yun Wu <wuyun.wu@huawei.com>
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*/
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irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
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#include <linux/acpi.h>
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2015-12-17 18:56:36 +07:00
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
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#include <linux/module.h>
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2015-12-17 18:56:36 +07:00
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#include <linux/msi.h>
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irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2015-12-17 18:56:36 +07:00
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/* Interrupt numbers per mbigen node supported */
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#define IRQS_PER_MBIGEN_NODE 128
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/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
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#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
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/* The maximum IRQ pin number of mbigen chip(start from 0) */
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#define MAXIMUM_IRQ_PIN_NUM 1407
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/**
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* In mbigen vector register
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* bit[21:12]: event id value
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* bit[11:0]: device id
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*/
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#define IRQ_EVENT_ID_SHIFT 12
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#define IRQ_EVENT_ID_MASK 0x3ff
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/* register range of each mbigen node */
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#define MBIGEN_NODE_OFFSET 0x1000
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/* offset of vector register in mbigen node */
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#define REG_MBIGEN_VEC_OFFSET 0x200
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2015-12-17 18:56:37 +07:00
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/**
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* offset of clear register in mbigen node
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* This register is used to clear the status
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* of interrupt
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*/
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#define REG_MBIGEN_CLEAR_OFFSET 0xa000
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/**
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* offset of interrupt type register
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* This register is used to configure interrupt
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* trigger type
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*/
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#define REG_MBIGEN_TYPE_OFFSET 0x0
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irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
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/**
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* struct mbigen_device - holds the information of mbigen device.
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*
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* @pdev: pointer to the platform device structure of mbigen chip.
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* @base: mapped address of this mbigen chip.
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*/
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struct mbigen_device {
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struct platform_device *pdev;
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void __iomem *base;
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};
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2015-12-17 18:56:36 +07:00
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static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
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{
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unsigned int nid, pin;
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hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
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nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
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pin = hwirq % IRQS_PER_MBIGEN_NODE;
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return pin * 4 + nid * MBIGEN_NODE_OFFSET
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+ REG_MBIGEN_VEC_OFFSET;
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}
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2015-12-17 18:56:37 +07:00
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static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
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u32 *mask, u32 *addr)
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{
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unsigned int nid, irq_ofst, ofst;
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hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
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nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
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irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
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*mask = 1 << (irq_ofst % 32);
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ofst = irq_ofst / 32 * 4;
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*addr = ofst + nid * MBIGEN_NODE_OFFSET
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+ REG_MBIGEN_TYPE_OFFSET;
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}
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static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
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u32 *mask, u32 *addr)
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{
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2017-05-12 10:55:28 +07:00
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unsigned int ofst = (hwirq / 32) * 4;
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2015-12-17 18:56:37 +07:00
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*mask = 1 << (hwirq % 32);
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*addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
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}
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static void mbigen_eoi_irq(struct irq_data *data)
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{
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void __iomem *base = data->chip_data;
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u32 mask, addr;
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get_mbigen_clear_reg(data->hwirq, &mask, &addr);
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writel_relaxed(mask, base + addr);
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irq_chip_eoi_parent(data);
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}
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static int mbigen_set_type(struct irq_data *data, unsigned int type)
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{
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void __iomem *base = data->chip_data;
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u32 mask, addr, val;
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if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
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return -EINVAL;
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get_mbigen_type_reg(data->hwirq, &mask, &addr);
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val = readl_relaxed(base + addr);
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if (type == IRQ_TYPE_LEVEL_HIGH)
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val |= mask;
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else
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val &= ~mask;
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writel_relaxed(val, base + addr);
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return 0;
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}
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2015-12-17 18:56:36 +07:00
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static struct irq_chip mbigen_irq_chip = {
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.name = "mbigen-v2",
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2015-12-17 18:56:37 +07:00
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_eoi = mbigen_eoi_irq,
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.irq_set_type = mbigen_set_type,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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2015-12-17 18:56:36 +07:00
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};
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static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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struct irq_data *d = irq_get_irq_data(desc->irq);
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void __iomem *base = d->chip_data;
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u32 val;
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2019-03-21 01:54:21 +07:00
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if (!msg->address_lo && !msg->address_hi)
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return;
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2015-12-17 18:56:36 +07:00
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base += get_mbigen_vec_reg(d->hwirq);
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val = readl_relaxed(base);
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val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
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val |= (msg->data << IRQ_EVENT_ID_SHIFT);
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/* The address of doorbell is encoded in mbigen register by default
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* So,we don't need to program the doorbell address at here
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*/
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writel_relaxed(val, base);
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}
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static int mbigen_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
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if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
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2015-12-17 18:56:36 +07:00
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if (fwspec->param_count != 2)
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return -EINVAL;
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if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
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(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
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return -EINVAL;
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else
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*hwirq = fwspec->param[0];
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/* If there is no valid irq type, just use the default type */
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if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
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(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
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*type = fwspec->param[1];
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else
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return -EINVAL;
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return 0;
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}
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return -EINVAL;
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}
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static int mbigen_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *args)
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{
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struct irq_fwspec *fwspec = args;
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irq_hw_number_t hwirq;
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unsigned int type;
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struct mbigen_device *mgn_chip;
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int i, err;
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|
|
err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
err = platform_msi_domain_alloc(domain, virq, nr_irqs);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
mgn_chip = platform_msi_get_host_data(domain);
|
|
|
|
|
|
|
|
for (i = 0; i < nr_irqs; i++)
|
|
|
|
irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
|
|
|
|
&mbigen_irq_chip, mgn_chip->base);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-06-02 15:20:55 +07:00
|
|
|
static const struct irq_domain_ops mbigen_domain_ops = {
|
2015-12-17 18:56:36 +07:00
|
|
|
.translate = mbigen_domain_translate,
|
|
|
|
.alloc = mbigen_irq_domain_alloc,
|
|
|
|
.free = irq_domain_free_irqs_common,
|
|
|
|
};
|
|
|
|
|
2017-03-07 19:40:09 +07:00
|
|
|
static int mbigen_of_create_domain(struct platform_device *pdev,
|
|
|
|
struct mbigen_device *mgn_chip)
|
irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
|
|
|
{
|
2017-03-07 19:40:09 +07:00
|
|
|
struct device *parent;
|
2016-03-17 15:34:01 +07:00
|
|
|
struct platform_device *child;
|
2015-12-17 18:56:36 +07:00
|
|
|
struct irq_domain *domain;
|
2016-03-17 15:34:01 +07:00
|
|
|
struct device_node *np;
|
2015-12-17 18:56:36 +07:00
|
|
|
u32 num_pins;
|
irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
|
|
|
|
2016-03-17 15:34:01 +07:00
|
|
|
for_each_child_of_node(pdev->dev.of_node, np) {
|
|
|
|
if (!of_property_read_bool(np, "interrupt-controller"))
|
|
|
|
continue;
|
2015-12-17 18:56:36 +07:00
|
|
|
|
2016-03-17 15:34:01 +07:00
|
|
|
parent = platform_bus_type.dev_root;
|
|
|
|
child = of_platform_device_create(np, NULL, parent);
|
2019-07-23 17:39:10 +07:00
|
|
|
if (!child) {
|
|
|
|
of_node_put(np);
|
2016-04-04 18:17:36 +07:00
|
|
|
return -ENOMEM;
|
2019-07-23 17:39:10 +07:00
|
|
|
}
|
2015-12-17 18:56:36 +07:00
|
|
|
|
2016-03-17 15:34:01 +07:00
|
|
|
if (of_property_read_u32(child->dev.of_node, "num-pins",
|
|
|
|
&num_pins) < 0) {
|
|
|
|
dev_err(&pdev->dev, "No num-pins property\n");
|
2019-07-23 17:39:10 +07:00
|
|
|
of_node_put(np);
|
2016-03-17 15:34:01 +07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
domain = platform_msi_create_device_domain(&child->dev, num_pins,
|
|
|
|
mbigen_write_msg,
|
|
|
|
&mbigen_domain_ops,
|
|
|
|
mgn_chip);
|
2019-07-23 17:39:10 +07:00
|
|
|
if (!domain) {
|
|
|
|
of_node_put(np);
|
2016-03-17 15:34:01 +07:00
|
|
|
return -ENOMEM;
|
2019-07-23 17:39:10 +07:00
|
|
|
}
|
2016-03-17 15:34:01 +07:00
|
|
|
}
|
2015-12-17 18:56:36 +07:00
|
|
|
|
2017-03-07 19:40:09 +07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
static int mbigen_acpi_create_domain(struct platform_device *pdev,
|
|
|
|
struct mbigen_device *mgn_chip)
|
|
|
|
{
|
|
|
|
struct irq_domain *domain;
|
|
|
|
u32 num_pins = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* "num-pins" is the total number of interrupt pins implemented in
|
|
|
|
* this mbigen instance, and mbigen is an interrupt controller
|
|
|
|
* connected to ITS converting wired interrupts into MSI, so we
|
|
|
|
* use "num-pins" to alloc MSI vectors which are needed by client
|
|
|
|
* devices connected to it.
|
|
|
|
*
|
|
|
|
* Here is the DSDT device node used for mbigen in firmware:
|
|
|
|
* Device(MBI0) {
|
|
|
|
* Name(_HID, "HISI0152")
|
|
|
|
* Name(_UID, Zero)
|
|
|
|
* Name(_CRS, ResourceTemplate() {
|
|
|
|
* Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
|
|
|
|
* })
|
|
|
|
*
|
|
|
|
* Name(_DSD, Package () {
|
|
|
|
* ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
|
|
|
* Package () {
|
|
|
|
* Package () {"num-pins", 378}
|
|
|
|
* }
|
|
|
|
* })
|
|
|
|
* }
|
|
|
|
*/
|
|
|
|
ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
|
|
|
|
if (ret || num_pins == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
|
|
|
|
mbigen_write_msg,
|
|
|
|
&mbigen_domain_ops,
|
|
|
|
mgn_chip);
|
|
|
|
if (!domain)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
|
|
|
|
struct mbigen_device *mgn_chip)
|
|
|
|
{
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-03-07 19:40:09 +07:00
|
|
|
static int mbigen_device_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct mbigen_device *mgn_chip;
|
|
|
|
struct resource *res;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
|
|
|
|
if (!mgn_chip)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
mgn_chip->pdev = pdev;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
2017-05-12 10:55:27 +07:00
|
|
|
if (!res)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-05-12 10:55:26 +07:00
|
|
|
mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
|
|
|
|
resource_size(res));
|
|
|
|
if (!mgn_chip->base) {
|
|
|
|
dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2017-03-07 19:40:09 +07:00
|
|
|
|
irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
|
|
|
if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
|
|
|
|
err = mbigen_of_create_domain(pdev, mgn_chip);
|
|
|
|
else if (ACPI_COMPANION(&pdev->dev))
|
|
|
|
err = mbigen_acpi_create_domain(pdev, mgn_chip);
|
|
|
|
else
|
|
|
|
err = -EINVAL;
|
|
|
|
|
|
|
|
if (err) {
|
2019-06-18 16:15:05 +07:00
|
|
|
dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
|
2017-03-07 19:40:09 +07:00
|
|
|
return err;
|
irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
|
|
|
}
|
2017-03-07 19:40:09 +07:00
|
|
|
|
irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
|
|
|
platform_set_drvdata(pdev, mgn_chip);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id mbigen_of_match[] = {
|
|
|
|
{ .compatible = "hisilicon,mbigen-v2" },
|
|
|
|
{ /* END */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mbigen_of_match);
|
|
|
|
|
irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
|
|
|
static const struct acpi_device_id mbigen_acpi_match[] = {
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{ "HISI0152", 0 },
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{}
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};
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MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
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irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
|
|
|
static struct platform_driver mbigen_platform_driver = {
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.driver = {
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|
.name = "Hisilicon MBIGEN-V2",
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|
|
.of_match_table = mbigen_of_match,
|
irqchip/mbigen: Add ACPI support
With the preparation of platform msi support and interrupt producer
in commit d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ
domain mapping"), we can add mbigen ACPI support now.
Now that the major framework changes are ready, we just need to add
the ACPI probe code which creates the irqdomain for devices connecting
to it.
In order to create the irqdomain, we need to know the number of hw
irqs as input which is provided by mbigen. In DT case, we are using
"num-pins" property to describe it, and we will take advantage of
that too using _DSD in ACPI as there is no standard way of describe
it in ACPI way, also according to the _DSD rule described in
Documentation/acpi/DSD-properties-rules.txt, it doesn't break
the rules.
The DSDT is represented as below:
For mbigen,
Device(MBI0) {
Name(_HID, "HISI0152")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
})
Name(_DSD, Package () {
ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
Package () {"num-pins", 378}
}
})
}
For devices,
Device(SAS0) {
Name(_HID, "HISIxxxx")
Name(_UID, Zero)
Name(_CRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xb0030000, 0x10000)
Interrupt(ResourceConsumer,..., "\_SB.MBI0") {12, ...}
})
}
So for the devices connected to the mbigen, as we clearly say that
it refers to a specific interrupt controller (mbigen), we can get
the virq from mbigen's irqdomain once it's created successfully.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: MaJun <majun258@huawei.com>
Cc: Al Stone <ahs3@redhat.com>
Cc: Darren Hart <dvhart@infradead.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2017-03-28 19:21:05 +07:00
|
|
|
.acpi_match_table = ACPI_PTR(mbigen_acpi_match),
|
irqchip/mgigen: Add platform device driver for mbigen device
Mbigen means Message Based Interrupt Generator(MBIGEN).
Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.
As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.
Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.
Mbigen is designed to fix this problem.
Mbigen chip locates in ITS or outside of ITS.
Mbigen chip hardware structure shows as below:
mbigen chip
|---------------------|-------------------|
mgn_node0 mgn_node1 mgn_node2
| |-------| |-------|------|
dev1 dev1 dev2 dev1 dev3 dev4
Each mbigen chip contains several mbigen nodes.
External devices can connect to mbigen node through wire connecting way.
Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.
Also, several different devices can connect to a same mbigen node.
When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.
To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.
Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.
So from software view, the structure likes below
mbigen chip
|---------------------|-----------------|
mbigen device1 mbigen device2 mbigen device3
| | |
dev1 dev2 dev3
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ma Jun <majun258@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2015-12-17 18:56:35 +07:00
|
|
|
},
|
|
|
|
.probe = mbigen_device_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(mbigen_platform_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
|
|
|
|
MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
|
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|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
|