2011-06-29 07:22:05 +07:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* Copyright 2010-2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/hugetlb.h>
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#include <asm/tlbflush.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/mmu-hash64.h>
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#include <asm/hvcall.h>
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#include <asm/synch.h>
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#include <asm/ppc-opcode.h>
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2011-12-12 19:28:21 +07:00
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/*
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* Since this file is built in even if KVM is a module, we need
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* a local copy of this function for the case where kvm_main.c is
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* modular.
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*/
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static struct kvm_memory_slot *builtin_gfn_to_memslot(struct kvm *kvm,
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gfn_t gfn)
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{
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struct kvm_memslots *slots;
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struct kvm_memory_slot *memslot;
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slots = kvm_memslots(kvm);
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kvm_for_each_memslot(memslot, slots)
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if (gfn >= memslot->base_gfn &&
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gfn < memslot->base_gfn + memslot->npages)
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return memslot;
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return NULL;
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}
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2011-12-12 19:27:39 +07:00
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/* Translate address of a vmalloc'd thing to a linear map address */
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static void *real_vmalloc_addr(void *x)
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{
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unsigned long addr = (unsigned long) x;
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pte_t *p;
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p = find_linux_pte(swapper_pg_dir, addr);
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if (!p || !pte_present(*p))
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return NULL;
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/* assume we don't have huge pages in vmalloc space... */
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addr = (pte_pfn(*p) << PAGE_SHIFT) | (addr & ~PAGE_MASK);
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return __va(addr);
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}
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2011-06-29 07:22:05 +07:00
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long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
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long pte_index, unsigned long pteh, unsigned long ptel)
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{
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unsigned long porder;
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struct kvm *kvm = vcpu->kvm;
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2011-12-12 19:28:21 +07:00
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unsigned long i, gfn, lpn, pa;
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2011-06-29 07:22:05 +07:00
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unsigned long *hpte;
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2011-12-12 19:27:39 +07:00
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struct revmap_entry *rev;
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unsigned long g_ptel = ptel;
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2011-12-12 19:28:21 +07:00
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struct kvm_memory_slot *memslot;
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unsigned long *physp;
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2011-06-29 07:22:05 +07:00
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/* only handle 4k, 64k and 16M pages for now */
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porder = 12;
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if (pteh & HPTE_V_LARGE) {
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KVM: PPC: book3s_hv: Add support for PPC970-family processors
This adds support for running KVM guests in supervisor mode on those
PPC970 processors that have a usable hypervisor mode. Unfortunately,
Apple G5 machines have supervisor mode disabled (MSR[HV] is forced to
1), but the YDL PowerStation does have a usable hypervisor mode.
There are several differences between the PPC970 and POWER7 in how
guests are managed. These differences are accommodated using the
CPU_FTR_ARCH_201 (PPC970) and CPU_FTR_ARCH_206 (POWER7) CPU feature
bits. Notably, on PPC970:
* The LPCR, LPID or RMOR registers don't exist, and the functions of
those registers are provided by bits in HID4 and one bit in HID0.
* External interrupts can be directed to the hypervisor, but unlike
POWER7 they are masked by MSR[EE] in non-hypervisor modes and use
SRR0/1 not HSRR0/1.
* There is no virtual RMA (VRMA) mode; the guest must use an RMO
(real mode offset) area.
* The TLB entries are not tagged with the LPID, so it is necessary to
flush the whole TLB on partition switch. Furthermore, when switching
partitions we have to ensure that no other CPU is executing the tlbie
or tlbsync instructions in either the old or the new partition,
otherwise undefined behaviour can occur.
* The PMU has 8 counters (PMC registers) rather than 6.
* The DSCR, PURR, SPURR, AMR, AMOR, UAMOR registers don't exist.
* The SLB has 64 entries rather than 32.
* There is no mediated external interrupt facility, so if we switch to
a guest that has a virtual external interrupt pending but the guest
has MSR[EE] = 0, we have to arrange to have an interrupt pending for
it so that we can get control back once it re-enables interrupts. We
do that by sending ourselves an IPI with smp_send_reschedule after
hard-disabling interrupts.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-29 07:40:08 +07:00
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if (cpu_has_feature(CPU_FTR_ARCH_206) &&
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(ptel & 0xf000) == 0x1000) {
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2011-06-29 07:22:05 +07:00
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/* 64k page */
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porder = 16;
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} else if ((ptel & 0xff000) == 0) {
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/* 16M page */
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porder = 24;
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/* lowest AVA bit must be 0 for 16M pages */
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if (pteh & 0x80)
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return H_PARAMETER;
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} else
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return H_PARAMETER;
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}
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2011-12-12 19:28:21 +07:00
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if (porder > kvm->arch.ram_porder)
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2011-06-29 07:22:05 +07:00
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return H_PARAMETER;
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2011-12-12 19:28:21 +07:00
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gfn = ((ptel & HPTE_R_RPN) & ~((1ul << porder) - 1)) >> PAGE_SHIFT;
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memslot = builtin_gfn_to_memslot(kvm, gfn);
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if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID)))
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return H_PARAMETER;
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physp = kvm->arch.slot_phys[memslot->id];
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if (!physp)
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return H_PARAMETER;
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lpn = (gfn - memslot->base_gfn) >> (kvm->arch.ram_porder - PAGE_SHIFT);
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physp = real_vmalloc_addr(physp + lpn);
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pa = *physp;
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2011-06-29 07:22:05 +07:00
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if (!pa)
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return H_PARAMETER;
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2011-12-12 19:28:21 +07:00
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pa &= PAGE_MASK;
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2011-06-29 07:22:05 +07:00
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/* Check WIMG */
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M &&
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(ptel & HPTE_R_WIMG) != (HPTE_R_W | HPTE_R_I | HPTE_R_M))
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return H_PARAMETER;
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pteh &= ~0x60UL;
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ptel &= ~(HPTE_R_PP0 - kvm->arch.ram_psize);
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ptel |= pa;
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2011-12-12 19:30:16 +07:00
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2011-12-12 19:27:39 +07:00
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if (pte_index >= HPT_NPTE)
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2011-06-29 07:22:05 +07:00
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return H_PARAMETER;
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if (likely((flags & H_EXACT) == 0)) {
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pte_index &= ~7UL;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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2011-12-12 19:30:16 +07:00
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for (i = 0; i < 8; ++i) {
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2011-06-29 07:22:05 +07:00
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if ((*hpte & HPTE_V_VALID) == 0 &&
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2011-12-12 19:30:16 +07:00
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try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID))
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2011-06-29 07:22:05 +07:00
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break;
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hpte += 2;
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}
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2011-12-12 19:30:16 +07:00
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if (i == 8) {
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/*
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* Since try_lock_hpte doesn't retry (not even stdcx.
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* failures), it could be that there is a free slot
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* but we transiently failed to lock it. Try again,
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* actually locking each slot and checking it.
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*/
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hpte -= 16;
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for (i = 0; i < 8; ++i) {
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if ((*hpte & HPTE_V_VALID) == 0)
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break;
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*hpte &= ~HPTE_V_HVLOCK;
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hpte += 2;
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}
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if (i == 8)
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return H_PTEG_FULL;
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}
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2011-12-12 19:27:39 +07:00
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pte_index += i;
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2011-06-29 07:22:05 +07:00
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} else {
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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2011-12-12 19:30:16 +07:00
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if (!try_lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
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/* Lock the slot and check again */
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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cpu_relax();
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if (*hpte & HPTE_V_VALID) {
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*hpte &= ~HPTE_V_HVLOCK;
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return H_PTEG_FULL;
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}
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}
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2011-06-29 07:22:05 +07:00
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}
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2011-12-12 19:27:39 +07:00
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/* Save away the guest's idea of the second HPTE dword */
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rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
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if (rev)
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rev->guest_rpte = g_ptel;
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2011-06-29 07:22:05 +07:00
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hpte[1] = ptel;
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eieio();
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hpte[0] = pteh;
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asm volatile("ptesync" : : : "memory");
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2011-12-12 19:27:39 +07:00
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vcpu->arch.gpr[4] = pte_index;
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2011-06-29 07:22:05 +07:00
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return H_SUCCESS;
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}
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#define LOCK_TOKEN (*(u32 *)(&get_paca()->lock_token))
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static inline int try_lock_tlbie(unsigned int *lock)
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{
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unsigned int tmp, old;
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unsigned int token = LOCK_TOKEN;
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asm volatile("1:lwarx %1,0,%2\n"
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" cmpwi cr0,%1,0\n"
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" bne 2f\n"
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" stwcx. %3,0,%2\n"
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" bne- 1b\n"
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" isync\n"
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"2:"
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: "=&r" (tmp), "=&r" (old)
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: "r" (lock), "r" (token)
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: "cc", "memory");
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return old == 0;
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}
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long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
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unsigned long pte_index, unsigned long avpn,
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unsigned long va)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *hpte;
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unsigned long v, r, rb;
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2011-12-12 19:27:39 +07:00
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if (pte_index >= HPT_NPTE)
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2011-06-29 07:22:05 +07:00
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return H_PARAMETER;
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hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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2011-12-12 19:30:16 +07:00
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while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
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2011-06-29 07:22:05 +07:00
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cpu_relax();
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if ((hpte[0] & HPTE_V_VALID) == 0 ||
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((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn) ||
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((flags & H_ANDCOND) && (hpte[0] & avpn) != 0)) {
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hpte[0] &= ~HPTE_V_HVLOCK;
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return H_NOT_FOUND;
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}
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if (atomic_read(&kvm->online_vcpus) == 1)
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flags |= H_LOCAL;
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vcpu->arch.gpr[4] = v = hpte[0] & ~HPTE_V_HVLOCK;
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vcpu->arch.gpr[5] = r = hpte[1];
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rb = compute_tlbie_rb(v, r, pte_index);
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hpte[0] = 0;
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if (!(flags & H_LOCAL)) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
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: : "r" (rb), "r" (kvm->arch.lpid));
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asm volatile("ptesync" : : : "memory");
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kvm->arch.tlbie_lock = 0;
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} else {
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asm volatile("ptesync" : : : "memory");
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asm volatile("tlbiel %0" : : "r" (rb));
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asm volatile("ptesync" : : : "memory");
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}
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return H_SUCCESS;
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}
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long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
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{
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struct kvm *kvm = vcpu->kvm;
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unsigned long *args = &vcpu->arch.gpr[4];
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unsigned long *hp, tlbrb[4];
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long int i, found;
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long int n_inval = 0;
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unsigned long flags, req, pte_index;
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long int local = 0;
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long int ret = H_SUCCESS;
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if (atomic_read(&kvm->online_vcpus) == 1)
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local = 1;
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for (i = 0; i < 4; ++i) {
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pte_index = args[i * 2];
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flags = pte_index >> 56;
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pte_index &= ((1ul << 56) - 1);
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req = flags >> 6;
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flags &= 3;
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if (req == 3)
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break;
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if (req != 1 || flags == 3 ||
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2011-12-12 19:27:39 +07:00
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pte_index >= HPT_NPTE) {
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2011-06-29 07:22:05 +07:00
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/* parameter error */
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args[i * 2] = ((0xa0 | flags) << 56) + pte_index;
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ret = H_PARAMETER;
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break;
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}
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hp = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
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2011-12-12 19:30:16 +07:00
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while (!try_lock_hpte(hp, HPTE_V_HVLOCK))
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2011-06-29 07:22:05 +07:00
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cpu_relax();
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found = 0;
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if (hp[0] & HPTE_V_VALID) {
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switch (flags & 3) {
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case 0: /* absolute */
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found = 1;
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break;
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case 1: /* andcond */
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if (!(hp[0] & args[i * 2 + 1]))
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found = 1;
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break;
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case 2: /* AVPN */
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if ((hp[0] & ~0x7fUL) == args[i * 2 + 1])
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found = 1;
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break;
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}
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}
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if (!found) {
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hp[0] &= ~HPTE_V_HVLOCK;
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args[i * 2] = ((0x90 | flags) << 56) + pte_index;
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continue;
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}
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/* insert R and C bits from PTE */
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flags |= (hp[1] >> 5) & 0x0c;
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args[i * 2] = ((0x80 | flags) << 56) + pte_index;
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tlbrb[n_inval++] = compute_tlbie_rb(hp[0], hp[1], pte_index);
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hp[0] = 0;
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}
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if (n_inval == 0)
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return ret;
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if (!local) {
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while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
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cpu_relax();
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asm volatile("ptesync" : : : "memory");
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for (i = 0; i < n_inval; ++i)
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asm volatile(PPC_TLBIE(%1,%0)
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: : "r" (tlbrb[i]), "r" (kvm->arch.lpid));
|
|
|
|
asm volatile("eieio; tlbsync; ptesync" : : : "memory");
|
|
|
|
kvm->arch.tlbie_lock = 0;
|
|
|
|
} else {
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
for (i = 0; i < n_inval; ++i)
|
|
|
|
asm volatile("tlbiel %0" : : "r" (tlbrb[i]));
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
|
|
unsigned long pte_index, unsigned long avpn,
|
|
|
|
unsigned long va)
|
|
|
|
{
|
|
|
|
struct kvm *kvm = vcpu->kvm;
|
|
|
|
unsigned long *hpte;
|
2011-12-12 19:27:39 +07:00
|
|
|
struct revmap_entry *rev;
|
|
|
|
unsigned long v, r, rb, mask, bits;
|
2011-06-29 07:22:05 +07:00
|
|
|
|
2011-12-12 19:27:39 +07:00
|
|
|
if (pte_index >= HPT_NPTE)
|
2011-06-29 07:22:05 +07:00
|
|
|
return H_PARAMETER;
|
|
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
2011-12-12 19:30:16 +07:00
|
|
|
while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
|
2011-06-29 07:22:05 +07:00
|
|
|
cpu_relax();
|
|
|
|
if ((hpte[0] & HPTE_V_VALID) == 0 ||
|
|
|
|
((flags & H_AVPN) && (hpte[0] & ~0x7fUL) != avpn)) {
|
|
|
|
hpte[0] &= ~HPTE_V_HVLOCK;
|
|
|
|
return H_NOT_FOUND;
|
|
|
|
}
|
|
|
|
if (atomic_read(&kvm->online_vcpus) == 1)
|
|
|
|
flags |= H_LOCAL;
|
|
|
|
v = hpte[0];
|
2011-12-12 19:27:39 +07:00
|
|
|
bits = (flags << 55) & HPTE_R_PP0;
|
|
|
|
bits |= (flags << 48) & HPTE_R_KEY_HI;
|
|
|
|
bits |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO);
|
|
|
|
|
|
|
|
/* Update guest view of 2nd HPTE dword */
|
|
|
|
mask = HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N |
|
|
|
|
HPTE_R_KEY_HI | HPTE_R_KEY_LO;
|
|
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
|
|
|
if (rev) {
|
|
|
|
r = (rev->guest_rpte & ~mask) | bits;
|
|
|
|
rev->guest_rpte = r;
|
|
|
|
}
|
|
|
|
r = (hpte[1] & ~mask) | bits;
|
|
|
|
|
|
|
|
/* Update HPTE */
|
2011-06-29 07:22:05 +07:00
|
|
|
rb = compute_tlbie_rb(v, r, pte_index);
|
|
|
|
hpte[0] = v & ~HPTE_V_VALID;
|
|
|
|
if (!(flags & H_LOCAL)) {
|
|
|
|
while(!try_lock_tlbie(&kvm->arch.tlbie_lock))
|
|
|
|
cpu_relax();
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
asm volatile(PPC_TLBIE(%1,%0)"; eieio; tlbsync"
|
|
|
|
: : "r" (rb), "r" (kvm->arch.lpid));
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
kvm->arch.tlbie_lock = 0;
|
|
|
|
} else {
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
asm volatile("tlbiel %0" : : "r" (rb));
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
}
|
|
|
|
hpte[1] = r;
|
|
|
|
eieio();
|
|
|
|
hpte[0] = v & ~HPTE_V_HVLOCK;
|
|
|
|
asm volatile("ptesync" : : : "memory");
|
|
|
|
return H_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
|
|
|
|
unsigned long pte_index)
|
|
|
|
{
|
|
|
|
struct kvm *kvm = vcpu->kvm;
|
|
|
|
unsigned long *hpte, r;
|
|
|
|
int i, n = 1;
|
2011-12-12 19:27:39 +07:00
|
|
|
struct revmap_entry *rev = NULL;
|
2011-06-29 07:22:05 +07:00
|
|
|
|
2011-12-12 19:27:39 +07:00
|
|
|
if (pte_index >= HPT_NPTE)
|
2011-06-29 07:22:05 +07:00
|
|
|
return H_PARAMETER;
|
|
|
|
if (flags & H_READ_4) {
|
|
|
|
pte_index &= ~3;
|
|
|
|
n = 4;
|
|
|
|
}
|
2011-12-12 19:27:39 +07:00
|
|
|
if (flags & H_R_XLATE)
|
|
|
|
rev = real_vmalloc_addr(&kvm->arch.revmap[pte_index]);
|
2011-06-29 07:22:05 +07:00
|
|
|
for (i = 0; i < n; ++i, ++pte_index) {
|
|
|
|
hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
|
|
|
|
r = hpte[1];
|
2011-12-12 19:27:39 +07:00
|
|
|
if (hpte[0] & HPTE_V_VALID) {
|
|
|
|
if (rev)
|
|
|
|
r = rev[i].guest_rpte;
|
|
|
|
else
|
|
|
|
r = hpte[1] | HPTE_R_RPN;
|
|
|
|
}
|
2011-06-29 07:22:05 +07:00
|
|
|
vcpu->arch.gpr[4 + i * 2] = hpte[0];
|
|
|
|
vcpu->arch.gpr[5 + i * 2] = r;
|
|
|
|
}
|
|
|
|
return H_SUCCESS;
|
|
|
|
}
|