2006-07-03 14:24:42 +07:00
|
|
|
/*
|
|
|
|
|
* IRQ flags handling
|
|
|
|
|
*/
|
|
|
|
|
#ifndef _ASM_IRQFLAGS_H
|
|
|
|
|
#define _ASM_IRQFLAGS_H
|
|
|
|
|
|
2008-04-17 11:35:01 +07:00
|
|
|
#ifndef __ASSEMBLY__
|
2006-07-03 14:24:42 +07:00
|
|
|
/*
|
2010-10-07 20:08:55 +07:00
|
|
|
* Get definitions for arch_local_save_flags(x), etc.
|
2006-07-03 14:24:42 +07:00
|
|
|
*/
|
2008-08-01 12:20:30 +07:00
|
|
|
#include <asm/hw_irq.h>
|
2006-07-03 14:24:42 +07:00
|
|
|
|
2008-04-17 11:35:01 +07:00
|
|
|
#else
|
|
|
|
|
#ifdef CONFIG_TRACE_IRQFLAGS
|
2010-12-24 02:46:06 +07:00
|
|
|
#ifdef CONFIG_IRQSOFF_TRACER
|
|
|
|
|
/*
|
|
|
|
|
* Since the ftrace irqsoff latency trace checks CALLER_ADDR1,
|
|
|
|
|
* which is the stack frame here, we need to force a stack frame
|
|
|
|
|
* in case we came from user space.
|
|
|
|
|
*/
|
|
|
|
|
#define TRACE_WITH_FRAME_BUFFER(func) \
|
|
|
|
|
mflr r0; \
|
|
|
|
|
stdu r1, -32(r1); \
|
|
|
|
|
std r0, 16(r1); \
|
|
|
|
|
stdu r1, -32(r1); \
|
|
|
|
|
bl func; \
|
|
|
|
|
ld r1, 0(r1); \
|
|
|
|
|
ld r1, 0(r1);
|
|
|
|
|
#else
|
|
|
|
|
#define TRACE_WITH_FRAME_BUFFER(func) \
|
|
|
|
|
bl func;
|
|
|
|
|
#endif
|
|
|
|
|
|
2006-07-03 14:24:42 +07:00
|
|
|
/*
|
2008-04-17 11:35:01 +07:00
|
|
|
* Most of the CPU's IRQ-state tracing is done from assembly code; we
|
|
|
|
|
* have to call a C function so call a wrapper that saves all the
|
|
|
|
|
* C-clobbered registers.
|
2006-07-03 14:24:42 +07:00
|
|
|
*/
|
2010-12-24 02:46:06 +07:00
|
|
|
#define TRACE_ENABLE_INTS TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_on)
|
|
|
|
|
#define TRACE_DISABLE_INTS TRACE_WITH_FRAME_BUFFER(.trace_hardirqs_off)
|
|
|
|
|
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 14:27:59 +07:00
|
|
|
/*
|
|
|
|
|
* This is used by assembly code to soft-disable interrupts
|
|
|
|
|
*/
|
|
|
|
|
#define SOFT_DISABLE_INTS(__rA, __rB) \
|
|
|
|
|
lbz __rA,PACASOFTIRQEN(r13); \
|
|
|
|
|
lbz __rB,PACAIRQHAPPENED(r13); \
|
|
|
|
|
cmpwi cr0,__rA,0; \
|
|
|
|
|
li __rA,0; \
|
|
|
|
|
ori __rB,__rB,PACA_IRQ_HARD_DIS; \
|
|
|
|
|
stb __rB,PACAIRQHAPPENED(r13); \
|
|
|
|
|
beq 44f; \
|
|
|
|
|
stb __rA,PACASOFTIRQEN(r13); \
|
|
|
|
|
TRACE_DISABLE_INTS; \
|
|
|
|
|
44:
|
|
|
|
|
|
2006-07-03 14:24:42 +07:00
|
|
|
#else
|
2008-04-17 11:35:01 +07:00
|
|
|
#define TRACE_ENABLE_INTS
|
|
|
|
|
#define TRACE_DISABLE_INTS
|
powerpc: Rework lazy-interrupt handling
The current implementation of lazy interrupts handling has some
issues that this tries to address.
We don't do the various workarounds we need to do when re-enabling
interrupts in some cases such as when returning from an interrupt
and thus we may still lose or get delayed decrementer or doorbell
interrupts.
The current scheme also makes it much harder to handle the external
"edge" interrupts provided by some BookE processors when using the
EPR facility (External Proxy) and the Freescale Hypervisor.
Additionally, we tend to keep interrupts hard disabled in a number
of cases, such as decrementer interrupts, external interrupts, or
when a masked decrementer interrupt is pending. This is sub-optimal.
This is an attempt at fixing it all in one go by reworking the way
we do the lazy interrupt disabling from the ground up.
The base idea is to replace the "hard_enabled" field with a
"irq_happened" field in which we store a bit mask of what interrupt
occurred while soft-disabled.
When re-enabling, either via arch_local_irq_restore() or when returning
from an interrupt, we can now decide what to do by testing bits in that
field.
We then implement replaying of the missed interrupts either by
re-using the existing exception frame (in exception exit case) or via
the creation of a new one from an assembly trampoline (in the
arch_local_irq_enable case).
This removes the need to play with the decrementer to try to create
fake interrupts, among others.
In addition, this adds a few refinements:
- We no longer hard disable decrementer interrupts that occur
while soft-disabled. We now simply bump the decrementer back to max
(on BookS) or leave it stopped (on BookE) and continue with hard interrupts
enabled, which means that we'll potentially get better sample quality from
performance monitor interrupts.
- Timer, decrementer and doorbell interrupts now hard-enable
shortly after removing the source of the interrupt, which means
they no longer run entirely hard disabled. Again, this will improve
perf sample quality.
- On Book3E 64-bit, we now make the performance monitor interrupt
act as an NMI like Book3S (the necessary C code for that to work
appear to already be present in the FSL perf code, notably calling
nmi_enter instead of irq_enter). (This also fixes a bug where BookE
perfmon interrupts could clobber r14 ... oops)
- We could make "masked" decrementer interrupts act as NMIs when doing
timer-based perf sampling to improve the sample quality.
Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2:
- Add hard-enable to decrementer, timer and doorbells
- Fix CR clobber in masked irq handling on BookE
- Make embedded perf interrupt act as an NMI
- Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
to retrigger an interrupt without preventing hard-enable
v3:
- Fix or vs. ori bug on Book3E
- Fix enabling of interrupts for some exceptions on Book3E
v4:
- Fix resend of doorbells on return from interrupt on Book3E
v5:
- Rebased on top of my latest series, which involves some significant
rework of some aspects of the patch.
v6:
- 32-bit compile fix
- more compile fixes with various .config combos
- factor out the asm code to soft-disable interrupts
- remove the C wrapper around preempt_schedule_irq
v7:
- Fix a bug with hard irq state tracking on native power7
2012-03-06 14:27:59 +07:00
|
|
|
|
|
|
|
|
#define SOFT_DISABLE_INTS(__rA, __rB) \
|
|
|
|
|
lbz __rA,PACAIRQHAPPENED(r13); \
|
|
|
|
|
li __rB,0; \
|
|
|
|
|
ori __rA,__rA,PACA_IRQ_HARD_DIS; \
|
|
|
|
|
stb __rB,PACASOFTIRQEN(r13); \
|
|
|
|
|
stb __rA,PACAIRQHAPPENED(r13)
|
2008-04-17 11:35:01 +07:00
|
|
|
#endif
|
2006-07-03 14:24:42 +07:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif
|