2015-09-30 15:47:52 +07:00
|
|
|
* Renesas R-Car PWM Timer Controller
|
|
|
|
|
|
|
|
Required Properties:
|
2015-10-06 18:28:28 +07:00
|
|
|
- compatible: should be "renesas,pwm-rcar" and one of the following.
|
2017-12-20 18:15:43 +07:00
|
|
|
- "renesas,pwm-r8a7743": for RZ/G1M
|
2018-10-04 23:17:19 +07:00
|
|
|
- "renesas,pwm-r8a7744": for RZ/G1N
|
2017-12-20 18:15:43 +07:00
|
|
|
- "renesas,pwm-r8a7745": for RZ/G1E
|
2018-08-21 23:03:46 +07:00
|
|
|
- "renesas,pwm-r8a774a1": for RZ/G2M
|
2018-12-14 03:20:15 +07:00
|
|
|
- "renesas,pwm-r8a774c0": for RZ/G2E
|
2015-09-30 15:47:52 +07:00
|
|
|
- "renesas,pwm-r8a7778": for R-Car M1A
|
|
|
|
- "renesas,pwm-r8a7779": for R-Car H1
|
|
|
|
- "renesas,pwm-r8a7790": for R-Car H2
|
|
|
|
- "renesas,pwm-r8a7791": for R-Car M2-W
|
|
|
|
- "renesas,pwm-r8a7794": for R-Car E2
|
2016-03-31 18:39:15 +07:00
|
|
|
- "renesas,pwm-r8a7795": for R-Car H3
|
2017-04-27 21:37:43 +07:00
|
|
|
- "renesas,pwm-r8a7796": for R-Car M3-W
|
2018-03-09 18:53:17 +07:00
|
|
|
- "renesas,pwm-r8a77965": for R-Car M3-N
|
2018-10-02 02:57:39 +07:00
|
|
|
- "renesas,pwm-r8a77970": for R-Car V3M
|
|
|
|
- "renesas,pwm-r8a77980": for R-Car V3H
|
2018-07-30 18:49:51 +07:00
|
|
|
- "renesas,pwm-r8a77990": for R-Car E3
|
2017-10-04 17:10:38 +07:00
|
|
|
- "renesas,pwm-r8a77995": for R-Car D3
|
2015-09-30 15:47:52 +07:00
|
|
|
- reg: base address and length of the registers block for the PWM.
|
|
|
|
- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
|
|
|
|
the cells format.
|
|
|
|
- clocks: clock phandle and specifier pair.
|
|
|
|
- pinctrl-0: phandle, referring to a default pin configuration node.
|
|
|
|
- pinctrl-names: Set to "default".
|
|
|
|
|
2017-12-20 18:15:43 +07:00
|
|
|
Example: R8A7743 (RZ/G1M) PWM Timer node
|
2015-09-30 15:47:52 +07:00
|
|
|
|
|
|
|
pwm0: pwm@e6e30000 {
|
2017-12-20 18:15:43 +07:00
|
|
|
compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar";
|
2015-09-30 15:47:52 +07:00
|
|
|
reg = <0 0xe6e30000 0 0x8>;
|
2017-12-20 18:15:43 +07:00
|
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
|
|
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
|
|
|
|
resets = <&cpg 523>;
|
2015-09-30 15:47:52 +07:00
|
|
|
#pwm-cells = <2>;
|
|
|
|
pinctrl-0 = <&pwm0_pins>;
|
|
|
|
pinctrl-names = "default";
|
|
|
|
};
|