2005-04-17 05:20:36 +07:00
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/*
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* ahci.c - AHCI SATA support
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*
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2005-08-29 07:18:39 +07:00
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* Maintained by: Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004-2005 Red Hat, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* AHCI hardware documentation:
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2005-04-17 05:20:36 +07:00
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* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
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2005-08-29 07:18:39 +07:00
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* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
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2005-04-17 05:20:36 +07:00
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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2005-04-08 14:53:06 +07:00
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#include <linux/dma-mapping.h>
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2005-10-31 02:39:11 +07:00
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#include <linux/device.h>
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2007-10-25 12:59:16 +07:00
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#include <linux/dmi.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 15:04:11 +07:00
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#include <linux/gfp.h>
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2005-04-17 05:20:36 +07:00
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#include <scsi/scsi_host.h>
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2005-11-07 12:59:37 +07:00
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#include <scsi/scsi_cmnd.h>
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2005-04-17 05:20:36 +07:00
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#include <linux/libata.h>
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2010-03-28 11:22:14 +07:00
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#include "ahci.h"
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2005-04-17 05:20:36 +07:00
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#define DRV_NAME "ahci"
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2007-09-23 11:19:54 +07:00
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#define DRV_VERSION "3.0"
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2005-04-17 05:20:36 +07:00
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enum {
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2012-01-06 19:33:39 +07:00
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AHCI_PCI_BAR_STA2X11 = 0,
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2013-01-05 05:39:09 +07:00
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AHCI_PCI_BAR_ENMOTUS = 2,
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2012-01-06 19:33:39 +07:00
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AHCI_PCI_BAR_STANDARD = 5,
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2010-03-29 08:32:39 +07:00
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};
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enum board_ids {
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/* board IDs by feature in alphabetical order */
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board_ahci,
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board_ahci_ign_iferr,
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board_ahci_nosntf,
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2010-07-24 21:53:48 +07:00
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board_ahci_yes_fbs,
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2005-04-17 05:20:36 +07:00
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2010-03-29 08:32:39 +07:00
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/* board IDs for specific chipsets in alphabetical order */
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board_ahci_mcp65,
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2010-03-30 08:28:32 +07:00
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board_ahci_mcp77,
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board_ahci_mcp89,
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2010-03-29 08:32:39 +07:00
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board_ahci_mv,
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board_ahci_sb600,
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board_ahci_sb700, /* for SB700 and SB800 */
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board_ahci_vt8251,
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/* aliases */
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board_ahci_mcp_linux = board_ahci_mcp65,
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board_ahci_mcp67 = board_ahci_mcp65,
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board_ahci_mcp73 = board_ahci_mcp65,
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2010-03-30 08:28:32 +07:00
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board_ahci_mcp79 = board_ahci_mcp77,
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2005-04-17 05:20:36 +07:00
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};
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2007-10-19 17:42:56 +07:00
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static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:50 +07:00
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static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline);
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2007-03-02 15:31:26 +07:00
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#ifdef CONFIG_PM
|
2006-07-26 13:59:26 +07:00
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static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
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static int ahci_pci_device_resume(struct pci_dev *pdev);
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2007-03-02 15:31:26 +07:00
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#endif
|
2006-11-01 16:00:24 +07:00
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2010-09-21 14:25:48 +07:00
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static struct scsi_host_template ahci_sht = {
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AHCI_SHT("ahci"),
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};
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libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
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|
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static struct ata_port_operations ahci_vt8251_ops = {
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.inherits = &ahci_ops,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:50 +07:00
|
|
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.hardreset = ahci_vt8251_hardreset,
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
|
|
|
};
|
2007-10-25 12:59:16 +07:00
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:49 +07:00
|
|
|
static struct ata_port_operations ahci_p5wdh_ops = {
|
|
|
|
|
.inherits = &ahci_ops,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 10:22:50 +07:00
|
|
|
.hardreset = ahci_p5wdh_hardreset,
|
2007-10-25 12:59:16 +07:00
|
|
|
};
|
|
|
|
|
|
2005-11-28 16:06:23 +07:00
|
|
|
static const struct ata_port_info ahci_port_info[] = {
|
2010-03-29 08:32:39 +07:00
|
|
|
/* by features */
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci] = {
|
2007-04-23 00:41:05 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-07-08 12:13:16 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2005-04-17 05:20:36 +07:00
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_ign_iferr] = {
|
2010-03-29 08:32:39 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
|
2007-09-23 11:19:55 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-07-08 12:13:16 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2010-03-29 08:32:39 +07:00
|
|
|
.port_ops = &ahci_ops,
|
2006-04-17 19:17:59 +07:00
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_nosntf] = {
|
2010-03-29 08:32:39 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
|
2007-09-23 11:19:55 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-07-08 12:13:16 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2006-11-29 09:33:14 +07:00
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_yes_fbs] = {
|
2010-07-24 21:53:48 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
|
|
|
|
|
.flags = AHCI_FLAG_COMMON,
|
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2010-03-29 08:32:39 +07:00
|
|
|
/* by chipsets */
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_mcp65] = {
|
2010-03-30 08:28:32 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
|
|
|
|
|
AHCI_HFLAG_YES_NCQ),
|
2011-03-16 17:14:55 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
|
2010-03-30 08:28:32 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_mcp77] = {
|
2010-03-30 08:28:32 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
|
|
|
|
|
.flags = AHCI_FLAG_COMMON,
|
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_mcp89] = {
|
2010-03-30 08:28:32 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
|
2007-09-23 11:19:55 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-07-08 12:13:16 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2010-03-29 08:32:39 +07:00
|
|
|
.port_ops = &ahci_ops,
|
2007-03-27 17:33:05 +07:00
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_mv] = {
|
2007-09-23 11:19:55 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
|
2008-08-29 21:03:59 +07:00
|
|
|
AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
|
2011-02-05 02:05:48 +07:00
|
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2007-07-08 13:29:42 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
|
.port_ops = &ahci_ops,
|
|
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_sb600] = {
|
2010-03-29 08:32:39 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
|
|
|
|
|
AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
|
|
|
|
|
AHCI_HFLAG_32BIT_ONLY),
|
2008-02-22 20:00:31 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
2009-03-15 03:38:24 +07:00
|
|
|
.pio_mask = ATA_PIO4,
|
2008-02-22 20:00:31 +07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2011-06-21 16:17:38 +07:00
|
|
|
.port_ops = &ahci_pmp_retry_srst_ops,
|
2008-02-22 20:00:31 +07:00
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_sb700] = { /* for SB700 and SB800 */
|
2010-03-29 08:32:39 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
|
2009-04-09 04:25:31 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
2011-06-21 16:17:38 +07:00
|
|
|
.port_ops = &ahci_pmp_retry_srst_ops,
|
2009-04-09 04:25:31 +07:00
|
|
|
},
|
2012-06-05 03:03:37 +07:00
|
|
|
[board_ahci_vt8251] = {
|
2010-03-29 08:32:39 +07:00
|
|
|
AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
|
2009-11-16 08:56:05 +07:00
|
|
|
.flags = AHCI_FLAG_COMMON,
|
|
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
|
.udma_mask = ATA_UDMA6,
|
2010-03-29 08:32:39 +07:00
|
|
|
.port_ops = &ahci_vt8251_ops,
|
2009-11-16 08:56:05 +07:00
|
|
|
},
|
2005-04-17 05:20:36 +07:00
|
|
|
};
|
|
|
|
|
|
2005-11-10 23:04:11 +07:00
|
|
|
static const struct pci_device_id ahci_pci_tbl[] = {
|
2006-06-23 10:05:36 +07:00
|
|
|
/* Intel */
|
2006-09-28 09:20:11 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
|
2007-01-23 13:13:39 +07:00
|
|
|
{ PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
|
2006-09-28 09:20:11 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
|
2007-09-03 10:44:57 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
|
2009-11-16 08:56:05 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
|
2007-09-03 10:44:57 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
|
2007-09-21 04:35:00 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
|
2008-01-29 08:34:14 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
|
2009-06-26 22:44:11 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
|
2008-01-29 08:34:14 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
|
2009-07-23 03:15:56 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
|
2008-08-12 07:03:09 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
|
2008-08-28 06:47:22 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
|
2009-07-23 03:15:56 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
|
2008-08-12 07:03:09 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
|
2008-08-28 06:47:22 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
|
2009-07-23 03:15:56 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
|
2010-01-13 08:00:18 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
|
2010-09-09 23:44:56 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
|
2011-03-12 02:57:42 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
|
2011-01-11 03:57:17 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
|
2011-04-20 22:45:20 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
|
2011-07-15 06:50:49 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
|
2012-01-24 07:27:30 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
|
2012-08-09 23:02:31 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
|
2013-01-26 03:01:05 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
|
2013-02-22 02:08:51 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
|
2013-02-09 08:34:47 +07:00
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
|
|
|
|
|
{ PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
|
2006-06-23 10:05:36 +07:00
|
|
|
|
2007-02-26 18:24:03 +07:00
|
|
|
/* JMicron 360/1/3/5/6, match class to avoid IDE function */
|
|
|
|
|
{ PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
|
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
|
2012-09-10 07:09:04 +07:00
|
|
|
/* JMicron 362B and 362C have an AHCI function with IDE class code */
|
|
|
|
|
{ PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
|
|
|
|
|
{ PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
|
2006-06-23 10:05:36 +07:00
|
|
|
|
|
|
|
|
/* ATI */
|
2007-04-11 17:23:14 +07:00
|
|
|
{ PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
|
2008-02-22 20:00:31 +07:00
|
|
|
{ PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
|
|
|
|
|
{ PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
|
|
|
|
|
{ PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
|
|
|
|
|
{ PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
|
|
|
|
|
{ PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
|
|
|
|
|
{ PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
|
2006-06-23 10:05:36 +07:00
|
|
|
|
2009-07-29 10:34:49 +07:00
|
|
|
/* AMD */
|
2009-10-13 10:14:00 +07:00
|
|
|
{ PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
|
2009-07-29 10:34:49 +07:00
|
|
|
/* AMD is using RAID class only for ahci controllers */
|
|
|
|
|
{ PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
|
PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
|
|
|
|
|
|
2006-06-23 10:05:36 +07:00
|
|
|
/* VIA */
|
2006-09-28 09:20:11 +07:00
|
|
|
{ PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
|
2007-04-11 15:27:14 +07:00
|
|
|
{ PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
|
2006-06-23 10:05:36 +07:00
|
|
|
|
|
|
|
|
/* NVIDIA */
|
2008-06-09 22:13:04 +07:00
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
|
2010-03-29 08:32:39 +07:00
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
|
|
|
|
|
{ PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
|
2006-06-23 10:05:36 +07:00
|
|
|
|
2006-07-29 15:10:14 +07:00
|
|
|
/* SiS */
|
2008-08-01 10:51:43 +07:00
|
|
|
{ PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
|
|
|
|
|
{ PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
|
|
|
|
|
{ PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
|
2006-07-29 15:10:14 +07:00
|
|
|
|
2012-01-06 19:33:39 +07:00
|
|
|
/* ST Microelectronics */
|
|
|
|
|
{ PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
|
|
|
|
|
|
2007-07-08 13:29:42 +07:00
|
|
|
/* Marvell */
|
|
|
|
|
{ PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
|
2008-03-14 05:22:24 +07:00
|
|
|
{ PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
|
2010-07-24 21:53:48 +07:00
|
|
|
{ PCI_DEVICE(0x1b4b, 0x9123),
|
2011-01-19 08:03:26 +07:00
|
|
|
.class = PCI_CLASS_STORAGE_SATA_AHCI,
|
|
|
|
|
.class_mask = 0xffffff,
|
2010-07-24 21:53:48 +07:00
|
|
|
.driver_data = board_ahci_yes_fbs }, /* 88se9128 */
|
2011-02-08 19:54:32 +07:00
|
|
|
{ PCI_DEVICE(0x1b4b, 0x9125),
|
|
|
|
|
.driver_data = board_ahci_yes_fbs }, /* 88se9125 */
|
2012-04-27 13:42:30 +07:00
|
|
|
{ PCI_DEVICE(0x1b4b, 0x917a),
|
|
|
|
|
.driver_data = board_ahci_yes_fbs }, /* 88se9172 */
|
2012-09-04 22:07:18 +07:00
|
|
|
{ PCI_DEVICE(0x1b4b, 0x9192),
|
|
|
|
|
.driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
|
2010-11-29 21:57:14 +07:00
|
|
|
{ PCI_DEVICE(0x1b4b, 0x91a3),
|
|
|
|
|
.driver_data = board_ahci_yes_fbs },
|
2007-07-08 13:29:42 +07:00
|
|
|
|
2008-10-23 10:08:16 +07:00
|
|
|
/* Promise */
|
|
|
|
|
{ PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
|
|
|
|
|
|
2011-11-09 13:47:36 +07:00
|
|
|
/* Asmedia */
|
2012-09-04 22:25:25 +07:00
|
|
|
{ PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
|
|
|
|
|
{ PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
|
|
|
|
|
{ PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
|
|
|
|
|
{ PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
|
2011-11-09 13:47:36 +07:00
|
|
|
|
2013-01-05 05:39:09 +07:00
|
|
|
/* Enmotus */
|
|
|
|
|
{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
|
|
|
|
|
|
2006-11-01 17:10:42 +07:00
|
|
|
/* Generic, PCI class code for AHCI */
|
|
|
|
|
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
2007-01-09 17:32:51 +07:00
|
|
|
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
|
2006-11-01 17:10:42 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
{ } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static struct pci_driver ahci_pci_driver = {
|
|
|
|
|
.name = DRV_NAME,
|
|
|
|
|
.id_table = ahci_pci_tbl,
|
|
|
|
|
.probe = ahci_init_one,
|
2007-01-20 14:00:28 +07:00
|
|
|
.remove = ata_pci_remove_one,
|
2007-03-02 15:31:26 +07:00
|
|
|
#ifdef CONFIG_PM
|
2006-07-26 13:59:26 +07:00
|
|
|
.suspend = ahci_pci_device_suspend,
|
2010-03-28 11:22:14 +07:00
|
|
|
.resume = ahci_pci_device_resume,
|
|
|
|
|
#endif
|
|
|
|
|
};
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
|
|
|
|
|
static int marvell_enable;
|
|
|
|
|
#else
|
|
|
|
|
static int marvell_enable = 1;
|
|
|
|
|
#endif
|
|
|
|
|
module_param(marvell_enable, int, 0644);
|
|
|
|
|
MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
|
2008-07-05 11:10:50 +07:00
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
static void ahci_pci_save_initial_config(struct pci_dev *pdev,
|
|
|
|
|
struct ahci_host_priv *hpriv)
|
|
|
|
|
{
|
|
|
|
|
unsigned int force_port_map = 0;
|
|
|
|
|
unsigned int mask_port_map = 0;
|
2005-10-05 13:58:32 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
|
|
|
|
|
dev_info(&pdev->dev, "JMB361 has only one port\n");
|
|
|
|
|
force_port_map = 1;
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/*
|
|
|
|
|
* Temporary Marvell 6145 hack: PATA port presence
|
|
|
|
|
* is asserted through the standard AHCI port
|
|
|
|
|
* presence register, as bit 4 (counting from 0)
|
2008-07-05 11:10:50 +07:00
|
|
|
*/
|
2010-03-28 11:22:14 +07:00
|
|
|
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
|
|
|
|
|
if (pdev->device == 0x6121)
|
|
|
|
|
mask_port_map = 0x3;
|
|
|
|
|
else
|
|
|
|
|
mask_port_map = 0xf;
|
|
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
|
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
|
|
|
|
|
mask_port_map);
|
2005-04-17 05:20:36 +07:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
static int ahci_pci_reset_controller(struct ata_host *host)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2010-03-28 11:22:14 +07:00
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
2007-09-23 11:19:54 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_reset_controller(host);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
|
|
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
|
u16 tmp16;
|
2009-12-09 16:23:04 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/* configure PCS */
|
|
|
|
|
pci_read_config_word(pdev, 0x92, &tmp16);
|
|
|
|
|
if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
|
|
|
|
|
tmp16 |= hpriv->port_map;
|
|
|
|
|
pci_write_config_word(pdev, 0x92, tmp16);
|
|
|
|
|
}
|
2009-12-09 16:23:04 +07:00
|
|
|
}
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
static void ahci_pci_init_controller(struct ata_host *host)
|
2006-05-15 18:58:29 +07:00
|
|
|
{
|
2010-03-28 11:22:14 +07:00
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
|
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
|
void __iomem *port_mmio;
|
2006-05-15 18:58:29 +07:00
|
|
|
u32 tmp;
|
2010-03-28 11:22:14 +07:00
|
|
|
int mv;
|
2006-05-15 18:58:29 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
|
|
|
|
|
if (pdev->device == 0x6121)
|
|
|
|
|
mv = 2;
|
|
|
|
|
else
|
|
|
|
|
mv = 4;
|
|
|
|
|
port_mmio = __ahci_port_base(host, mv);
|
2006-05-15 18:58:29 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
writel(0, port_mmio + PORT_IRQ_MASK);
|
2006-05-15 18:58:29 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/* clear port IRQ */
|
|
|
|
|
tmp = readl(port_mmio + PORT_IRQ_STAT);
|
|
|
|
|
VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
|
|
|
|
|
if (tmp)
|
|
|
|
|
writel(tmp, port_mmio + PORT_IRQ_STAT);
|
2006-05-15 18:58:29 +07:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_init_controller(host);
|
2007-10-25 12:59:16 +07:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
|
|
|
|
|
unsigned long deadline)
|
2009-12-09 16:23:04 +07:00
|
|
|
{
|
2010-03-28 11:22:14 +07:00
|
|
|
struct ata_port *ap = link->ap;
|
|
|
|
|
bool online;
|
2009-12-09 16:23:04 +07:00
|
|
|
int rc;
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
DPRINTK("ENTER\n");
|
2009-12-09 16:23:04 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_stop_engine(ap);
|
2009-12-09 16:23:04 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
|
|
|
|
|
deadline, &online, NULL);
|
2009-12-09 16:23:04 +07:00
|
|
|
|
|
|
|
|
ahci_start_engine(ap);
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
|
2009-12-09 16:23:04 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/* vt8251 doesn't clear BSY on signature FIS reception,
|
|
|
|
|
* request follow-up softreset.
|
|
|
|
|
*/
|
|
|
|
|
return online ? -EAGAIN : rc;
|
2007-09-23 11:19:54 +07:00
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
|
|
|
|
|
unsigned long deadline)
|
2007-09-23 11:19:54 +07:00
|
|
|
{
|
2010-03-28 11:22:14 +07:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-10-09 13:01:37 +07:00
|
|
|
struct ahci_port_priv *pp = ap->private_data;
|
2010-03-28 11:22:14 +07:00
|
|
|
u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
|
|
|
|
|
struct ata_taskfile tf;
|
|
|
|
|
bool online;
|
|
|
|
|
int rc;
|
2007-09-23 11:19:54 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_stop_engine(ap);
|
2007-07-18 02:48:48 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/* clear D2H reception area to properly wait for D2H FIS */
|
|
|
|
|
ata_tf_init(link->device, &tf);
|
|
|
|
|
tf.command = 0x80;
|
|
|
|
|
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
|
2007-09-23 11:19:54 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
|
|
|
|
|
deadline, &online, NULL);
|
2007-07-18 02:48:48 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
ahci_start_engine(ap);
|
2006-07-26 13:59:26 +07:00
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
/* The pseudo configuration device on SIMG4726 attached to
|
|
|
|
|
* ASUS P5W-DH Deluxe doesn't send signature FIS after
|
|
|
|
|
* hardreset if no device is attached to the first downstream
|
|
|
|
|
* port && the pseudo device locks up on SRST w/ PMP==0. To
|
|
|
|
|
* work around this, wait for !BSY only briefly. If BSY isn't
|
|
|
|
|
* cleared, perform CLO and proceed to IDENTIFY (achieved by
|
|
|
|
|
* ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
|
|
|
|
|
*
|
|
|
|
|
* Wait for two seconds. Devices attached to downstream port
|
|
|
|
|
* which can't process the following IDENTIFY after this will
|
|
|
|
|
* have to be reset again. For most cases, this should
|
|
|
|
|
* suffice while making probing snappish enough.
|
|
|
|
|
*/
|
|
|
|
|
if (online) {
|
|
|
|
|
rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
|
|
|
|
|
ahci_check_ready);
|
|
|
|
|
if (rc)
|
|
|
|
|
ahci_kick_engine(ap);
|
2006-07-26 13:59:26 +07:00
|
|
|
}
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-28 11:22:14 +07:00
|
|
|
#ifdef CONFIG_PM
|
2006-07-26 13:59:26 +07:00
|
|
|
static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
|
|
|
|
|
{
|
2006-08-24 14:19:22 +07:00
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
2009-05-30 18:50:12 +07:00
|
|
|
struct ahci_host_priv *hpriv = host->private_data;
|
2010-03-04 00:17:34 +07:00
|
|
|
void __iomem *mmio = hpriv->mmio;
|
2006-07-26 13:59:26 +07:00
|
|
|
u32 ctl;
|
|
|
|
|
|
2009-05-30 18:50:12 +07:00
|
|
|
if (mesg.event & PM_EVENT_SUSPEND &&
|
|
|
|
|
hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"BIOS update required for suspend/resume\n");
|
2009-05-30 18:50:12 +07:00
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-24 01:13:25 +07:00
|
|
|
if (mesg.event & PM_EVENT_SLEEP) {
|
2006-07-26 13:59:26 +07:00
|
|
|
/* AHCI spec rev1.1 section 8.3.3:
|
|
|
|
|
* Software must disable interrupts prior to requesting a
|
|
|
|
|
* transition of the HBA to D3 state.
|
|
|
|
|
*/
|
|
|
|
|
ctl = readl(mmio + HOST_CTL);
|
|
|
|
|
ctl &= ~HOST_IRQ_EN;
|
|
|
|
|
writel(ctl, mmio + HOST_CTL);
|
|
|
|
|
readl(mmio + HOST_CTL); /* flush */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ata_pci_device_suspend(pdev, mesg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ahci_pci_device_resume(struct pci_dev *pdev)
|
|
|
|
|
{
|
2006-08-24 14:19:22 +07:00
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
2006-07-26 13:59:26 +07:00
|
|
|
int rc;
|
|
|
|
|
|
2006-12-26 17:39:50 +07:00
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
2006-07-26 13:59:26 +07:00
|
|
|
|
|
|
|
|
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
|
2010-03-04 00:17:39 +07:00
|
|
|
rc = ahci_pci_reset_controller(host);
|
2006-07-26 13:59:26 +07:00
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
2010-03-04 00:17:42 +07:00
|
|
|
ahci_pci_init_controller(host);
|
2006-07-26 13:59:26 +07:00
|
|
|
}
|
|
|
|
|
|
2006-08-24 14:19:22 +07:00
|
|
|
ata_host_resume(host);
|
2006-07-26 13:59:26 +07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2007-03-02 15:31:26 +07:00
|
|
|
#endif
|
2006-07-26 13:59:26 +07:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
|
2012-01-06 19:33:39 +07:00
|
|
|
/*
|
|
|
|
|
* If the device fixup already set the dma_mask to some non-standard
|
|
|
|
|
* value, don't extend it here. This happens on STA2X11, for example.
|
|
|
|
|
*/
|
|
|
|
|
if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
|
|
|
|
|
return 0;
|
|
|
|
|
|
2005-04-17 05:20:36 +07:00
|
|
|
if (using_dac &&
|
2009-04-07 09:01:13 +07:00
|
|
|
!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
|
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc) {
|
2009-04-07 09:01:15 +07:00
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc) {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"64-bit DMA enable failed\n");
|
2005-04-17 05:20:36 +07:00
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} else {
|
2009-04-07 09:01:15 +07:00
|
|
|
rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc) {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_err(&pdev->dev, "32-bit DMA enable failed\n");
|
2005-04-17 05:20:36 +07:00
|
|
|
return rc;
|
|
|
|
|
}
|
2009-04-07 09:01:15 +07:00
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc) {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"32-bit consistent DMA enable failed\n");
|
2005-04-17 05:20:36 +07:00
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2010-03-04 00:17:43 +07:00
|
|
|
static void ahci_pci_print_info(struct ata_host *host)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
|
u16 cc;
|
|
|
|
|
const char *scc_s;
|
|
|
|
|
|
|
|
|
|
pci_read_config_word(pdev, 0x0a, &cc);
|
|
|
|
|
if (cc == PCI_CLASS_STORAGE_IDE)
|
|
|
|
|
scc_s = "IDE";
|
|
|
|
|
else if (cc == PCI_CLASS_STORAGE_SATA)
|
|
|
|
|
scc_s = "SATA";
|
|
|
|
|
else if (cc == PCI_CLASS_STORAGE_RAID)
|
|
|
|
|
scc_s = "RAID";
|
|
|
|
|
else
|
|
|
|
|
scc_s = "unknown";
|
|
|
|
|
|
|
|
|
|
ahci_print_info(host, scc_s);
|
|
|
|
|
}
|
|
|
|
|
|
2007-10-25 12:59:16 +07:00
|
|
|
/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
|
|
|
|
|
* hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
|
|
|
|
|
* support PMP and the 4726 either directly exports the device
|
|
|
|
|
* attached to the first downstream port or acts as a hardware storage
|
|
|
|
|
* controller and emulate a single ATA device (can be RAID 0/1 or some
|
|
|
|
|
* other configuration).
|
|
|
|
|
*
|
|
|
|
|
* When there's no device attached to the first downstream port of the
|
|
|
|
|
* 4726, "Config Disk" appears, which is a pseudo ATA device to
|
|
|
|
|
* configure the 4726. However, ATA emulation of the device is very
|
|
|
|
|
* lame. It doesn't send signature D2H Reg FIS after the initial
|
|
|
|
|
* hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
|
|
|
|
|
*
|
|
|
|
|
* The following function works around the problem by always using
|
|
|
|
|
* hardreset on the port and not depending on receiving signature FIS
|
|
|
|
|
* afterward. If signature FIS isn't received soon, ATA class is
|
|
|
|
|
* assumed without follow-up softreset.
|
|
|
|
|
*/
|
|
|
|
|
static void ahci_p5wdh_workaround(struct ata_host *host)
|
|
|
|
|
{
|
|
|
|
|
static struct dmi_system_id sysids[] = {
|
|
|
|
|
{
|
|
|
|
|
.ident = "P5W DH Deluxe",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR,
|
|
|
|
|
"ASUSTEK COMPUTER INC"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{ }
|
|
|
|
|
};
|
|
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
|
|
|
|
|
|
|
|
|
if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
|
|
|
|
|
dmi_check_system(sysids)) {
|
|
|
|
|
struct ata_port *ap = host->ports[1];
|
|
|
|
|
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
|
2007-10-25 12:59:16 +07:00
|
|
|
|
|
|
|
|
ap->ops = &ahci_p5wdh_ops;
|
|
|
|
|
ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-03 16:27:29 +07:00
|
|
|
/* only some SB600 ahci controllers can do 64bit DMA */
|
|
|
|
|
static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
|
2009-05-27 14:04:43 +07:00
|
|
|
{
|
|
|
|
|
static const struct dmi_system_id sysids[] = {
|
2009-08-16 19:04:02 +07:00
|
|
|
/*
|
|
|
|
|
* The oldest version known to be broken is 0901 and
|
|
|
|
|
* working is 1501 which was released on 2007-10-26.
|
2009-10-03 16:27:29 +07:00
|
|
|
* Enable 64bit DMA on 1501 and anything newer.
|
|
|
|
|
*
|
2009-08-16 19:04:02 +07:00
|
|
|
* Please read bko#9412 for more info.
|
|
|
|
|
*/
|
2009-05-27 14:04:43 +07:00
|
|
|
{
|
|
|
|
|
.ident = "ASUS M2A-VM",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"ASUSTeK Computer INC."),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
|
|
|
|
|
},
|
2009-08-16 19:04:02 +07:00
|
|
|
.driver_data = "20071026", /* yyyymmdd */
|
2009-05-27 14:04:43 +07:00
|
|
|
},
|
2009-11-03 16:06:48 +07:00
|
|
|
/*
|
|
|
|
|
* All BIOS versions for the MSI K9A2 Platinum (MS-7376)
|
|
|
|
|
* support 64bit DMA.
|
|
|
|
|
*
|
|
|
|
|
* BIOS versions earlier than 1.5 had the Manufacturer DMI
|
|
|
|
|
* fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
|
|
|
|
|
* This spelling mistake was fixed in BIOS version 1.5, so
|
|
|
|
|
* 1.5 and later have the Manufacturer as
|
|
|
|
|
* "MICRO-STAR INTERNATIONAL CO.,LTD".
|
|
|
|
|
* So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
|
|
|
|
|
*
|
|
|
|
|
* BIOS versions earlier than 1.9 had a Board Product Name
|
|
|
|
|
* DMI field of "MS-7376". This was changed to be
|
|
|
|
|
* "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
|
|
|
|
|
* match on DMI_BOARD_NAME of "MS-7376".
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "MSI K9A2 Platinum",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"MICRO-STAR INTER"),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2012-06-28 09:32:14 +07:00
|
|
|
/*
|
|
|
|
|
* All BIOS versions for the MSI K9AGM2 (MS-7327) support
|
|
|
|
|
* 64bit DMA.
|
|
|
|
|
*
|
|
|
|
|
* This board also had the typo mentioned above in the
|
|
|
|
|
* Manufacturer DMI field (fixed in BIOS version 1.5), so
|
|
|
|
|
* match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "MSI K9AGM2",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"MICRO-STAR INTER"),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2011-06-27 13:33:44 +07:00
|
|
|
/*
|
|
|
|
|
* All BIOS versions for the Asus M3A support 64bit DMA.
|
|
|
|
|
* (all release versions from 0301 to 1206 were tested)
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "ASUS M3A",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"ASUSTeK Computer INC."),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "M3A"),
|
|
|
|
|
},
|
|
|
|
|
},
|
2009-05-27 14:04:43 +07:00
|
|
|
{ }
|
|
|
|
|
};
|
2009-08-16 19:04:02 +07:00
|
|
|
const struct dmi_system_id *match;
|
2009-10-03 16:27:29 +07:00
|
|
|
int year, month, date;
|
|
|
|
|
char buf[9];
|
2009-05-27 14:04:43 +07:00
|
|
|
|
2009-08-16 19:04:02 +07:00
|
|
|
match = dmi_first_match(sysids);
|
2009-05-27 14:04:43 +07:00
|
|
|
if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
|
2009-08-16 19:04:02 +07:00
|
|
|
!match)
|
2009-05-27 14:04:43 +07:00
|
|
|
return false;
|
|
|
|
|
|
2009-11-03 16:06:48 +07:00
|
|
|
if (!match->driver_data)
|
|
|
|
|
goto enable_64bit;
|
|
|
|
|
|
2009-10-03 16:27:29 +07:00
|
|
|
dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
|
|
|
|
|
snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
|
2009-08-16 19:04:02 +07:00
|
|
|
|
2009-11-03 16:06:48 +07:00
|
|
|
if (strcmp(buf, match->driver_data) >= 0)
|
|
|
|
|
goto enable_64bit;
|
|
|
|
|
else {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
|
"%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
|
|
|
|
|
match->ident);
|
2009-10-03 16:27:29 +07:00
|
|
|
return false;
|
|
|
|
|
}
|
2009-11-03 16:06:48 +07:00
|
|
|
|
|
|
|
|
enable_64bit:
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
|
2009-11-03 16:06:48 +07:00
|
|
|
return true;
|
2009-05-27 14:04:43 +07:00
|
|
|
}
|
|
|
|
|
|
2009-01-20 02:57:36 +07:00
|
|
|
static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
static const struct dmi_system_id broken_systems[] = {
|
|
|
|
|
{
|
|
|
|
|
.ident = "HP Compaq nx6310",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
|
|
|
|
|
},
|
|
|
|
|
/* PCI slot number of the controller */
|
|
|
|
|
.driver_data = (void *)0x1FUL,
|
|
|
|
|
},
|
2009-03-20 06:06:46 +07:00
|
|
|
{
|
|
|
|
|
.ident = "HP Compaq 6720s",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
|
|
|
|
|
},
|
|
|
|
|
/* PCI slot number of the controller */
|
|
|
|
|
.driver_data = (void *)0x1FUL,
|
|
|
|
|
},
|
2009-01-20 02:57:36 +07:00
|
|
|
|
|
|
|
|
{ } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
|
|
|
|
|
|
|
|
|
|
if (dmi) {
|
|
|
|
|
unsigned long slot = (unsigned long)dmi->driver_data;
|
|
|
|
|
/* apply the quirk only to on-board controllers */
|
|
|
|
|
return slot == PCI_SLOT(pdev->devfn);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2009-05-30 18:50:12 +07:00
|
|
|
static bool ahci_broken_suspend(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
static const struct dmi_system_id sysids[] = {
|
|
|
|
|
/*
|
|
|
|
|
* On HP dv[4-6] and HDX18 with earlier BIOSen, link
|
|
|
|
|
* to the harddisk doesn't become online after
|
|
|
|
|
* resuming from STR. Warn and fail suspend.
|
2010-03-16 07:50:26 +07:00
|
|
|
*
|
|
|
|
|
* http://bugzilla.kernel.org/show_bug.cgi?id=12276
|
|
|
|
|
*
|
|
|
|
|
* Use dates instead of versions to match as HP is
|
|
|
|
|
* apparently recycling both product and version
|
|
|
|
|
* strings.
|
|
|
|
|
*
|
|
|
|
|
* http://bugzilla.kernel.org/show_bug.cgi?id=15462
|
2009-05-30 18:50:12 +07:00
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "dv4",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME,
|
|
|
|
|
"HP Pavilion dv4 Notebook PC"),
|
|
|
|
|
},
|
2010-03-16 07:50:26 +07:00
|
|
|
.driver_data = "20090105", /* F.30 */
|
2009-05-30 18:50:12 +07:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.ident = "dv5",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME,
|
|
|
|
|
"HP Pavilion dv5 Notebook PC"),
|
|
|
|
|
},
|
2010-03-16 07:50:26 +07:00
|
|
|
.driver_data = "20090506", /* F.16 */
|
2009-05-30 18:50:12 +07:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.ident = "dv6",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME,
|
|
|
|
|
"HP Pavilion dv6 Notebook PC"),
|
|
|
|
|
},
|
2010-03-16 07:50:26 +07:00
|
|
|
.driver_data = "20090423", /* F.21 */
|
2009-05-30 18:50:12 +07:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.ident = "HDX18",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME,
|
|
|
|
|
"HP HDX18 Notebook PC"),
|
|
|
|
|
},
|
2010-03-16 07:50:26 +07:00
|
|
|
.driver_data = "20090430", /* F.23 */
|
2009-05-30 18:50:12 +07:00
|
|
|
},
|
2010-01-28 14:04:15 +07:00
|
|
|
/*
|
|
|
|
|
* Acer eMachines G725 has the same problem. BIOS
|
|
|
|
|
* V1.03 is known to be broken. V3.04 is known to
|
2011-03-31 08:57:33 +07:00
|
|
|
* work. Between, there are V1.06, V2.06 and V3.03
|
2010-01-28 14:04:15 +07:00
|
|
|
* that we don't have much idea about. For now,
|
|
|
|
|
* blacklist anything older than V3.04.
|
2010-03-16 07:50:26 +07:00
|
|
|
*
|
|
|
|
|
* http://bugzilla.kernel.org/show_bug.cgi?id=15104
|
2010-01-28 14:04:15 +07:00
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "G725",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
|
|
|
|
|
},
|
2010-03-16 07:50:26 +07:00
|
|
|
.driver_data = "20091216", /* V3.04 */
|
2010-01-28 14:04:15 +07:00
|
|
|
},
|
2009-05-30 18:50:12 +07:00
|
|
|
{ } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
const struct dmi_system_id *dmi = dmi_first_match(sysids);
|
2010-03-16 07:50:26 +07:00
|
|
|
int year, month, date;
|
|
|
|
|
char buf[9];
|
2009-05-30 18:50:12 +07:00
|
|
|
|
|
|
|
|
if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
|
|
|
|
|
return false;
|
|
|
|
|
|
2010-03-16 07:50:26 +07:00
|
|
|
dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
|
|
|
|
|
snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
|
2009-05-30 18:50:12 +07:00
|
|
|
|
2010-03-16 07:50:26 +07:00
|
|
|
return strcmp(buf, dmi->driver_data) < 0;
|
2009-05-30 18:50:12 +07:00
|
|
|
}
|
|
|
|
|
|
2009-08-04 12:30:08 +07:00
|
|
|
static bool ahci_broken_online(struct pci_dev *pdev)
|
|
|
|
|
{
|
|
|
|
|
#define ENCODE_BUSDEVFN(bus, slot, func) \
|
|
|
|
|
(void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
|
|
|
|
|
static const struct dmi_system_id sysids[] = {
|
|
|
|
|
/*
|
|
|
|
|
* There are several gigabyte boards which use
|
|
|
|
|
* SIMG5723s configured as hardware RAID. Certain
|
|
|
|
|
* 5723 firmware revisions shipped there keep the link
|
|
|
|
|
* online but fail to answer properly to SRST or
|
|
|
|
|
* IDENTIFY when no device is attached downstream
|
|
|
|
|
* causing libata to retry quite a few times leading
|
|
|
|
|
* to excessive detection delay.
|
|
|
|
|
*
|
|
|
|
|
* As these firmwares respond to the second reset try
|
|
|
|
|
* with invalid device signature, considering unknown
|
|
|
|
|
* sig as offline works around the problem acceptably.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "EP45-DQ6",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"Gigabyte Technology Co., Ltd."),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
|
|
|
|
|
},
|
|
|
|
|
.driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.ident = "EP45-DS5",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_BOARD_VENDOR,
|
|
|
|
|
"Gigabyte Technology Co., Ltd."),
|
|
|
|
|
DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
|
|
|
|
|
},
|
|
|
|
|
.driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
|
|
|
|
|
},
|
|
|
|
|
{ } /* terminate list */
|
|
|
|
|
};
|
|
|
|
|
#undef ENCODE_BUSDEVFN
|
|
|
|
|
const struct dmi_system_id *dmi = dmi_first_match(sysids);
|
|
|
|
|
unsigned int val;
|
|
|
|
|
|
|
|
|
|
if (!dmi)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
val = (unsigned long)dmi->driver_data;
|
|
|
|
|
|
|
|
|
|
return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
|
|
|
|
|
}
|
|
|
|
|
|
2009-10-09 10:41:47 +07:00
|
|
|
#ifdef CONFIG_ATA_ACPI
|
2009-09-16 02:18:03 +07:00
|
|
|
static void ahci_gtf_filter_workaround(struct ata_host *host)
|
|
|
|
|
{
|
|
|
|
|
static const struct dmi_system_id sysids[] = {
|
|
|
|
|
/*
|
|
|
|
|
* Aspire 3810T issues a bunch of SATA enable commands
|
|
|
|
|
* via _GTF including an invalid one and one which is
|
|
|
|
|
* rejected by the device. Among the successful ones
|
|
|
|
|
* is FPDMA non-zero offset enable which when enabled
|
|
|
|
|
* only on the drive side leads to NCQ command
|
|
|
|
|
* failures. Filter it out.
|
|
|
|
|
*/
|
|
|
|
|
{
|
|
|
|
|
.ident = "Aspire 3810T",
|
|
|
|
|
.matches = {
|
|
|
|
|
DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
|
|
|
|
|
DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
|
|
|
|
|
},
|
|
|
|
|
.driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
|
|
|
|
|
},
|
|
|
|
|
{ }
|
|
|
|
|
};
|
|
|
|
|
const struct dmi_system_id *dmi = dmi_first_match(sysids);
|
|
|
|
|
unsigned int filter;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (!dmi)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
filter = (unsigned long)dmi->driver_data;
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
|
|
|
|
|
filter, dmi->ident);
|
2009-09-16 02:18:03 +07:00
|
|
|
|
|
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
|
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
|
struct ata_link *link;
|
|
|
|
|
struct ata_device *dev;
|
|
|
|
|
|
|
|
|
|
ata_for_each_link(link, ap, EDGE)
|
|
|
|
|
ata_for_each_dev(dev, link, ALL)
|
|
|
|
|
dev->gtf_filter |= filter;
|
|
|
|
|
}
|
|
|
|
|
}
|
2009-10-09 10:41:47 +07:00
|
|
|
#else
|
|
|
|
|
static inline void ahci_gtf_filter_workaround(struct ata_host *host)
|
|
|
|
|
{}
|
|
|
|
|
#endif
|
2009-09-16 02:18:03 +07:00
|
|
|
|
2012-11-19 22:02:48 +07:00
|
|
|
int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
|
|
|
|
|
{
|
|
|
|
|
int rc;
|
|
|
|
|
unsigned int maxvec;
|
|
|
|
|
|
|
|
|
|
if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
|
|
|
|
|
rc = pci_enable_msi_block_auto(pdev, &maxvec);
|
|
|
|
|
if (rc > 0) {
|
|
|
|
|
if ((rc == maxvec) || (rc == 1))
|
|
|
|
|
return rc;
|
|
|
|
|
/*
|
|
|
|
|
* Assume that advantage of multipe MSIs is negated,
|
|
|
|
|
* so fallback to single MSI mode to save resources
|
|
|
|
|
*/
|
|
|
|
|
pci_disable_msi(pdev);
|
|
|
|
|
if (!pci_enable_msi(pdev))
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
pci_intx(pdev, 1);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* ahci_host_activate - start AHCI host, request IRQs and register it
|
|
|
|
|
* @host: target ATA host
|
|
|
|
|
* @irq: base IRQ number to request
|
|
|
|
|
* @n_msis: number of MSIs allocated for this host
|
|
|
|
|
* @irq_handler: irq_handler used when requesting IRQs
|
|
|
|
|
* @irq_flags: irq_flags used when requesting IRQs
|
|
|
|
|
*
|
|
|
|
|
* Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
|
|
|
|
|
* when multiple MSIs were allocated. That is one MSI per port, starting
|
|
|
|
|
* from @irq.
|
|
|
|
|
*
|
|
|
|
|
* LOCKING:
|
|
|
|
|
* Inherited from calling layer (may sleep).
|
|
|
|
|
*
|
|
|
|
|
* RETURNS:
|
|
|
|
|
* 0 on success, -errno otherwise.
|
|
|
|
|
*/
|
|
|
|
|
int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
|
|
|
|
|
{
|
|
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
|
|
/* Sharing Last Message among several ports is not supported */
|
|
|
|
|
if (n_msis < host->n_ports)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
rc = ata_host_start(host);
|
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
|
|
|
|
rc = devm_request_threaded_irq(host->dev,
|
|
|
|
|
irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
|
|
|
|
|
dev_driver_string(host->dev), host->ports[i]);
|
|
|
|
|
if (rc)
|
|
|
|
|
goto out_free_irqs;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < host->n_ports; i++)
|
|
|
|
|
ata_port_desc(host->ports[i], "irq %d", irq + i);
|
|
|
|
|
|
|
|
|
|
rc = ata_host_register(host, &ahci_sht);
|
|
|
|
|
if (rc)
|
|
|
|
|
goto out_free_all_irqs;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
out_free_all_irqs:
|
|
|
|
|
i = host->n_ports;
|
|
|
|
|
out_free_irqs:
|
|
|
|
|
for (i--; i >= 0; i--)
|
|
|
|
|
devm_free_irq(host->dev, irq + i, host->ports[i]);
|
|
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
|
2007-01-20 14:00:28 +07:00
|
|
|
static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
2005-04-17 05:20:36 +07:00
|
|
|
{
|
2008-06-09 22:13:04 +07:00
|
|
|
unsigned int board_id = ent->driver_data;
|
|
|
|
|
struct ata_port_info pi = ahci_port_info[board_id];
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
const struct ata_port_info *ppi[] = { &pi, NULL };
|
2007-01-20 14:00:28 +07:00
|
|
|
struct device *dev = &pdev->dev;
|
2005-04-17 05:20:36 +07:00
|
|
|
struct ahci_host_priv *hpriv;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
struct ata_host *host;
|
2012-11-19 22:02:48 +07:00
|
|
|
int n_ports, n_msis, i, rc;
|
2012-01-06 19:33:39 +07:00
|
|
|
int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
|
2010-07-03 21:29:25 +07:00
|
|
|
WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
|
2006-05-15 19:03:55 +07:00
|
|
|
|
2011-04-16 05:52:00 +07:00
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2008-09-03 20:48:34 +07:00
|
|
|
/* The AHCI driver can only drive the SATA ports, the PATA driver
|
|
|
|
|
can drive them all so if both drivers are selected make sure
|
|
|
|
|
AHCI stays out of the way */
|
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2010-06-17 16:42:22 +07:00
|
|
|
/*
|
|
|
|
|
* For some reason, MCP89 on MacBook 7,1 doesn't work with
|
|
|
|
|
* ahci, use ata_generic instead.
|
|
|
|
|
*/
|
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
|
|
|
|
|
pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
|
|
|
|
|
pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
|
|
|
|
|
pdev->subsystem_device == 0xcb89)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2009-11-22 08:07:41 +07:00
|
|
|
/* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
|
|
|
|
|
* At the moment, we can only use the AHCI mode. Let the users know
|
|
|
|
|
* that for SAS drives they're out of luck.
|
|
|
|
|
*/
|
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"PDC42819 can only drive SATA devices with this driver\n");
|
2009-11-22 08:07:41 +07:00
|
|
|
|
2013-01-05 05:39:09 +07:00
|
|
|
/* Both Connext and Enmotus devices use non-standard BARs */
|
2012-01-06 19:33:39 +07:00
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
|
|
|
|
|
ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
|
2013-01-05 05:39:09 +07:00
|
|
|
else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
|
|
|
|
|
ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
|
2012-01-06 19:33:39 +07:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
/* acquire resources */
|
2007-01-20 14:00:28 +07:00
|
|
|
rc = pcim_enable_device(pdev);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
2008-03-11 17:52:31 +07:00
|
|
|
/* AHCI controllers often implement SFF compatible interface.
|
|
|
|
|
* Grab all PCI BARs just in case.
|
|
|
|
|
*/
|
2012-01-06 19:33:39 +07:00
|
|
|
rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
|
2007-02-01 13:06:36 +07:00
|
|
|
if (rc == -EBUSY)
|
2007-01-20 14:00:28 +07:00
|
|
|
pcim_pin_device(pdev);
|
2007-02-01 13:06:36 +07:00
|
|
|
if (rc)
|
2007-01-20 14:00:28 +07:00
|
|
|
return rc;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2007-12-06 13:09:43 +07:00
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
|
|
|
|
|
(pdev->device == 0x2652 || pdev->device == 0x2653)) {
|
|
|
|
|
u8 map;
|
|
|
|
|
|
|
|
|
|
/* ICH6s share the same PCI ID for both piix and ahci
|
|
|
|
|
* modes. Enabling ahci mode while MAP indicates
|
|
|
|
|
* combined mode is a bad idea. Yield to ata_piix.
|
|
|
|
|
*/
|
|
|
|
|
pci_read_config_byte(pdev, ICH_MAP, &map);
|
|
|
|
|
if (map & 0x3) {
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"controller is in combined mode, can't enable AHCI mode\n");
|
2007-12-06 13:09:43 +07:00
|
|
|
return -ENODEV;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2007-01-20 14:00:28 +07:00
|
|
|
hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
|
|
|
|
|
if (!hpriv)
|
|
|
|
|
return -ENOMEM;
|
2007-09-23 11:19:55 +07:00
|
|
|
hpriv->flags |= (unsigned long)pi.private_data;
|
|
|
|
|
|
2008-06-09 22:13:04 +07:00
|
|
|
/* MCP65 revision A1 and A2 can't do MSI */
|
|
|
|
|
if (board_id == board_ahci_mcp65 &&
|
|
|
|
|
(pdev->revision == 0xa1 || pdev->revision == 0xa2))
|
|
|
|
|
hpriv->flags |= AHCI_HFLAG_NO_MSI;
|
|
|
|
|
|
2008-12-30 09:53:41 +07:00
|
|
|
/* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
|
|
|
|
|
if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
|
|
|
|
|
hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
|
|
|
|
|
|
2009-10-03 16:27:29 +07:00
|
|
|
/* only some SB600s can do 64bit DMA */
|
|
|
|
|
if (ahci_sb600_enable_64bit(pdev))
|
|
|
|
|
hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
|
2009-05-27 14:04:43 +07:00
|
|
|
|
2012-01-06 19:33:39 +07:00
|
|
|
hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
|
2010-03-04 00:17:34 +07:00
|
|
|
|
2012-11-19 22:02:48 +07:00
|
|
|
n_msis = ahci_init_interrupts(pdev, hpriv);
|
|
|
|
|
if (n_msis > 1)
|
|
|
|
|
hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
|
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
/* save initial config */
|
2010-03-04 00:17:36 +07:00
|
|
|
ahci_pci_save_initial_config(pdev, hpriv);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
/* prepare host */
|
2010-01-27 11:33:23 +07:00
|
|
|
if (hpriv->cap & HOST_CAP_NCQ) {
|
|
|
|
|
pi.flags |= ATA_FLAG_NCQ;
|
2010-03-30 08:28:32 +07:00
|
|
|
/*
|
|
|
|
|
* Auto-activate optimization is supposed to be
|
|
|
|
|
* supported on all AHCI controllers indicating NCQ
|
|
|
|
|
* capability, but it seems to be broken on some
|
|
|
|
|
* chipsets including NVIDIAs.
|
|
|
|
|
*/
|
|
|
|
|
if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
|
2010-01-27 11:33:23 +07:00
|
|
|
pi.flags |= ATA_FLAG_FPDMA_AA;
|
|
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2007-09-23 11:19:54 +07:00
|
|
|
if (hpriv->cap & HOST_CAP_PMP)
|
|
|
|
|
pi.flags |= ATA_FLAG_PMP;
|
|
|
|
|
|
2010-03-04 00:17:45 +07:00
|
|
|
ahci_set_em_messages(hpriv, &pi);
|
2008-06-04 00:33:55 +07:00
|
|
|
|
2009-01-20 02:57:36 +07:00
|
|
|
if (ahci_broken_system_poweroff(pdev)) {
|
|
|
|
|
pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
|
|
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"quirky BIOS, skipping spindown on poweroff\n");
|
|
|
|
|
}
|
|
|
|
|
|
2009-05-30 18:50:12 +07:00
|
|
|
if (ahci_broken_suspend(pdev)) {
|
|
|
|
|
hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
|
2011-04-16 05:51:58 +07:00
|
|
|
dev_warn(&pdev->dev,
|
|
|
|
|
"BIOS update required for suspend/resume\n");
|
2009-05-30 18:50:12 +07:00
|
|
|
}
|
|
|
|
|
|
2009-08-04 12:30:08 +07:00
|
|
|
if (ahci_broken_online(pdev)) {
|
|
|
|
|
hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
|
|
|
|
|
dev_info(&pdev->dev,
|
|
|
|
|
"online status unreliable, applying workaround\n");
|
|
|
|
|
}
|
|
|
|
|
|
2008-02-06 13:13:51 +07:00
|
|
|
/* CAP.NP sometimes indicate the index of the last enabled
|
|
|
|
|
* port, at other times, that of the last possible port, so
|
|
|
|
|
* determining the maximum port number requires looking at
|
|
|
|
|
* both CAP.NP and port_map.
|
|
|
|
|
*/
|
|
|
|
|
n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
|
|
|
|
|
|
|
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
if (!host)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
host->private_data = hpriv;
|
|
|
|
|
|
2009-01-26 17:05:44 +07:00
|
|
|
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
|
2009-01-10 06:54:07 +07:00
|
|
|
host->flags |= ATA_HOST_PARALLEL_SCAN;
|
2009-01-26 17:05:44 +07:00
|
|
|
else
|
|
|
|
|
printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
|
2009-01-10 06:54:07 +07:00
|
|
|
|
2008-06-04 00:33:55 +07:00
|
|
|
if (pi.flags & ATA_FLAG_EM)
|
|
|
|
|
ahci_reset_em(host);
|
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
for (i = 0; i < host->n_ports; i++) {
|
2007-05-28 19:33:01 +07:00
|
|
|
struct ata_port *ap = host->ports[i];
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
|
2012-01-06 19:33:39 +07:00
|
|
|
ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
|
|
|
|
|
ata_port_pbar_desc(ap, ahci_pci_bar,
|
2007-08-18 11:14:55 +07:00
|
|
|
0x100 + ap->port_no * 0x80, "port");
|
|
|
|
|
|
2008-06-04 00:33:55 +07:00
|
|
|
/* set enclosure management message type */
|
|
|
|
|
if (ap->flags & ATA_FLAG_EM)
|
2010-04-23 16:27:19 +07:00
|
|
|
ap->em_message_type = hpriv->em_msg_type;
|
2008-06-04 00:33:55 +07:00
|
|
|
|
|
|
|
|
|
2007-05-28 19:33:01 +07:00
|
|
|
/* disabled/not-implemented port */
|
2008-04-07 20:47:21 +07:00
|
|
|
if (!(hpriv->port_map & (1 << i)))
|
2007-05-28 19:33:01 +07:00
|
|
|
ap->ops = &ata_dummy_port_ops;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
}
|
2007-03-18 20:15:33 +07:00
|
|
|
|
2007-10-25 12:59:16 +07:00
|
|
|
/* apply workaround for ASUS P5W DH Deluxe mainboard */
|
|
|
|
|
ahci_p5wdh_workaround(host);
|
|
|
|
|
|
2009-09-16 02:18:03 +07:00
|
|
|
/* apply gtf filter quirk */
|
|
|
|
|
ahci_gtf_filter_workaround(host);
|
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
/* initialize adapter */
|
|
|
|
|
rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
|
2005-04-17 05:20:36 +07:00
|
|
|
if (rc)
|
2007-01-20 14:00:28 +07:00
|
|
|
return rc;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-04 00:17:39 +07:00
|
|
|
rc = ahci_pci_reset_controller(host);
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2010-03-04 00:17:42 +07:00
|
|
|
ahci_pci_init_controller(host);
|
2010-03-04 00:17:43 +07:00
|
|
|
ahci_pci_print_info(host);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
pci_set_master(pdev);
|
2012-11-19 22:02:48 +07:00
|
|
|
|
|
|
|
|
if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
|
|
|
|
|
return ahci_host_activate(host, pdev->irq, n_msis);
|
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 21:44:08 +07:00
|
|
|
return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
|
|
|
|
|
&ahci_sht);
|
2005-05-13 02:03:42 +07:00
|
|
|
}
|
2005-04-17 05:20:36 +07:00
|
|
|
|
2012-04-19 12:43:05 +07:00
|
|
|
module_pci_driver(ahci_pci_driver);
|
2005-04-17 05:20:36 +07:00
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Jeff Garzik");
|
|
|
|
|
MODULE_DESCRIPTION("AHCI SATA low-level driver");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
|
2005-08-23 13:53:51 +07:00
|
|
|
MODULE_VERSION(DRV_VERSION);
|