License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 21:07:57 +07:00
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// SPDX-License-Identifier: GPL-2.0
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2014-03-07 23:56:59 +07:00
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/dts-v1/;
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2018-08-03 21:10:15 +07:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2014-03-07 23:56:59 +07:00
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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2015-03-13 15:01:08 +07:00
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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2018-08-03 21:10:15 +07:00
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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2014-03-07 23:56:59 +07:00
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#include <dt-bindings/soc/qcom,gsbi.h>
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2018-06-20 16:23:39 +07:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2014-03-07 23:56:59 +07:00
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/ {
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2019-01-09 23:26:14 +07:00
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#address-cells = <1>;
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#size-cells = <1>;
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2014-03-07 23:56:59 +07:00
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model = "Qualcomm IPQ8064";
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compatible = "qcom,ipq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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2019-01-09 23:26:14 +07:00
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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2014-03-07 23:56:59 +07:00
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cpu-pmu {
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compatible = "qcom,krait-pmu";
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2018-06-20 16:23:39 +07:00
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interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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2014-03-07 23:56:59 +07:00
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nss@40000000 {
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reg = <0x40000000 0x1000000>;
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no-map;
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};
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smem@41000000 {
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reg = <0x41000000 0x200000>;
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no-map;
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};
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};
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2015-02-21 09:19:35 +07:00
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clocks {
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2016-01-07 08:41:51 +07:00
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cxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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2016-11-10 08:13:57 +07:00
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clock-frequency = <25000000>;
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2016-01-07 08:41:51 +07:00
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};
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pxo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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2016-11-10 08:13:57 +07:00
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clock-frequency = <25000000>;
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2016-01-07 08:41:51 +07:00
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};
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2015-02-21 09:19:35 +07:00
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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};
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2014-03-07 23:56:59 +07:00
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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2015-03-13 15:01:08 +07:00
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lpass@28100000 {
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compatible = "qcom,lpass-cpu";
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status = "disabled";
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clocks = <&lcc AHBIX_CLK>,
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<&lcc MI2S_OSR_CLK>,
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<&lcc MI2S_BIT_CLK>;
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clock-names = "ahbix-clk",
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"mi2s-osr-clk",
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"mi2s-bit-clk";
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2018-06-20 16:23:39 +07:00
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interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
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2015-03-13 15:01:08 +07:00
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interrupt-names = "lpass-irq-lpaif";
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reg = <0x28100000 0x10000>;
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reg-names = "lpass-lpaif";
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};
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2014-03-07 23:56:59 +07:00
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qcom_pinmux: pinmux@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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2018-06-20 16:23:39 +07:00
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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2018-08-03 21:10:15 +07:00
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pcie0_pins: pcie0_pinmux {
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mux {
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pins = "gpio3";
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function = "pcie1_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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pcie1_pins: pcie1_pinmux {
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mux {
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pins = "gpio48";
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function = "pcie2_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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pcie2_pins: pcie2_pinmux {
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mux {
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pins = "gpio63";
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function = "pcie3_rst";
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drive-strength = <12>;
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bias-disable;
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};
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};
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2018-08-03 21:10:17 +07:00
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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function = "gsbi5";
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drive-strength = <10>;
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bias-none;
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};
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};
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2018-08-03 21:10:19 +07:00
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leds_pins: leds_pins {
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mux {
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pins = "gpio7", "gpio8", "gpio9",
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"gpio26", "gpio53";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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output-low;
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};
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};
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buttons_pins: buttons_pins {
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mux {
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pins = "gpio54";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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2014-03-07 23:56:59 +07:00
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x02000000 0x1000>,
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<0x02002000 0x1000>;
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};
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timer@200a000 {
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2016-06-30 00:50:00 +07:00
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compatible = "qcom,kpss-timer",
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"qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
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2018-06-20 16:23:39 +07:00
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>,
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<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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2014-03-07 23:56:59 +07:00
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>,
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<32768>;
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2015-02-21 09:19:35 +07:00
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clocks = <&sleep_clk>;
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clock-names = "sleep";
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2014-03-07 23:56:59 +07:00
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cpu-offset = <0x80000>;
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};
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acc0: clock-controller@2088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
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};
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acc1: clock-controller@2098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
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};
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saw0: regulator@2089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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saw1: regulator@2099000 {
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compatible = "qcom,saw2";
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reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
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regulator;
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};
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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2015-02-10 05:01:09 +07:00
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cell-index = <2>;
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2014-03-07 23:56:59 +07:00
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reg = <0x12480000 0x100>;
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clocks = <&gcc GSBI2_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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2015-02-10 05:01:09 +07:00
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syscon-tcsr = <&tcsr>;
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|
|
2014-03-07 23:56:59 +07:00
|
|
|
serial@12490000 {
|
|
|
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
|
|
|
reg = <0x12490000 0x1000>,
|
|
|
|
|
<0x12480000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@124a0000 {
|
|
|
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
|
|
|
reg = <0x124a0000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
|
|
|
|
|
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gsbi4: gsbi@16300000 {
|
|
|
|
|
compatible = "qcom,gsbi-v1.0.0";
|
2015-02-10 05:01:09 +07:00
|
|
|
cell-index = <4>;
|
2014-03-07 23:56:59 +07:00
|
|
|
reg = <0x16300000 0x100>;
|
|
|
|
|
clocks = <&gcc GSBI4_H_CLK>;
|
|
|
|
|
clock-names = "iface";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
2015-02-10 05:01:09 +07:00
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
|
|
2015-06-17 04:31:44 +07:00
|
|
|
gsbi4_serial: serial@16340000 {
|
2014-03-07 23:56:59 +07:00
|
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
|
|
|
reg = <0x16340000 0x1000>,
|
|
|
|
|
<0x16300000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@16380000 {
|
|
|
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
|
|
|
reg = <0x16380000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
|
|
|
|
|
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gsbi5: gsbi@1a200000 {
|
|
|
|
|
compatible = "qcom,gsbi-v1.0.0";
|
2015-02-10 05:01:09 +07:00
|
|
|
cell-index = <5>;
|
2014-03-07 23:56:59 +07:00
|
|
|
reg = <0x1a200000 0x100>;
|
|
|
|
|
clocks = <&gcc GSBI5_H_CLK>;
|
|
|
|
|
clock-names = "iface";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
2015-02-10 05:01:09 +07:00
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
|
|
2014-03-07 23:56:59 +07:00
|
|
|
serial@1a240000 {
|
|
|
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
|
|
|
reg = <0x1a240000 0x1000>,
|
|
|
|
|
<0x1a200000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@1a280000 {
|
|
|
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
|
|
|
reg = <0x1a280000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
|
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi@1a280000 {
|
|
|
|
|
compatible = "qcom,spi-qup-v1.1.1";
|
|
|
|
|
reg = <0x1a280000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
2014-03-07 23:56:59 +07:00
|
|
|
|
|
|
|
|
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2017-04-28 17:10:36 +07:00
|
|
|
gsbi7: gsbi@16600000 {
|
|
|
|
|
status = "disabled";
|
|
|
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
|
|
|
cell-index = <7>;
|
|
|
|
|
reg = <0x16600000 0x100>;
|
|
|
|
|
clocks = <&gcc GSBI7_H_CLK>;
|
|
|
|
|
clock-names = "iface";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
|
|
|
|
|
|
gsbi7_serial: serial@16640000 {
|
|
|
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
|
|
|
reg = <0x16640000 0x1000>,
|
|
|
|
|
<0x16600000 0x1000>;
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
2017-04-28 17:10:36 +07:00
|
|
|
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
|
|
|
|
|
clock-names = "core", "iface";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-24 01:21:41 +07:00
|
|
|
sata_phy: sata-phy@1b400000 {
|
|
|
|
|
compatible = "qcom,ipq806x-sata-phy";
|
|
|
|
|
reg = <0x1b400000 0x200>;
|
|
|
|
|
|
|
|
|
|
clocks = <&gcc SATA_PHY_CFG_CLK>;
|
|
|
|
|
clock-names = "cfg";
|
|
|
|
|
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sata@29000000 {
|
|
|
|
|
compatible = "qcom,ipq806x-ahci", "generic-ahci";
|
|
|
|
|
reg = <0x29000000 0x180>;
|
|
|
|
|
|
2018-06-20 16:23:39 +07:00
|
|
|
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
2014-09-24 01:21:41 +07:00
|
|
|
|
|
|
|
|
clocks = <&gcc SFAB_SATA_S_H_CLK>,
|
|
|
|
|
<&gcc SATA_H_CLK>,
|
|
|
|
|
<&gcc SATA_A_CLK>,
|
|
|
|
|
<&gcc SATA_RXOOB_CLK>,
|
|
|
|
|
<&gcc SATA_PMALIVE_CLK>;
|
|
|
|
|
clock-names = "slave_face", "iface", "core",
|
|
|
|
|
"rxoob", "pmalive";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
|
|
|
|
|
assigned-clock-rates = <100000000>, <100000000>;
|
|
|
|
|
|
|
|
|
|
phys = <&sata_phy>;
|
|
|
|
|
phy-names = "sata-phy";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2014-03-07 23:56:59 +07:00
|
|
|
qcom,ssbi@500000 {
|
|
|
|
|
compatible = "qcom,ssbi";
|
|
|
|
|
reg = <0x00500000 0x1000>;
|
|
|
|
|
qcom,controller-type = "pmic-arbiter";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gcc: clock-controller@900000 {
|
|
|
|
|
compatible = "qcom,gcc-ipq8064";
|
|
|
|
|
reg = <0x00900000 0x4000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
2015-02-10 05:01:09 +07:00
|
|
|
|
|
|
|
|
tcsr: syscon@1a400000 {
|
|
|
|
|
compatible = "qcom,tcsr-ipq8064", "syscon";
|
|
|
|
|
reg = <0x1a400000 0x100>;
|
|
|
|
|
};
|
2015-01-29 04:36:12 +07:00
|
|
|
|
|
|
|
|
lcc: clock-controller@28000000 {
|
|
|
|
|
compatible = "qcom,lcc-ipq8064";
|
|
|
|
|
reg = <0x28000000 0x1000>;
|
|
|
|
|
#clock-cells = <1>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
2018-08-03 21:10:15 +07:00
|
|
|
pcie0: pci@1b500000 {
|
|
|
|
|
compatible = "qcom,pcie-ipq8064";
|
|
|
|
|
reg = <0x1b500000 0x1000
|
|
|
|
|
0x1b502000 0x80
|
|
|
|
|
0x1b600000 0x100
|
|
|
|
|
0x0ff00000 0x100000>;
|
|
|
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
linux,pci-domain = <0>;
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
|
|
ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
|
|
|
|
|
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
|
|
|
|
|
|
|
|
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "msi";
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
|
|
|
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
|
|
|
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
|
|
|
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
|
|
|
|
|
|
clocks = <&gcc PCIE_A_CLK>,
|
|
|
|
|
<&gcc PCIE_H_CLK>,
|
|
|
|
|
<&gcc PCIE_PHY_CLK>,
|
|
|
|
|
<&gcc PCIE_AUX_CLK>,
|
|
|
|
|
<&gcc PCIE_ALT_REF_CLK>;
|
|
|
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
|
|
|
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
|
|
|
|
|
|
resets = <&gcc PCIE_ACLK_RESET>,
|
|
|
|
|
<&gcc PCIE_HCLK_RESET>,
|
|
|
|
|
<&gcc PCIE_POR_RESET>,
|
|
|
|
|
<&gcc PCIE_PCI_RESET>,
|
|
|
|
|
<&gcc PCIE_PHY_RESET>,
|
|
|
|
|
<&gcc PCIE_EXT_RESET>;
|
|
|
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
|
|
|
|
|
|
pinctrl-0 = <&pcie0_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie1: pci@1b700000 {
|
|
|
|
|
compatible = "qcom,pcie-ipq8064";
|
|
|
|
|
reg = <0x1b700000 0x1000
|
|
|
|
|
0x1b702000 0x80
|
|
|
|
|
0x1b800000 0x100
|
|
|
|
|
0x31f00000 0x100000>;
|
|
|
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
linux,pci-domain = <1>;
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
|
|
ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
|
|
|
|
|
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
|
|
|
|
|
|
|
|
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "msi";
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
|
|
|
<0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
|
|
|
<0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
|
|
|
<0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
|
|
|
|
|
|
clocks = <&gcc PCIE_1_A_CLK>,
|
|
|
|
|
<&gcc PCIE_1_H_CLK>,
|
|
|
|
|
<&gcc PCIE_1_PHY_CLK>,
|
|
|
|
|
<&gcc PCIE_1_AUX_CLK>,
|
|
|
|
|
<&gcc PCIE_1_ALT_REF_CLK>;
|
|
|
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
|
|
|
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
|
|
|
|
|
|
resets = <&gcc PCIE_1_ACLK_RESET>,
|
|
|
|
|
<&gcc PCIE_1_HCLK_RESET>,
|
|
|
|
|
<&gcc PCIE_1_POR_RESET>,
|
|
|
|
|
<&gcc PCIE_1_PCI_RESET>,
|
|
|
|
|
<&gcc PCIE_1_PHY_RESET>,
|
|
|
|
|
<&gcc PCIE_1_EXT_RESET>;
|
|
|
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
|
|
|
|
|
|
pinctrl-0 = <&pcie1_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie2: pci@1b900000 {
|
|
|
|
|
compatible = "qcom,pcie-ipq8064";
|
|
|
|
|
reg = <0x1b900000 0x1000
|
|
|
|
|
0x1b902000 0x80
|
|
|
|
|
0x1ba00000 0x100
|
|
|
|
|
0x35f00000 0x100000>;
|
|
|
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
linux,pci-domain = <2>;
|
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
|
num-lanes = <1>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
|
|
|
|
|
ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
|
|
|
|
|
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
|
|
|
|
|
|
|
|
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "msi";
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
|
|
|
interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
|
|
|
<0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
|
|
|
<0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
|
|
|
<0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
|
|
|
|
|
|
clocks = <&gcc PCIE_2_A_CLK>,
|
|
|
|
|
<&gcc PCIE_2_H_CLK>,
|
|
|
|
|
<&gcc PCIE_2_PHY_CLK>,
|
|
|
|
|
<&gcc PCIE_2_AUX_CLK>,
|
|
|
|
|
<&gcc PCIE_2_ALT_REF_CLK>;
|
|
|
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
|
|
|
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
|
|
|
|
|
|
resets = <&gcc PCIE_2_ACLK_RESET>,
|
|
|
|
|
<&gcc PCIE_2_HCLK_RESET>,
|
|
|
|
|
<&gcc PCIE_2_POR_RESET>,
|
|
|
|
|
<&gcc PCIE_2_PCI_RESET>,
|
|
|
|
|
<&gcc PCIE_2_PHY_RESET>,
|
|
|
|
|
<&gcc PCIE_2_EXT_RESET>;
|
|
|
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
|
|
|
|
|
|
|
|
pinctrl-0 = <&pcie2_pins>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
|
|
|
|
|
};
|
2018-08-03 21:10:16 +07:00
|
|
|
|
|
|
|
|
vsdcc_fixed: vsdcc-regulator {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "SDCC Power";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdcc1bam:dma@12402000 {
|
|
|
|
|
compatible = "qcom,bam-v1.3.0";
|
|
|
|
|
reg = <0x12402000 0x8000>;
|
|
|
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&gcc SDC1_H_CLK>;
|
|
|
|
|
clock-names = "bam_clk";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
qcom,ee = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdcc3bam:dma@12182000 {
|
|
|
|
|
compatible = "qcom,bam-v1.3.0";
|
|
|
|
|
reg = <0x12182000 0x8000>;
|
|
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&gcc SDC3_H_CLK>;
|
|
|
|
|
clock-names = "bam_clk";
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
qcom,ee = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
amba {
|
|
|
|
|
compatible = "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
sdcc@12400000 {
|
|
|
|
|
status = "disabled";
|
|
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
arm,primecell-periphid = <0x00051180>;
|
|
|
|
|
reg = <0x12400000 0x2000>;
|
|
|
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cmd_irq";
|
|
|
|
|
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
|
|
|
|
clock-names = "mclk", "apb_pclk";
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
max-frequency = <96000000>;
|
|
|
|
|
non-removable;
|
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
|
mmc-ddr-1_8v;
|
|
|
|
|
vmmc-supply = <&vsdcc_fixed>;
|
|
|
|
|
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sdcc@12180000 {
|
|
|
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
|
|
|
arm,primecell-periphid = <0x00051180>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
reg = <0x12180000 0x2000>;
|
|
|
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-names = "cmd_irq";
|
|
|
|
|
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
|
|
|
|
clock-names = "mclk", "apb_pclk";
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
cap-sd-highspeed;
|
|
|
|
|
cap-mmc-highspeed;
|
|
|
|
|
max-frequency = <192000000>;
|
|
|
|
|
#mmc-ddr-1_8v;
|
|
|
|
|
sd-uhs-sdr104;
|
|
|
|
|
sd-uhs-ddr50;
|
|
|
|
|
vqmmc-supply = <&vsdcc_fixed>;
|
|
|
|
|
dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
|
|
|
|
};
|
2014-03-07 23:56:59 +07:00
|
|
|
};
|
|
|
|
|
};
|