2018-08-07 14:08:36 +07:00
|
|
|
// SPDX-License-Identifier: GPL-2.0 OR X11
|
2017-01-02 20:40:20 +07:00
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2016 Amarula Solutions B.V.
|
|
|
|
|
* Copyright (C) 2016 Engicam S.r.l.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
|
#include "imx6ul.dtsi"
|
|
|
|
|
|
|
|
|
|
/ {
|
2018-01-24 20:22:14 +07:00
|
|
|
memory@80000000 {
|
2018-11-20 22:59:43 +07:00
|
|
|
device_type = "memory";
|
2017-01-02 20:40:20 +07:00
|
|
|
reg = <0x80000000 0x20000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
chosen {
|
|
|
|
|
stdout-path = &uart1;
|
|
|
|
|
};
|
2017-03-24 23:18:37 +07:00
|
|
|
|
|
|
|
|
backlight {
|
|
|
|
|
compatible = "pwm-backlight";
|
|
|
|
|
pwms = <&pwm8 0 100000>;
|
|
|
|
|
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
|
|
|
|
|
10 11 12 13 14 15 16 17 18 19
|
|
|
|
|
20 21 22 23 24 25 26 27 28 29
|
|
|
|
|
30 31 32 33 34 35 36 37 38 39
|
|
|
|
|
40 41 42 43 44 45 46 47 48 49
|
|
|
|
|
50 51 52 53 54 55 56 57 58 59
|
|
|
|
|
60 61 62 63 64 65 66 67 68 69
|
|
|
|
|
70 71 72 73 74 75 76 77 78 79
|
|
|
|
|
80 81 82 83 84 85 86 87 88 89
|
|
|
|
|
90 91 92 93 94 95 96 97 98 99
|
|
|
|
|
100>;
|
|
|
|
|
default-brightness-level = <100>;
|
|
|
|
|
};
|
2017-06-15 19:03:38 +07:00
|
|
|
|
|
|
|
|
reg_1p8v: regulator-1p8v {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "1P8V";
|
|
|
|
|
regulator-min-microvolt = <1800000>;
|
|
|
|
|
regulator-max-microvolt = <1800000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
reg_3p3v: regulator-3p3v {
|
|
|
|
|
compatible = "regulator-fixed";
|
|
|
|
|
regulator-name = "3P3V";
|
|
|
|
|
regulator-min-microvolt = <3300000>;
|
|
|
|
|
regulator-max-microvolt = <3300000>;
|
|
|
|
|
regulator-always-on;
|
|
|
|
|
regulator-boot-on;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sound {
|
|
|
|
|
compatible = "simple-audio-card";
|
|
|
|
|
simple-audio-card,name = "imx6ul-isiot-sgtl5000";
|
|
|
|
|
simple-audio-card,format = "i2s";
|
|
|
|
|
simple-audio-card,bitclock-master = <&dailink_master>;
|
|
|
|
|
simple-audio-card,frame-master = <&dailink_master>;
|
|
|
|
|
simple-audio-card,widgets =
|
|
|
|
|
"Microphone", "Mic Jack",
|
|
|
|
|
"Line", "Line In",
|
|
|
|
|
"Line", "Line Out",
|
|
|
|
|
"Headphone", "Headphone Jack";
|
|
|
|
|
simple-audio-card,routing =
|
|
|
|
|
"MIC_IN", "Mic Jack",
|
|
|
|
|
"Mic Jack", "Mic Bias",
|
|
|
|
|
"Headphone Jack", "HP_OUT";
|
|
|
|
|
|
|
|
|
|
simple-audio-card,cpu {
|
|
|
|
|
sound-dai = <&sai2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dailink_master: simple-audio-card,codec {
|
|
|
|
|
sound-dai = <&sgtl5000>;
|
|
|
|
|
clocks = <&clks IMX6UL_CLK_SAI2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2017-03-24 23:18:37 +07:00
|
|
|
};
|
|
|
|
|
|
2017-06-15 19:03:39 +07:00
|
|
|
&fec1 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_enet1>;
|
|
|
|
|
phy-mode = "rmii";
|
|
|
|
|
phy-handle = <ðphy0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
mdio {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
ethphy0: ethernet-phy@0 {
|
|
|
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2018-08-07 14:08:37 +07:00
|
|
|
&gpmi {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_gpmi_nand>;
|
|
|
|
|
nand-on-flash-bbt;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:39 +07:00
|
|
|
&i2c1 {
|
|
|
|
|
clock-frequency = <100000>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
|
|
|
status = "okay";
|
2017-06-15 19:03:37 +07:00
|
|
|
|
2017-06-15 19:03:38 +07:00
|
|
|
sgtl5000: codec@a {
|
|
|
|
|
compatible = "fsl,sgtl5000";
|
|
|
|
|
reg = <0x0a>;
|
2018-03-16 01:29:29 +07:00
|
|
|
#sound-dai-cells = <0>;
|
2017-06-15 19:03:38 +07:00
|
|
|
clocks = <&clks IMX6UL_CLK_OSC>;
|
|
|
|
|
clock-names = "mclk";
|
|
|
|
|
VDDA-supply = <®_3p3v>;
|
|
|
|
|
VDDIO-supply = <®_3p3v>;
|
|
|
|
|
VDDD-supply = <®_1p8v>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 19:03:37 +07:00
|
|
|
stmpe811: gpio-expander@44 {
|
|
|
|
|
compatible = "st,stmpe811";
|
|
|
|
|
reg = <0x44>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_stmpe>;
|
|
|
|
|
interrupt-parent = <&gpio1>;
|
|
|
|
|
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
|
|
|
|
|
stmpe: touchscreen {
|
|
|
|
|
compatible = "st,stmpe-ts";
|
|
|
|
|
st,sample-time = <4>;
|
|
|
|
|
st,mod-12b = <1>;
|
|
|
|
|
st,ref-sel = <0>;
|
|
|
|
|
st,adc-freq = <1>;
|
|
|
|
|
st,ave-ctrl = <1>;
|
|
|
|
|
st,touch-det-delay = <2>;
|
|
|
|
|
st,settling = <2>;
|
|
|
|
|
st,fraction-z = <7>;
|
|
|
|
|
st,i-drive = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2017-03-24 23:18:39 +07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&i2c2 {
|
|
|
|
|
clock_frequency = <100000>;
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_i2c2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 19:03:37 +07:00
|
|
|
&lcdif {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_lcdif_dat
|
|
|
|
|
&pinctrl_lcdif_ctrl>;
|
|
|
|
|
display = <&display0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
|
|
|
|
|
display0: display {
|
|
|
|
|
bits-per-pixel = <16>;
|
|
|
|
|
bus-width = <18>;
|
|
|
|
|
|
|
|
|
|
display-timings {
|
|
|
|
|
native-mode = <&timing0>;
|
|
|
|
|
timing0: timing0 {
|
|
|
|
|
clock-frequency = <28000000>;
|
|
|
|
|
hactive = <800>;
|
|
|
|
|
vactive = <480>;
|
|
|
|
|
hfront-porch = <30>;
|
|
|
|
|
hback-porch = <30>;
|
|
|
|
|
hsync-len = <64>;
|
|
|
|
|
vback-porch = <5>;
|
|
|
|
|
vfront-porch = <5>;
|
|
|
|
|
vsync-len = <20>;
|
|
|
|
|
hsync-active = <0>;
|
|
|
|
|
vsync-active = <0>;
|
|
|
|
|
de-active = <1>;
|
|
|
|
|
pixelclk-active = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:37 +07:00
|
|
|
&pwm8 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_pwm8>;
|
|
|
|
|
status = "okay";
|
2017-01-02 20:40:20 +07:00
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:41 +07:00
|
|
|
&sai2 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_sai2>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-02 20:40:20 +07:00
|
|
|
&uart1 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&usdhc1 {
|
|
|
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
|
|
|
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
|
|
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
|
|
|
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
no-1-8-v;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2018-08-07 14:08:37 +07:00
|
|
|
&usdhc2 {
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
|
|
|
|
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
|
|
|
|
|
bus-width = <8>;
|
|
|
|
|
no-1-8-v;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-02 20:40:20 +07:00
|
|
|
&iomuxc {
|
2017-06-15 19:03:39 +07:00
|
|
|
pinctrl_enet1: enet1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
|
|
|
|
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
|
|
|
|
|
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2018-08-07 14:08:38 +07:00
|
|
|
pinctrl_gpmi_nand: gpminandgrp {
|
2018-08-07 14:08:37 +07:00
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
|
|
|
|
|
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
|
|
|
|
|
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:39 +07:00
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
|
|
|
|
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
|
|
|
|
|
MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 19:03:37 +07:00
|
|
|
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
|
|
|
|
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
|
|
|
|
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
|
|
|
|
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_lcdif_dat: lcdifdatgrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
|
|
|
|
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:37 +07:00
|
|
|
pinctrl_pwm8: pwm8grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-03-24 23:18:41 +07:00
|
|
|
pinctrl_sai2: sai2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
|
|
|
|
|
MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
|
|
|
|
|
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
|
|
|
|
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
|
|
|
|
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-06-15 19:03:37 +07:00
|
|
|
pinctrl_stmpe: stmpegrp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-02 20:40:20 +07:00
|
|
|
pinctrl_uart1: uart1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
|
|
|
|
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
|
|
|
|
>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
|
|
|
|
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
|
|
|
|
>;
|
|
|
|
|
};
|
2018-08-07 14:08:37 +07:00
|
|
|
|
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
|
|
|
fsl,pins = <
|
|
|
|
|
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
|
|
|
|
|
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
|
|
|
|
|
MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
|
|
|
|
|
>;
|
|
|
|
|
};
|
2017-01-02 20:40:20 +07:00
|
|
|
};
|
